1*fcc337cfSVijayenthiran Subramaniam /* 2*fcc337cfSVijayenthiran Subramaniam * Copyright (c) 2019, ARM Limited. All rights reserved. 3*fcc337cfSVijayenthiran Subramaniam * 4*fcc337cfSVijayenthiran Subramaniam * SPDX-License-Identifier: BSD-3-Clause 5*fcc337cfSVijayenthiran Subramaniam */ 6*fcc337cfSVijayenthiran Subramaniam 7*fcc337cfSVijayenthiran Subramaniam #ifndef GIC600_MULTICHIP_PRIVATE_H 8*fcc337cfSVijayenthiran Subramaniam #define GIC600_MULTICHIP_PRIVATE_H 9*fcc337cfSVijayenthiran Subramaniam 10*fcc337cfSVijayenthiran Subramaniam #include <drivers/arm/gic600_multichip.h> 11*fcc337cfSVijayenthiran Subramaniam 12*fcc337cfSVijayenthiran Subramaniam #include "gicv3_private.h" 13*fcc337cfSVijayenthiran Subramaniam 14*fcc337cfSVijayenthiran Subramaniam /* GIC600 GICD multichip related offsets */ 15*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPSR U(0xC000) 16*fcc337cfSVijayenthiran Subramaniam #define GICD_DCHIPR U(0xC004) 17*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPR U(0xC008) 18*fcc337cfSVijayenthiran Subramaniam 19*fcc337cfSVijayenthiran Subramaniam /* GIC600 GICD multichip related masks */ 20*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPRx_PUP_BIT BIT_64(1) 21*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPRx_SOCKET_STATE BIT_64(0) 22*fcc337cfSVijayenthiran Subramaniam #define GICD_DCHIPR_PUP_BIT BIT_32(0) 23*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPSR_RTS_MASK (BIT_32(4) | BIT_32(5)) 24*fcc337cfSVijayenthiran Subramaniam 25*fcc337cfSVijayenthiran Subramaniam /* GIC600 GICD multichip related shifts */ 26*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPRx_ADDR_SHIFT 16 27*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10 28*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5 29*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPSR_RTS_SHIFT 4 30*fcc337cfSVijayenthiran Subramaniam #define GICD_DCHIPR_RT_OWNER_SHIFT 4 31*fcc337cfSVijayenthiran Subramaniam 32*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0) 33*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPSR_RTS_STATE_UPDATING U(1) 34*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2) 35*fcc337cfSVijayenthiran Subramaniam 36*fcc337cfSVijayenthiran Subramaniam /* SPI interrupt id minimum and maximum range */ 37*fcc337cfSVijayenthiran Subramaniam #define GIC600_SPI_ID_MIN 32 38*fcc337cfSVijayenthiran Subramaniam #define GIC600_SPI_ID_MAX 960 39*fcc337cfSVijayenthiran Subramaniam 40*fcc337cfSVijayenthiran Subramaniam /* Number of retries for PUP update */ 41*fcc337cfSVijayenthiran Subramaniam #define GICD_PUP_UPDATE_RETRIES 10000 42*fcc337cfSVijayenthiran Subramaniam 43*fcc337cfSVijayenthiran Subramaniam #define SPI_MIN_INDEX 0 44*fcc337cfSVijayenthiran Subramaniam #define SPI_MAX_INDEX 1 45*fcc337cfSVijayenthiran Subramaniam 46*fcc337cfSVijayenthiran Subramaniam #define SPI_BLOCK_MIN_VALUE(spi_id_min) \ 47*fcc337cfSVijayenthiran Subramaniam (((spi_id_min) - GIC600_SPI_ID_MIN) / \ 48*fcc337cfSVijayenthiran Subramaniam GIC600_SPI_ID_MIN) 49*fcc337cfSVijayenthiran Subramaniam #define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \ 50*fcc337cfSVijayenthiran Subramaniam (((spi_id_max) - (spi_id_min) + 1) / \ 51*fcc337cfSVijayenthiran Subramaniam GIC600_SPI_ID_MIN) 52*fcc337cfSVijayenthiran Subramaniam #define GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks) \ 53*fcc337cfSVijayenthiran Subramaniam (((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \ 54*fcc337cfSVijayenthiran Subramaniam ((spi_block_min) << GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT) | \ 55*fcc337cfSVijayenthiran Subramaniam ((spi_blocks) << GICD_CHIPRx_SPI_BLOCKS_SHIFT)) 56*fcc337cfSVijayenthiran Subramaniam 57*fcc337cfSVijayenthiran Subramaniam /* 58*fcc337cfSVijayenthiran Subramaniam * Multichip data assertion macros 59*fcc337cfSVijayenthiran Subramaniam */ 60*fcc337cfSVijayenthiran Subramaniam /* Set bits from 0 to ((spi_id_max + 1) / 32) */ 61*fcc337cfSVijayenthiran Subramaniam #define SPI_BLOCKS_TILL_MAX(spi_id_max) ((1 << (((spi_id_max) + 1) >> 5)) - 1) 62*fcc337cfSVijayenthiran Subramaniam /* Set bits from 0 to (spi_id_min / 32) */ 63*fcc337cfSVijayenthiran Subramaniam #define SPI_BLOCKS_TILL_MIN(spi_id_min) ((1 << ((spi_id_min) >> 5)) - 1) 64*fcc337cfSVijayenthiran Subramaniam /* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */ 65*fcc337cfSVijayenthiran Subramaniam #define BLOCKS_OF_32(spi_id_min, spi_id_max) \ 66*fcc337cfSVijayenthiran Subramaniam SPI_BLOCKS_TILL_MAX(spi_id_max) ^ \ 67*fcc337cfSVijayenthiran Subramaniam SPI_BLOCKS_TILL_MIN(spi_id_min) 68*fcc337cfSVijayenthiran Subramaniam 69*fcc337cfSVijayenthiran Subramaniam /******************************************************************************* 70*fcc337cfSVijayenthiran Subramaniam * GIC-600 multichip operation related helper functions 71*fcc337cfSVijayenthiran Subramaniam ******************************************************************************/ 72*fcc337cfSVijayenthiran Subramaniam static inline uint32_t read_gicd_dchipr(uintptr_t base) 73*fcc337cfSVijayenthiran Subramaniam { 74*fcc337cfSVijayenthiran Subramaniam return mmio_read_32(base + GICD_DCHIPR); 75*fcc337cfSVijayenthiran Subramaniam } 76*fcc337cfSVijayenthiran Subramaniam 77*fcc337cfSVijayenthiran Subramaniam static inline uint64_t read_gicd_chipr_n(uintptr_t base, uint8_t n) 78*fcc337cfSVijayenthiran Subramaniam { 79*fcc337cfSVijayenthiran Subramaniam return mmio_read_64(base + (GICD_CHIPR + (8U * n))); 80*fcc337cfSVijayenthiran Subramaniam } 81*fcc337cfSVijayenthiran Subramaniam 82*fcc337cfSVijayenthiran Subramaniam static inline uint32_t read_gicd_chipsr(uintptr_t base) 83*fcc337cfSVijayenthiran Subramaniam { 84*fcc337cfSVijayenthiran Subramaniam return mmio_read_32(base + GICD_CHIPSR); 85*fcc337cfSVijayenthiran Subramaniam } 86*fcc337cfSVijayenthiran Subramaniam 87*fcc337cfSVijayenthiran Subramaniam static inline void write_gicd_dchipr(uintptr_t base, uint32_t val) 88*fcc337cfSVijayenthiran Subramaniam { 89*fcc337cfSVijayenthiran Subramaniam mmio_write_32(base + GICD_DCHIPR, val); 90*fcc337cfSVijayenthiran Subramaniam } 91*fcc337cfSVijayenthiran Subramaniam 92*fcc337cfSVijayenthiran Subramaniam static inline void write_gicd_chipr_n(uintptr_t base, uint8_t n, uint64_t val) 93*fcc337cfSVijayenthiran Subramaniam { 94*fcc337cfSVijayenthiran Subramaniam mmio_write_64(base + (GICD_CHIPR + (8U * n)), val); 95*fcc337cfSVijayenthiran Subramaniam } 96*fcc337cfSVijayenthiran Subramaniam 97*fcc337cfSVijayenthiran Subramaniam #endif /* GIC600_MULTICHIP_PRIVATE_H */ 98