1 /* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * Copyright (c) 2022-2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * GIC-600 driver extension for multichip setup 10 */ 11 12 #include <assert.h> 13 14 #include <common/debug.h> 15 #include <drivers/arm/arm_gicv3_common.h> 16 #include <drivers/arm/gic600_multichip.h> 17 #include <drivers/arm/gicv3.h> 18 19 #include "../common/gic_common_private.h" 20 #include "gic600_multichip_private.h" 21 22 static struct gic600_multichip_data *plat_gic_multichip_data; 23 24 /******************************************************************************* 25 * Retrieve the address of the chip owner for a given SPI ID 26 ******************************************************************************/ 27 uintptr_t gic600_multichip_gicd_base_for_spi(uint32_t spi_id) 28 { 29 unsigned int i; 30 31 /* Find the multichip instance */ 32 for (i = 0U; i < GIC600_MAX_MULTICHIP; i++) { 33 if ((spi_id <= plat_gic_multichip_data->spi_ids[i].spi_id_max) && 34 (spi_id >= plat_gic_multichip_data->spi_ids[i].spi_id_min)) { 35 break; 36 } 37 } 38 39 /* Ensure that plat_gic_multichip_data contains valid values */ 40 assert(i < GIC600_MAX_MULTICHIP); 41 42 return plat_gic_multichip_data->spi_ids[i].gicd_base; 43 } 44 45 /******************************************************************************* 46 * GIC-600 multichip operation related helper functions 47 ******************************************************************************/ 48 static void gicd_dchipr_wait_for_power_update_progress(uintptr_t base) 49 { 50 unsigned int retry = GICD_PUP_UPDATE_RETRIES; 51 52 while ((read_gicd_dchipr(base) & GICD_DCHIPR_PUP_BIT) != 0U) { 53 if (retry-- == 0U) { 54 ERROR("GIC-600 connection to Routing Table Owner timed " 55 "out\n"); 56 panic(); 57 } 58 } 59 } 60 61 /******************************************************************************* 62 * Sets up the routing table owner. 63 ******************************************************************************/ 64 static void set_gicd_dchipr_rt_owner(uintptr_t base, unsigned int rt_owner) 65 { 66 /* 67 * Ensure that Group enables in GICD_CTLR are disabled and no pending 68 * register writes to GICD_CTLR. 69 */ 70 if ((gicd_read_ctlr(base) & 71 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | 72 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { 73 ERROR("GICD_CTLR group interrupts are either enabled or have " 74 "pending writes. Cannot set RT owner.\n"); 75 panic(); 76 } 77 78 /* Poll till PUP is zero before initiating write */ 79 gicd_dchipr_wait_for_power_update_progress(base); 80 81 write_gicd_dchipr(base, read_gicd_dchipr(base) | 82 (rt_owner << GICD_DCHIPR_RT_OWNER_SHIFT)); 83 84 /* Poll till PUP is zero to ensure write is complete */ 85 gicd_dchipr_wait_for_power_update_progress(base); 86 } 87 88 /******************************************************************************* 89 * Configures the Chip Register to make connections to GICDs on 90 * a multichip platform. 91 ******************************************************************************/ 92 static void set_gicd_chipr_n(uintptr_t base, 93 unsigned int chip_id, 94 uint64_t chip_addr, 95 unsigned int spi_id_min, 96 unsigned int spi_id_max) 97 { 98 unsigned int spi_block_min, spi_blocks; 99 unsigned int gicd_iidr_val = gicd_read_iidr(base); 100 uint64_t chipr_n_val; 101 102 /* 103 * Ensure that group enables in GICD_CTLR are disabled and no pending 104 * register writes to GICD_CTLR. 105 */ 106 if ((gicd_read_ctlr(base) & 107 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | 108 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { 109 ERROR("GICD_CTLR group interrupts are either enabled or have " 110 "pending writes. Cannot set CHIPR register.\n"); 111 panic(); 112 } 113 114 /* 115 * spi_id_min and spi_id_max of value 0 is used to indicate that the 116 * chip doesn't own any SPI block. Re-assign min and max values as SPI 117 * id starts from 32. 118 */ 119 if (spi_id_min == 0U && spi_id_max == 0U) { 120 spi_id_min = GIC600_SPI_ID_MIN; 121 spi_id_max = GIC600_SPI_ID_MIN; 122 } else if (spi_id_min < GIC600_SPI_ID_MIN || spi_id_max < spi_id_min || 123 spi_id_max > GIC600_SPI_ID_MAX) { 124 ERROR("Invalid SPI ID range: min=%u max=%u\n", spi_id_min, spi_id_max); 125 panic(); 126 } 127 128 switch ((gicd_iidr_val & IIDR_MODEL_MASK)) { 129 case IIDR_MODEL_ARM_GIC_600: 130 spi_block_min = SPI_BLOCK_MIN_VALUE(spi_id_min); 131 spi_blocks = SPI_BLOCKS_VALUE(spi_id_min, spi_id_max); 132 133 chipr_n_val = GICD_CHIPR_VALUE_GIC_600(chip_addr, 134 spi_block_min, 135 spi_blocks); 136 break; 137 case IIDR_MODEL_ARM_GIC_700: 138 /* Calculate the SPI_ID_MIN value for ESPI */ 139 if (spi_id_min >= GIC700_ESPI_ID_MIN) { 140 spi_block_min = ESPI_BLOCK_MIN_VALUE(spi_id_min); 141 spi_block_min += SPI_BLOCKS_VALUE(GIC700_SPI_ID_MIN, 142 GIC700_SPI_ID_MAX); 143 } else { 144 spi_block_min = SPI_BLOCK_MIN_VALUE(spi_id_min); 145 } 146 147 /* Calculate the total number of blocks */ 148 spi_blocks = SPI_BLOCKS_VALUE(spi_id_min, spi_id_max); 149 150 chipr_n_val = GICD_CHIPR_VALUE_GIC_700(chip_addr, 151 spi_block_min, 152 spi_blocks); 153 break; 154 default: 155 ERROR("Unsupported GIC model 0x%x for multichip setup.\n", 156 gicd_iidr_val); 157 panic(); 158 break; 159 } 160 chipr_n_val |= GICD_CHIPRx_SOCKET_STATE; 161 162 /* 163 * Wait for DCHIPR.PUP to be zero before commencing writes to 164 * GICD_CHIPRx. 165 */ 166 gicd_dchipr_wait_for_power_update_progress(base); 167 168 /* 169 * Assign chip addr, spi min block, number of spi blocks and bring chip 170 * online by setting SocketState. 171 */ 172 write_gicd_chipr_n(base, chip_id, chipr_n_val); 173 174 /* 175 * Poll until DCHIP.PUP is zero to verify connection to rt_owner chip 176 * is complete. 177 */ 178 gicd_dchipr_wait_for_power_update_progress(base); 179 180 /* 181 * Ensure that write to GICD_CHIPRx is successful and the chip_n came 182 * online. 183 */ 184 if (read_gicd_chipr_n(base, chip_id) != chipr_n_val) { 185 ERROR("GICD_CHIPR%u write failed\n", chip_id); 186 panic(); 187 } 188 189 /* Ensure that chip is in consistent state */ 190 if (((read_gicd_chipsr(base) & GICD_CHIPSR_RTS_MASK) >> 191 GICD_CHIPSR_RTS_SHIFT) != 192 GICD_CHIPSR_RTS_STATE_CONSISTENT) { 193 ERROR("Chip %u routing table is not in consistent state\n", 194 chip_id); 195 panic(); 196 } 197 } 198 199 /******************************************************************************* 200 * Validates the GIC-600 Multichip data structure passed by the platform. 201 ******************************************************************************/ 202 static void gic600_multichip_validate_data( 203 struct gic600_multichip_data *multichip_data) 204 { 205 unsigned int i, spi_id_min, spi_id_max, blocks_of_32; 206 unsigned int multichip_spi_blocks = 0; 207 208 assert(multichip_data != NULL); 209 210 if (multichip_data->chip_count > GIC600_MAX_MULTICHIP) { 211 ERROR("GIC-600 Multichip count should not exceed %d\n", 212 GIC600_MAX_MULTICHIP); 213 panic(); 214 } 215 216 for (i = 0U; i < multichip_data->chip_count; i++) { 217 spi_id_min = multichip_data->spi_ids[i].spi_id_min; 218 spi_id_max = multichip_data->spi_ids[i].spi_id_max; 219 220 if ((spi_id_min != 0U) || (spi_id_max != 0U)) { 221 222 /* SPI IDs range check */ 223 if (!(spi_id_min >= GIC600_SPI_ID_MIN) || 224 !(spi_id_max <= GIC600_SPI_ID_MAX) || 225 !(spi_id_min <= spi_id_max) || 226 !((spi_id_max - spi_id_min + 1) % 32 == 0)) { 227 ERROR("Invalid SPI IDs {%u, %u} passed for " 228 "Chip %u\n", spi_id_min, 229 spi_id_max, i); 230 panic(); 231 } 232 233 /* SPI IDs overlap check */ 234 blocks_of_32 = BLOCKS_OF_32(spi_id_min, spi_id_max); 235 if ((multichip_spi_blocks & blocks_of_32) != 0) { 236 ERROR("SPI IDs of Chip %u overlapping\n", i); 237 panic(); 238 } 239 multichip_spi_blocks |= blocks_of_32; 240 } 241 } 242 } 243 244 /******************************************************************************* 245 * Validates the GIC-700 Multichip data structure passed by the platform. 246 ******************************************************************************/ 247 static void gic700_multichip_validate_data( 248 struct gic600_multichip_data *multichip_data) 249 { 250 unsigned int i, spi_id_min, spi_id_max, blocks_of_32; 251 unsigned int multichip_spi_blocks = 0U, multichip_espi_blocks = 0U; 252 253 assert(multichip_data != NULL); 254 255 if (multichip_data->chip_count > GIC600_MAX_MULTICHIP) { 256 ERROR("GIC-700 Multichip count (%u) should not exceed %u\n", 257 multichip_data->chip_count, GIC600_MAX_MULTICHIP); 258 panic(); 259 } 260 261 for (i = 0U; i < multichip_data->chip_count; i++) { 262 spi_id_min = multichip_data->spi_ids[i].spi_id_min; 263 spi_id_max = multichip_data->spi_ids[i].spi_id_max; 264 265 if ((spi_id_min == 0U) || (spi_id_max == 0U)) { 266 continue; 267 } 268 269 /* MIN SPI ID check */ 270 if ((spi_id_min < GIC700_SPI_ID_MIN) || 271 ((spi_id_min >= GIC700_SPI_ID_MAX) && 272 (spi_id_min < GIC700_ESPI_ID_MIN))) { 273 ERROR("Invalid MIN SPI ID {%u} passed for " 274 "Chip %u\n", spi_id_min, i); 275 panic(); 276 } 277 278 if ((spi_id_min > spi_id_max) || 279 ((spi_id_max - spi_id_min + 1) % 32 != 0)) { 280 ERROR("Unaligned SPI IDs {%u, %u} passed for " 281 "Chip %u\n", spi_id_min, 282 spi_id_max, i); 283 panic(); 284 } 285 286 /* ESPI IDs range check */ 287 if ((spi_id_min >= GIC700_ESPI_ID_MIN) && 288 (spi_id_max > GIC700_ESPI_ID_MAX)) { 289 ERROR("Invalid ESPI IDs {%u, %u} passed for " 290 "Chip %u\n", spi_id_min, 291 spi_id_max, i); 292 panic(); 293 294 } 295 296 /* SPI IDs range check */ 297 if (((spi_id_min < GIC700_SPI_ID_MAX) && 298 (spi_id_max > GIC700_SPI_ID_MAX))) { 299 ERROR("Invalid SPI IDs {%u, %u} passed for " 300 "Chip %u\n", spi_id_min, 301 spi_id_max, i); 302 panic(); 303 } 304 305 /* SPI IDs overlap check */ 306 if (spi_id_max < GIC700_SPI_ID_MAX) { 307 blocks_of_32 = BLOCKS_OF_32(spi_id_min, spi_id_max); 308 if ((multichip_spi_blocks & blocks_of_32) != 0) { 309 ERROR("SPI IDs of Chip %u overlapping\n", i); 310 panic(); 311 } 312 multichip_spi_blocks |= blocks_of_32; 313 } 314 315 /* ESPI IDs overlap check */ 316 if (spi_id_max > GIC700_ESPI_ID_MIN) { 317 blocks_of_32 = BLOCKS_OF_32(spi_id_min - GIC700_ESPI_ID_MIN, 318 spi_id_max - GIC700_ESPI_ID_MIN); 319 if ((multichip_espi_blocks & blocks_of_32) != 0) { 320 ERROR("SPI IDs of Chip %u overlapping\n", i); 321 panic(); 322 } 323 multichip_espi_blocks |= blocks_of_32; 324 } 325 } 326 } 327 328 /******************************************************************************* 329 * Initialize GIC-600 and GIC-700 Multichip operation in LCA mode by setting up 330 * the routing table first. 331 ******************************************************************************/ 332 static void gic600_multichip_lca_init( 333 struct gic600_multichip_data *multichip_data) 334 { 335 unsigned int i, j; 336 unsigned int rt_owner = multichip_data->rt_owner; 337 338 for (i = 0; i < multichip_data->chip_count; i++) { 339 for (j = 0; j < multichip_data->chip_count; j++) { 340 INFO("RT(LCA): CHIP%u -> CHIP%u 0x%lx\n", i, j, 341 multichip_data->chip_addrs[i][j]); 342 set_gicd_chipr_n(multichip_data->base_addrs[i], j, 343 multichip_data->chip_addrs[i][j], 344 multichip_data->spi_ids[j].spi_id_min, 345 multichip_data->spi_ids[j].spi_id_max); 346 } 347 } 348 349 /* Initialize the GICD which is marked as routing table owner last */ 350 set_gicd_dchipr_rt_owner(multichip_data->base_addrs[rt_owner], 351 rt_owner); 352 } 353 354 /******************************************************************************* 355 * Initialize GIC-600 and GIC-700 Multichip operation. 356 ******************************************************************************/ 357 void gic600_multichip_init(struct gic600_multichip_data *multichip_data) 358 { 359 unsigned int i; 360 unsigned int rt_owner = multichip_data->rt_owner; 361 uint32_t gicd_iidr_val = 362 gicd_read_iidr(multichip_data->base_addrs[rt_owner]); 363 364 if ((gicd_iidr_val & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) { 365 gic600_multichip_validate_data(multichip_data); 366 } 367 368 if ((gicd_iidr_val & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_700) { 369 gic700_multichip_validate_data(multichip_data); 370 } 371 372 /* 373 * Ensure that G0/G1S/G1NS interrupts are disabled. This also ensures 374 * that GIC-600 Multichip configuration is done first. 375 */ 376 if ((gicd_read_ctlr(multichip_data->base_addrs[rt_owner]) & 377 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | 378 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { 379 ERROR("GICD_CTLR group interrupts are either enabled or have " 380 "pending writes.\n"); 381 panic(); 382 } 383 384 /* Ensure that the routing table owner is in disconnected state */ 385 if (((read_gicd_chipsr(multichip_data->base_addrs[rt_owner]) & 386 GICD_CHIPSR_RTS_MASK) >> GICD_CHIPSR_RTS_SHIFT) != 387 GICD_CHIPSR_RTS_STATE_DISCONNECTED) { 388 ERROR("GIC-600 routing table owner is not in disconnected " 389 "state to begin multichip configuration\n"); 390 panic(); 391 } 392 393 /* If LCA is not enabled */ 394 if ((read_gicd_cfgid(multichip_data->base_addrs[rt_owner]) & 395 GICD_CFGID_LCA_BIT) == 0) { 396 /* 397 * Initialize the GICD which is marked as routing table 398 * owner first. 399 */ 400 set_gicd_dchipr_rt_owner(multichip_data->base_addrs[rt_owner], 401 rt_owner); 402 403 set_gicd_chipr_n(multichip_data->base_addrs[rt_owner], rt_owner, 404 multichip_data->chip_addrs[rt_owner][rt_owner], 405 multichip_data->spi_ids[rt_owner].spi_id_min, 406 multichip_data->spi_ids[rt_owner].spi_id_max); 407 408 for (i = 0; i < multichip_data->chip_count; i++) { 409 if (i == rt_owner) 410 continue; 411 set_gicd_chipr_n( 412 multichip_data->base_addrs[rt_owner], i, 413 multichip_data->chip_addrs[rt_owner][i], 414 multichip_data->spi_ids[i].spi_id_min, 415 multichip_data->spi_ids[i].spi_id_max); 416 } 417 } else { 418 /* If LCA is enabled */ 419 INFO("GIC Local chip addressing is enabled\n"); 420 gic600_multichip_lca_init(multichip_data); 421 } 422 423 plat_gic_multichip_data = multichip_data; 424 } 425 426 /******************************************************************************* 427 * Allow a way to query the status of the GIC600 multichip driver 428 ******************************************************************************/ 429 bool gic600_multichip_is_initialized(void) 430 { 431 return (plat_gic_multichip_data != NULL); 432 } 433