1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV2_PRIVATE_H__ 8 #define __GICV2_PRIVATE_H__ 9 10 #include <gicv2.h> 11 #include <mmio.h> 12 #include <stdint.h> 13 14 /******************************************************************************* 15 * Private function prototypes 16 ******************************************************************************/ 17 void gicv2_spis_configure_defaults(uintptr_t gicd_base); 18 #if !ERROR_DEPRECATED 19 void gicv2_secure_spis_configure(uintptr_t gicd_base, 20 unsigned int num_ints, 21 const unsigned int *sec_intr_list); 22 void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, 23 unsigned int num_ints, 24 const unsigned int *sec_intr_list); 25 #endif 26 void gicv2_secure_spis_configure_props(uintptr_t gicd_base, 27 const interrupt_prop_t *interrupt_props, 28 unsigned int interrupt_props_num); 29 void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base, 30 const interrupt_prop_t *interrupt_props, 31 unsigned int interrupt_props_num); 32 unsigned int gicv2_get_cpuif_id(uintptr_t base); 33 34 /******************************************************************************* 35 * GIC Distributor interface accessors for reading entire registers 36 ******************************************************************************/ 37 static inline unsigned int gicd_read_pidr2(uintptr_t base) 38 { 39 return mmio_read_32(base + GICD_PIDR2_GICV2); 40 } 41 42 /******************************************************************************* 43 * GIC Distributor interface accessors for writing entire registers 44 ******************************************************************************/ 45 static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id) 46 { 47 return mmio_read_8(base + GICD_ITARGETSR + id); 48 } 49 50 static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id, 51 unsigned int target) 52 { 53 uint8_t val = target & GIC_TARGET_CPU_MASK; 54 55 mmio_write_8(base + GICD_ITARGETSR + id, val); 56 } 57 58 static inline void gicd_write_sgir(uintptr_t base, unsigned int val) 59 { 60 mmio_write_32(base + GICD_SGIR, val); 61 } 62 63 /******************************************************************************* 64 * GIC CPU interface accessors for reading entire registers 65 ******************************************************************************/ 66 67 static inline unsigned int gicc_read_ctlr(uintptr_t base) 68 { 69 return mmio_read_32(base + GICC_CTLR); 70 } 71 72 static inline unsigned int gicc_read_pmr(uintptr_t base) 73 { 74 return mmio_read_32(base + GICC_PMR); 75 } 76 77 static inline unsigned int gicc_read_BPR(uintptr_t base) 78 { 79 return mmio_read_32(base + GICC_BPR); 80 } 81 82 static inline unsigned int gicc_read_IAR(uintptr_t base) 83 { 84 return mmio_read_32(base + GICC_IAR); 85 } 86 87 static inline unsigned int gicc_read_EOIR(uintptr_t base) 88 { 89 return mmio_read_32(base + GICC_EOIR); 90 } 91 92 static inline unsigned int gicc_read_hppir(uintptr_t base) 93 { 94 return mmio_read_32(base + GICC_HPPIR); 95 } 96 97 static inline unsigned int gicc_read_ahppir(uintptr_t base) 98 { 99 return mmio_read_32(base + GICC_AHPPIR); 100 } 101 102 static inline unsigned int gicc_read_dir(uintptr_t base) 103 { 104 return mmio_read_32(base + GICC_DIR); 105 } 106 107 static inline unsigned int gicc_read_iidr(uintptr_t base) 108 { 109 return mmio_read_32(base + GICC_IIDR); 110 } 111 112 static inline unsigned int gicc_read_rpr(uintptr_t base) 113 { 114 return mmio_read_32(base + GICC_RPR); 115 } 116 117 /******************************************************************************* 118 * GIC CPU interface accessors for writing entire registers 119 ******************************************************************************/ 120 121 static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) 122 { 123 mmio_write_32(base + GICC_CTLR, val); 124 } 125 126 static inline void gicc_write_pmr(uintptr_t base, unsigned int val) 127 { 128 mmio_write_32(base + GICC_PMR, val); 129 } 130 131 static inline void gicc_write_BPR(uintptr_t base, unsigned int val) 132 { 133 mmio_write_32(base + GICC_BPR, val); 134 } 135 136 137 static inline void gicc_write_IAR(uintptr_t base, unsigned int val) 138 { 139 mmio_write_32(base + GICC_IAR, val); 140 } 141 142 static inline void gicc_write_EOIR(uintptr_t base, unsigned int val) 143 { 144 mmio_write_32(base + GICC_EOIR, val); 145 } 146 147 static inline void gicc_write_hppir(uintptr_t base, unsigned int val) 148 { 149 mmio_write_32(base + GICC_HPPIR, val); 150 } 151 152 static inline void gicc_write_dir(uintptr_t base, unsigned int val) 153 { 154 mmio_write_32(base + GICC_DIR, val); 155 } 156 157 #endif /* __GICV2_PRIVATE_H__ */ 158