1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __GICV2_PRIVATE_H__ 32 #define __GICV2_PRIVATE_H__ 33 34 #include <gicv2.h> 35 #include <mmio.h> 36 #include <stdint.h> 37 38 /******************************************************************************* 39 * Private function prototypes 40 ******************************************************************************/ 41 void gicv2_spis_configure_defaults(uintptr_t gicd_base); 42 void gicv2_secure_spis_configure(uintptr_t gicd_base, 43 unsigned int num_ints, 44 const unsigned int *sec_intr_list); 45 void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, 46 unsigned int num_ints, 47 const unsigned int *sec_intr_list); 48 unsigned int gicv2_get_cpuif_id(uintptr_t base); 49 50 /******************************************************************************* 51 * GIC Distributor interface accessors for reading entire registers 52 ******************************************************************************/ 53 static inline unsigned int gicd_read_pidr2(uintptr_t base) 54 { 55 return mmio_read_32(base + GICD_PIDR2_GICV2); 56 } 57 58 /******************************************************************************* 59 * GIC CPU interface accessors for reading entire registers 60 ******************************************************************************/ 61 62 static inline unsigned int gicc_read_ctlr(uintptr_t base) 63 { 64 return mmio_read_32(base + GICC_CTLR); 65 } 66 67 static inline unsigned int gicc_read_pmr(uintptr_t base) 68 { 69 return mmio_read_32(base + GICC_PMR); 70 } 71 72 static inline unsigned int gicc_read_BPR(uintptr_t base) 73 { 74 return mmio_read_32(base + GICC_BPR); 75 } 76 77 static inline unsigned int gicc_read_IAR(uintptr_t base) 78 { 79 return mmio_read_32(base + GICC_IAR); 80 } 81 82 static inline unsigned int gicc_read_EOIR(uintptr_t base) 83 { 84 return mmio_read_32(base + GICC_EOIR); 85 } 86 87 static inline unsigned int gicc_read_hppir(uintptr_t base) 88 { 89 return mmio_read_32(base + GICC_HPPIR); 90 } 91 92 static inline unsigned int gicc_read_ahppir(uintptr_t base) 93 { 94 return mmio_read_32(base + GICC_AHPPIR); 95 } 96 97 static inline unsigned int gicc_read_dir(uintptr_t base) 98 { 99 return mmio_read_32(base + GICC_DIR); 100 } 101 102 static inline unsigned int gicc_read_iidr(uintptr_t base) 103 { 104 return mmio_read_32(base + GICC_IIDR); 105 } 106 107 /******************************************************************************* 108 * GIC CPU interface accessors for writing entire registers 109 ******************************************************************************/ 110 111 static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) 112 { 113 mmio_write_32(base + GICC_CTLR, val); 114 } 115 116 static inline void gicc_write_pmr(uintptr_t base, unsigned int val) 117 { 118 mmio_write_32(base + GICC_PMR, val); 119 } 120 121 static inline void gicc_write_BPR(uintptr_t base, unsigned int val) 122 { 123 mmio_write_32(base + GICC_BPR, val); 124 } 125 126 127 static inline void gicc_write_IAR(uintptr_t base, unsigned int val) 128 { 129 mmio_write_32(base + GICC_IAR, val); 130 } 131 132 static inline void gicc_write_EOIR(uintptr_t base, unsigned int val) 133 { 134 mmio_write_32(base + GICC_EOIR, val); 135 } 136 137 static inline void gicc_write_hppir(uintptr_t base, unsigned int val) 138 { 139 mmio_write_32(base + GICC_HPPIR, val); 140 } 141 142 static inline void gicc_write_dir(uintptr_t base, unsigned int val) 143 { 144 mmio_write_32(base + GICC_DIR, val); 145 } 146 147 #endif /* __GICV2_PRIVATE_H__ */ 148