1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV2_PRIVATE_H 8 #define GICV2_PRIVATE_H 9 10 #include <stdint.h> 11 12 #include <drivers/arm/gicv2.h> 13 #include <lib/mmio.h> 14 15 /******************************************************************************* 16 * Private function prototypes 17 ******************************************************************************/ 18 void gicv2_spis_configure_defaults(uintptr_t gicd_base); 19 void gicv2_secure_spis_configure_props(uintptr_t gicd_base, 20 const interrupt_prop_t *interrupt_props, 21 unsigned int interrupt_props_num); 22 void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base, 23 const interrupt_prop_t *interrupt_props, 24 unsigned int interrupt_props_num); 25 unsigned int gicv2_get_cpuif_id(uintptr_t base); 26 27 /******************************************************************************* 28 * GIC Distributor interface accessors for reading entire registers 29 ******************************************************************************/ 30 static inline unsigned int gicd_read_pidr2(uintptr_t base) 31 { 32 return mmio_read_32(base + GICD_PIDR2_GICV2); 33 } 34 35 /******************************************************************************* 36 * GIC Distributor interface accessors for writing entire registers 37 ******************************************************************************/ 38 static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id) 39 { 40 return mmio_read_8(base + GICD_ITARGETSR + id); 41 } 42 43 static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id, 44 unsigned int target) 45 { 46 uint8_t val = target & GIC_TARGET_CPU_MASK; 47 48 mmio_write_8(base + GICD_ITARGETSR + id, val); 49 } 50 51 static inline void gicd_write_sgir(uintptr_t base, unsigned int val) 52 { 53 mmio_write_32(base + GICD_SGIR, val); 54 } 55 56 /******************************************************************************* 57 * GIC CPU interface accessors for reading entire registers 58 ******************************************************************************/ 59 60 static inline unsigned int gicc_read_ctlr(uintptr_t base) 61 { 62 return mmio_read_32(base + GICC_CTLR); 63 } 64 65 static inline unsigned int gicc_read_pmr(uintptr_t base) 66 { 67 return mmio_read_32(base + GICC_PMR); 68 } 69 70 static inline unsigned int gicc_read_BPR(uintptr_t base) 71 { 72 return mmio_read_32(base + GICC_BPR); 73 } 74 75 static inline unsigned int gicc_read_IAR(uintptr_t base) 76 { 77 return mmio_read_32(base + GICC_IAR); 78 } 79 80 static inline unsigned int gicc_read_EOIR(uintptr_t base) 81 { 82 return mmio_read_32(base + GICC_EOIR); 83 } 84 85 static inline unsigned int gicc_read_hppir(uintptr_t base) 86 { 87 return mmio_read_32(base + GICC_HPPIR); 88 } 89 90 static inline unsigned int gicc_read_ahppir(uintptr_t base) 91 { 92 return mmio_read_32(base + GICC_AHPPIR); 93 } 94 95 static inline unsigned int gicc_read_dir(uintptr_t base) 96 { 97 return mmio_read_32(base + GICC_DIR); 98 } 99 100 static inline unsigned int gicc_read_iidr(uintptr_t base) 101 { 102 return mmio_read_32(base + GICC_IIDR); 103 } 104 105 static inline unsigned int gicc_read_rpr(uintptr_t base) 106 { 107 return mmio_read_32(base + GICC_RPR); 108 } 109 110 /******************************************************************************* 111 * GIC CPU interface accessors for writing entire registers 112 ******************************************************************************/ 113 114 static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) 115 { 116 mmio_write_32(base + GICC_CTLR, val); 117 } 118 119 static inline void gicc_write_pmr(uintptr_t base, unsigned int val) 120 { 121 mmio_write_32(base + GICC_PMR, val); 122 } 123 124 static inline void gicc_write_BPR(uintptr_t base, unsigned int val) 125 { 126 mmio_write_32(base + GICC_BPR, val); 127 } 128 129 130 static inline void gicc_write_IAR(uintptr_t base, unsigned int val) 131 { 132 mmio_write_32(base + GICC_IAR, val); 133 } 134 135 static inline void gicc_write_EOIR(uintptr_t base, unsigned int val) 136 { 137 mmio_write_32(base + GICC_EOIR, val); 138 } 139 140 static inline void gicc_write_hppir(uintptr_t base, unsigned int val) 141 { 142 mmio_write_32(base + GICC_HPPIR, val); 143 } 144 145 static inline void gicc_write_dir(uintptr_t base, unsigned int val) 146 { 147 mmio_write_32(base + GICC_DIR, val); 148 } 149 150 #endif /* GICV2_PRIVATE_H */ 151