1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic_common.h> 15 #include <drivers/arm/gicv2.h> 16 #include <lib/spinlock.h> 17 18 #include "../common/gic_common_private.h" 19 #include "gicv2_private.h" 20 21 static const gicv2_driver_data_t *driver_data; 22 23 /* 24 * Spinlock to guard registers needing read-modify-write. APIs protected by this 25 * spinlock are used either at boot time (when only a single CPU is active), or 26 * when the system is fully coherent. 27 */ 28 static spinlock_t gic_lock; 29 30 /******************************************************************************* 31 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass 32 * and set the priority mask register to allow all interrupts to trickle in. 33 ******************************************************************************/ 34 void gicv2_cpuif_enable(void) 35 { 36 unsigned int val; 37 38 assert(driver_data != NULL); 39 assert(driver_data->gicc_base != 0U); 40 41 /* 42 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 43 * bypass. 44 */ 45 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; 46 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; 47 48 /* Program the idle priority in the PMR */ 49 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); 50 gicc_write_ctlr(driver_data->gicc_base, val); 51 } 52 53 /******************************************************************************* 54 * Place the cpu interface in a state where it can never make a cpu exit wfi as 55 * as result of an asserted interrupt. This is critical for powering down a cpu 56 ******************************************************************************/ 57 void gicv2_cpuif_disable(void) 58 { 59 unsigned int val; 60 61 assert(driver_data != NULL); 62 assert(driver_data->gicc_base != 0U); 63 64 /* Disable secure, non-secure interrupts and disable their bypass */ 65 val = gicc_read_ctlr(driver_data->gicc_base); 66 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); 67 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; 68 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; 69 gicc_write_ctlr(driver_data->gicc_base, val); 70 } 71 72 /******************************************************************************* 73 * Per cpu gic distributor setup which will be done by all cpus after a cold 74 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. 75 ******************************************************************************/ 76 void gicv2_pcpu_distif_init(void) 77 { 78 unsigned int ctlr; 79 80 assert(driver_data != NULL); 81 assert(driver_data->gicd_base != 0U); 82 83 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, 84 driver_data->interrupt_props, 85 driver_data->interrupt_props_num); 86 87 /* Enable G0 interrupts if not already */ 88 ctlr = gicd_read_ctlr(driver_data->gicd_base); 89 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) { 90 gicd_write_ctlr(driver_data->gicd_base, 91 ctlr | CTLR_ENABLE_G0_BIT); 92 } 93 } 94 95 /******************************************************************************* 96 * Global gic distributor init which will be done by the primary cpu after a 97 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It 98 * then enables the secure GIC distributor interface. 99 ******************************************************************************/ 100 void gicv2_distif_init(void) 101 { 102 unsigned int ctlr; 103 104 assert(driver_data != NULL); 105 assert(driver_data->gicd_base != 0U); 106 107 /* Disable the distributor before going further */ 108 ctlr = gicd_read_ctlr(driver_data->gicd_base); 109 gicd_write_ctlr(driver_data->gicd_base, 110 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); 111 112 /* Set the default attribute of all SPIs */ 113 gicv2_spis_configure_defaults(driver_data->gicd_base); 114 115 gicv2_secure_spis_configure_props(driver_data->gicd_base, 116 driver_data->interrupt_props, 117 driver_data->interrupt_props_num); 118 119 120 /* Re-enable the secure SPIs now that they have been configured */ 121 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); 122 } 123 124 /******************************************************************************* 125 * Initialize the ARM GICv2 driver with the provided platform inputs 126 ******************************************************************************/ 127 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) 128 { 129 unsigned int gic_version; 130 131 assert(plat_driver_data != NULL); 132 assert(plat_driver_data->gicd_base != 0U); 133 assert(plat_driver_data->gicc_base != 0U); 134 135 assert(plat_driver_data->interrupt_props_num > 0 ? 136 plat_driver_data->interrupt_props != NULL : 1); 137 138 /* Ensure that this is a GICv2 system */ 139 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 140 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) 141 & PIDR2_ARCH_REV_MASK; 142 143 /* 144 * GICv1 with security extension complies with trusted firmware 145 * GICv2 driver as far as virtualization and few tricky power 146 * features are not used. GICv2 features that are not supported 147 * by GICv1 with Security Extensions are: 148 * - virtual interrupt support. 149 * - wake up events. 150 * - writeable GIC state register (for power sequences) 151 * - interrupt priority drop. 152 * - interrupt signal bypass. 153 */ 154 assert((gic_version == ARCH_REV_GICV2) || 155 (gic_version == ARCH_REV_GICV1)); 156 157 driver_data = plat_driver_data; 158 159 /* 160 * The GIC driver data is initialized by the primary CPU with caches 161 * enabled. When the secondary CPU boots up, it initializes the 162 * GICC/GICR interface with the caches disabled. Hence flush the 163 * driver_data to ensure coherency. This is not required if the 164 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY 165 * enabled. 166 */ 167 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 168 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 169 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 170 #endif 171 INFO("ARM GICv2 driver initialized\n"); 172 } 173 174 /****************************************************************************** 175 * This function returns whether FIQ is enabled in the GIC CPU interface. 176 *****************************************************************************/ 177 unsigned int gicv2_is_fiq_enabled(void) 178 { 179 unsigned int gicc_ctlr; 180 181 assert(driver_data != NULL); 182 assert(driver_data->gicc_base != 0U); 183 184 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); 185 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1U; 186 } 187 188 /******************************************************************************* 189 * This function returns the type of the highest priority pending interrupt at 190 * the GIC cpu interface. The return values can be one of the following : 191 * PENDING_G1_INTID : The interrupt type is non secure Group 1. 192 * 0 - 1019 : The interrupt type is secure Group 0. 193 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 194 * sufficient priority to be signaled 195 ******************************************************************************/ 196 unsigned int gicv2_get_pending_interrupt_type(void) 197 { 198 assert(driver_data != NULL); 199 assert(driver_data->gicc_base != 0U); 200 201 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 202 } 203 204 /******************************************************************************* 205 * This function returns the id of the highest priority pending interrupt at 206 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no 207 * interrupt pending. 208 ******************************************************************************/ 209 unsigned int gicv2_get_pending_interrupt_id(void) 210 { 211 unsigned int id; 212 213 assert(driver_data != NULL); 214 assert(driver_data->gicc_base != 0U); 215 216 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 217 218 /* 219 * Find out which non-secure interrupt it is under the assumption that 220 * the GICC_CTLR.AckCtl bit is 0. 221 */ 222 if (id == PENDING_G1_INTID) 223 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; 224 225 return id; 226 } 227 228 /******************************************************************************* 229 * This functions reads the GIC cpu interface Interrupt Acknowledge register 230 * to start handling the pending secure 0 interrupt. It returns the 231 * contents of the IAR. 232 ******************************************************************************/ 233 unsigned int gicv2_acknowledge_interrupt(void) 234 { 235 assert(driver_data != NULL); 236 assert(driver_data->gicc_base != 0U); 237 238 return gicc_read_IAR(driver_data->gicc_base); 239 } 240 241 /******************************************************************************* 242 * This functions writes the GIC cpu interface End Of Interrupt register with 243 * the passed value to finish handling the active secure group 0 interrupt. 244 ******************************************************************************/ 245 void gicv2_end_of_interrupt(unsigned int id) 246 { 247 assert(driver_data != NULL); 248 assert(driver_data->gicc_base != 0U); 249 250 /* 251 * Ensure the write to peripheral registers are *complete* before the write 252 * to GIC_EOIR. 253 * 254 * Note: The completion gurantee depends on various factors of system design 255 * and the barrier is the best core can do by which execution of further 256 * instructions waits till the barrier is alive. 257 */ 258 dsbishst(); 259 gicc_write_EOIR(driver_data->gicc_base, id); 260 } 261 262 /******************************************************************************* 263 * This function returns the type of the interrupt id depending upon the group 264 * this interrupt has been configured under by the interrupt controller i.e. 265 * group0 secure or group1 non secure. It returns zero for Group 0 secure and 266 * one for Group 1 non secure interrupt. 267 ******************************************************************************/ 268 unsigned int gicv2_get_interrupt_group(unsigned int id) 269 { 270 assert(driver_data != NULL); 271 assert(driver_data->gicd_base != 0U); 272 273 return gicd_get_igroupr(driver_data->gicd_base, id); 274 } 275 276 /******************************************************************************* 277 * This function returns the priority of the interrupt the processor is 278 * currently servicing. 279 ******************************************************************************/ 280 unsigned int gicv2_get_running_priority(void) 281 { 282 assert(driver_data != NULL); 283 assert(driver_data->gicc_base != 0U); 284 285 return gicc_read_rpr(driver_data->gicc_base); 286 } 287 288 /******************************************************************************* 289 * This function sets the GICv2 target mask pattern for the current PE. The PE 290 * target mask is used to translate linear PE index (returned by platform core 291 * position) to a bit mask used when targeting interrupts to a PE (for example 292 * when raising SGIs and routing SPIs). 293 ******************************************************************************/ 294 void gicv2_set_pe_target_mask(unsigned int proc_num) 295 { 296 assert(driver_data != NULL); 297 assert(driver_data->gicd_base != 0U); 298 assert(driver_data->target_masks != NULL); 299 assert(proc_num < GICV2_MAX_TARGET_PE); 300 assert(proc_num < driver_data->target_masks_num); 301 302 /* Return if the target mask is already populated */ 303 if (driver_data->target_masks[proc_num] != 0U) 304 return; 305 306 /* 307 * Update target register corresponding to this CPU and flush for it to 308 * be visible to other CPUs. 309 */ 310 if (driver_data->target_masks[proc_num] == 0U) { 311 driver_data->target_masks[proc_num] = 312 gicv2_get_cpuif_id(driver_data->gicd_base); 313 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 314 /* 315 * PEs only update their own masks. Primary updates it with 316 * caches on. But because secondaries does it with caches off, 317 * all updates go to memory directly, and there's no danger of 318 * secondaries overwriting each others' mask, despite 319 * target_masks[] not being cache line aligned. 320 */ 321 flush_dcache_range((uintptr_t) 322 &driver_data->target_masks[proc_num], 323 sizeof(driver_data->target_masks[proc_num])); 324 #endif 325 } 326 } 327 328 /******************************************************************************* 329 * This function returns the active status of the interrupt (either because the 330 * state is active, or active and pending). 331 ******************************************************************************/ 332 unsigned int gicv2_get_interrupt_active(unsigned int id) 333 { 334 assert(driver_data != NULL); 335 assert(driver_data->gicd_base != 0U); 336 assert(id <= MAX_SPI_ID); 337 338 return gicd_get_isactiver(driver_data->gicd_base, id); 339 } 340 341 /******************************************************************************* 342 * This function enables the interrupt identified by id. 343 ******************************************************************************/ 344 void gicv2_enable_interrupt(unsigned int id) 345 { 346 assert(driver_data != NULL); 347 assert(driver_data->gicd_base != 0U); 348 assert(id <= MAX_SPI_ID); 349 350 /* 351 * Ensure that any shared variable updates depending on out of band 352 * interrupt trigger are observed before enabling interrupt. 353 */ 354 dsbishst(); 355 gicd_set_isenabler(driver_data->gicd_base, id); 356 } 357 358 /******************************************************************************* 359 * This function disables the interrupt identified by id. 360 ******************************************************************************/ 361 void gicv2_disable_interrupt(unsigned int id) 362 { 363 assert(driver_data != NULL); 364 assert(driver_data->gicd_base != 0U); 365 assert(id <= MAX_SPI_ID); 366 367 /* 368 * Disable interrupt, and ensure that any shared variable updates 369 * depending on out of band interrupt trigger are observed afterwards. 370 */ 371 gicd_set_icenabler(driver_data->gicd_base, id); 372 dsbishst(); 373 } 374 375 /******************************************************************************* 376 * This function sets the interrupt priority as supplied for the given interrupt 377 * id. 378 ******************************************************************************/ 379 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) 380 { 381 assert(driver_data != NULL); 382 assert(driver_data->gicd_base != 0U); 383 assert(id <= MAX_SPI_ID); 384 385 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); 386 } 387 388 /******************************************************************************* 389 * This function assigns group for the interrupt identified by id. The group can 390 * be any of GICV2_INTR_GROUP* 391 ******************************************************************************/ 392 void gicv2_set_interrupt_type(unsigned int id, unsigned int type) 393 { 394 assert(driver_data != NULL); 395 assert(driver_data->gicd_base != 0U); 396 assert(id <= MAX_SPI_ID); 397 398 /* Serialize read-modify-write to Distributor registers */ 399 spin_lock(&gic_lock); 400 switch (type) { 401 case GICV2_INTR_GROUP1: 402 gicd_set_igroupr(driver_data->gicd_base, id); 403 break; 404 case GICV2_INTR_GROUP0: 405 gicd_clr_igroupr(driver_data->gicd_base, id); 406 break; 407 default: 408 assert(false); 409 break; 410 } 411 spin_unlock(&gic_lock); 412 } 413 414 /******************************************************************************* 415 * This function raises the specified SGI to requested targets. 416 * 417 * The proc_num parameter must be the linear index of the target PE in the 418 * system. 419 ******************************************************************************/ 420 void gicv2_raise_sgi(int sgi_num, int proc_num) 421 { 422 unsigned int sgir_val, target; 423 424 assert(driver_data != NULL); 425 assert(proc_num >= 0); 426 assert(proc_num < (int)GICV2_MAX_TARGET_PE); 427 assert(driver_data->gicd_base != 0U); 428 429 /* 430 * Target masks array must have been supplied, and the core position 431 * should be valid. 432 */ 433 assert(driver_data->target_masks != NULL); 434 assert(proc_num < (int)driver_data->target_masks_num); 435 436 /* Don't raise SGI if the mask hasn't been populated */ 437 target = driver_data->target_masks[proc_num]; 438 assert(target != 0U); 439 440 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num); 441 442 /* 443 * Ensure that any shared variable updates depending on out of band 444 * interrupt trigger are observed before raising SGI. 445 */ 446 dsbishst(); 447 gicd_write_sgir(driver_data->gicd_base, sgir_val); 448 } 449 450 /******************************************************************************* 451 * This function sets the interrupt routing for the given SPI interrupt id. 452 * The interrupt routing is specified in routing mode. The proc_num parameter is 453 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target 454 * all PEs. 455 ******************************************************************************/ 456 void gicv2_set_spi_routing(unsigned int id, int proc_num) 457 { 458 unsigned int target; 459 460 assert(driver_data != NULL); 461 assert(driver_data->gicd_base != 0U); 462 463 assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID)); 464 465 /* 466 * Target masks array must have been supplied, and the core position 467 * should be valid. 468 */ 469 assert(driver_data->target_masks != NULL); 470 assert(proc_num < (int)GICV2_MAX_TARGET_PE); 471 assert(driver_data->target_masks_num < INT_MAX); 472 assert(proc_num < (int)driver_data->target_masks_num); 473 474 if (proc_num < 0) { 475 /* Target all PEs */ 476 target = GIC_TARGET_CPU_MASK; 477 } else { 478 /* Don't route interrupt if the mask hasn't been populated */ 479 target = driver_data->target_masks[proc_num]; 480 assert(target != 0U); 481 } 482 483 gicd_set_itargetsr(driver_data->gicd_base, id, target); 484 } 485 486 /******************************************************************************* 487 * This function clears the pending status of an interrupt identified by id. 488 ******************************************************************************/ 489 void gicv2_clear_interrupt_pending(unsigned int id) 490 { 491 assert(driver_data != NULL); 492 assert(driver_data->gicd_base != 0U); 493 494 /* SGIs can't be cleared pending */ 495 assert(id >= MIN_PPI_ID); 496 497 /* 498 * Clear pending interrupt, and ensure that any shared variable updates 499 * depending on out of band interrupt trigger are observed afterwards. 500 */ 501 gicd_set_icpendr(driver_data->gicd_base, id); 502 dsbishst(); 503 } 504 505 /******************************************************************************* 506 * This function sets the pending status of an interrupt identified by id. 507 ******************************************************************************/ 508 void gicv2_set_interrupt_pending(unsigned int id) 509 { 510 assert(driver_data != NULL); 511 assert(driver_data->gicd_base != 0U); 512 513 /* SGIs can't be cleared pending */ 514 assert(id >= MIN_PPI_ID); 515 516 /* 517 * Ensure that any shared variable updates depending on out of band 518 * interrupt trigger are observed before setting interrupt pending. 519 */ 520 dsbishst(); 521 gicd_set_ispendr(driver_data->gicd_base, id); 522 } 523 524 /******************************************************************************* 525 * This function sets the PMR register with the supplied value. Returns the 526 * original PMR. 527 ******************************************************************************/ 528 unsigned int gicv2_set_pmr(unsigned int mask) 529 { 530 unsigned int old_mask; 531 532 assert(driver_data != NULL); 533 assert(driver_data->gicc_base != 0U); 534 535 old_mask = gicc_read_pmr(driver_data->gicc_base); 536 537 /* 538 * Order memory updates w.r.t. PMR write, and ensure they're visible 539 * before potential out of band interrupt trigger because of PMR update. 540 */ 541 dmbishst(); 542 gicc_write_pmr(driver_data->gicc_base, mask); 543 dsbishst(); 544 545 return old_mask; 546 } 547 548 /******************************************************************************* 549 * This function updates single interrupt configuration to be level/edge 550 * triggered 551 ******************************************************************************/ 552 void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg) 553 { 554 gicd_set_icfgr(driver_data->gicd_base, id, cfg); 555 } 556