1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic_common.h> 15 #include <drivers/arm/gicv2.h> 16 #include <lib/spinlock.h> 17 18 #include "../common/gic_common_private.h" 19 #include "gicv2_private.h" 20 21 static const gicv2_driver_data_t *driver_data; 22 23 /* 24 * Spinlock to guard registers needing read-modify-write. APIs protected by this 25 * spinlock are used either at boot time (when only a single CPU is active), or 26 * when the system is fully coherent. 27 */ 28 static spinlock_t gic_lock; 29 30 /******************************************************************************* 31 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass 32 * and set the priority mask register to allow all interrupts to trickle in. 33 ******************************************************************************/ 34 void gicv2_cpuif_enable(void) 35 { 36 unsigned int val; 37 38 assert(driver_data != NULL); 39 assert(driver_data->gicc_base != 0U); 40 41 /* 42 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 43 * bypass. 44 */ 45 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; 46 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; 47 48 /* Program the idle priority in the PMR */ 49 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); 50 gicc_write_ctlr(driver_data->gicc_base, val); 51 } 52 53 /******************************************************************************* 54 * Place the cpu interface in a state where it can never make a cpu exit wfi as 55 * as result of an asserted interrupt. This is critical for powering down a cpu 56 ******************************************************************************/ 57 void gicv2_cpuif_disable(void) 58 { 59 unsigned int val; 60 61 assert(driver_data != NULL); 62 assert(driver_data->gicc_base != 0U); 63 64 /* Disable secure, non-secure interrupts and disable their bypass */ 65 val = gicc_read_ctlr(driver_data->gicc_base); 66 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); 67 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; 68 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; 69 gicc_write_ctlr(driver_data->gicc_base, val); 70 } 71 72 /******************************************************************************* 73 * Per cpu gic distributor setup which will be done by all cpus after a cold 74 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. 75 ******************************************************************************/ 76 void gicv2_pcpu_distif_init(void) 77 { 78 unsigned int ctlr; 79 80 assert(driver_data != NULL); 81 assert(driver_data->gicd_base != 0U); 82 83 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, 84 driver_data->interrupt_props, 85 driver_data->interrupt_props_num); 86 87 /* Enable G0 interrupts if not already */ 88 ctlr = gicd_read_ctlr(driver_data->gicd_base); 89 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) { 90 gicd_write_ctlr(driver_data->gicd_base, 91 ctlr | CTLR_ENABLE_G0_BIT); 92 } 93 } 94 95 /******************************************************************************* 96 * Global gic distributor init which will be done by the primary cpu after a 97 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It 98 * then enables the secure GIC distributor interface. 99 ******************************************************************************/ 100 void gicv2_distif_init(void) 101 { 102 unsigned int ctlr; 103 104 assert(driver_data != NULL); 105 assert(driver_data->gicd_base != 0U); 106 107 /* Disable the distributor before going further */ 108 ctlr = gicd_read_ctlr(driver_data->gicd_base); 109 gicd_write_ctlr(driver_data->gicd_base, 110 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); 111 112 /* Set the default attribute of all SPIs */ 113 gicv2_spis_configure_defaults(driver_data->gicd_base); 114 115 gicv2_secure_spis_configure_props(driver_data->gicd_base, 116 driver_data->interrupt_props, 117 driver_data->interrupt_props_num); 118 119 120 /* Re-enable the secure SPIs now that they have been configured */ 121 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); 122 } 123 124 /******************************************************************************* 125 * Initialize the ARM GICv2 driver with the provided platform inputs 126 ******************************************************************************/ 127 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) 128 { 129 unsigned int gic_version; 130 131 assert(plat_driver_data != NULL); 132 assert(plat_driver_data->gicd_base != 0U); 133 assert(plat_driver_data->gicc_base != 0U); 134 135 assert(plat_driver_data->interrupt_props_num > 0 ? 136 plat_driver_data->interrupt_props != NULL : 1); 137 138 /* Ensure that this is a GICv2 system */ 139 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 140 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) 141 & PIDR2_ARCH_REV_MASK; 142 143 /* 144 * GICv1 with security extension complies with trusted firmware 145 * GICv2 driver as far as virtualization and few tricky power 146 * features are not used. GICv2 features that are not supported 147 * by GICv1 with Security Extensions are: 148 * - virtual interrupt support. 149 * - wake up events. 150 * - writeable GIC state register (for power sequences) 151 * - interrupt priority drop. 152 * - interrupt signal bypass. 153 */ 154 assert((gic_version == ARCH_REV_GICV2) || 155 (gic_version == ARCH_REV_GICV1)); 156 157 driver_data = plat_driver_data; 158 159 /* 160 * The GIC driver data is initialized by the primary CPU with caches 161 * enabled. When the secondary CPU boots up, it initializes the 162 * GICC/GICR interface with the caches disabled. Hence flush the 163 * driver_data to ensure coherency. This is not required if the 164 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY 165 * enabled. 166 */ 167 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 168 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 169 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 170 #endif 171 INFO("ARM GICv2 driver initialized\n"); 172 } 173 174 /****************************************************************************** 175 * This function returns whether FIQ is enabled in the GIC CPU interface. 176 *****************************************************************************/ 177 unsigned int gicv2_is_fiq_enabled(void) 178 { 179 unsigned int gicc_ctlr; 180 181 assert(driver_data != NULL); 182 assert(driver_data->gicc_base != 0U); 183 184 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); 185 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1U; 186 } 187 188 /******************************************************************************* 189 * This function returns the type of the highest priority pending interrupt at 190 * the GIC cpu interface. The return values can be one of the following : 191 * PENDING_G1_INTID : The interrupt type is non secure Group 1. 192 * 0 - 1019 : The interrupt type is secure Group 0. 193 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 194 * sufficient priority to be signaled 195 ******************************************************************************/ 196 unsigned int gicv2_get_pending_interrupt_type(void) 197 { 198 assert(driver_data != NULL); 199 assert(driver_data->gicc_base != 0U); 200 201 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 202 } 203 204 /******************************************************************************* 205 * This function returns the id of the highest priority pending interrupt at 206 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no 207 * interrupt pending. 208 ******************************************************************************/ 209 unsigned int gicv2_get_pending_interrupt_id(void) 210 { 211 unsigned int id; 212 213 assert(driver_data != NULL); 214 assert(driver_data->gicc_base != 0U); 215 216 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 217 218 /* 219 * Find out which non-secure interrupt it is under the assumption that 220 * the GICC_CTLR.AckCtl bit is 0. 221 */ 222 if (id == PENDING_G1_INTID) 223 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; 224 225 return id; 226 } 227 228 /******************************************************************************* 229 * This functions reads the GIC cpu interface Interrupt Acknowledge register 230 * to start handling the pending secure 0 interrupt. It returns the 231 * contents of the IAR. 232 ******************************************************************************/ 233 unsigned int gicv2_acknowledge_interrupt(void) 234 { 235 assert(driver_data != NULL); 236 assert(driver_data->gicc_base != 0U); 237 238 return gicc_read_IAR(driver_data->gicc_base); 239 } 240 241 /******************************************************************************* 242 * This functions writes the GIC cpu interface End Of Interrupt register with 243 * the passed value to finish handling the active secure group 0 interrupt. 244 ******************************************************************************/ 245 void gicv2_end_of_interrupt(unsigned int id) 246 { 247 assert(driver_data != NULL); 248 assert(driver_data->gicc_base != 0U); 249 250 gicc_write_EOIR(driver_data->gicc_base, id); 251 } 252 253 /******************************************************************************* 254 * This function returns the type of the interrupt id depending upon the group 255 * this interrupt has been configured under by the interrupt controller i.e. 256 * group0 secure or group1 non secure. It returns zero for Group 0 secure and 257 * one for Group 1 non secure interrupt. 258 ******************************************************************************/ 259 unsigned int gicv2_get_interrupt_group(unsigned int id) 260 { 261 assert(driver_data != NULL); 262 assert(driver_data->gicd_base != 0U); 263 264 return gicd_get_igroupr(driver_data->gicd_base, id); 265 } 266 267 /******************************************************************************* 268 * This function returns the priority of the interrupt the processor is 269 * currently servicing. 270 ******************************************************************************/ 271 unsigned int gicv2_get_running_priority(void) 272 { 273 assert(driver_data != NULL); 274 assert(driver_data->gicc_base != 0U); 275 276 return gicc_read_rpr(driver_data->gicc_base); 277 } 278 279 /******************************************************************************* 280 * This function sets the GICv2 target mask pattern for the current PE. The PE 281 * target mask is used to translate linear PE index (returned by platform core 282 * position) to a bit mask used when targeting interrupts to a PE, viz. when 283 * raising SGIs and routing SPIs. 284 ******************************************************************************/ 285 void gicv2_set_pe_target_mask(unsigned int proc_num) 286 { 287 assert(driver_data != NULL); 288 assert(driver_data->gicd_base != 0U); 289 assert(driver_data->target_masks != NULL); 290 assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); 291 assert((unsigned int)proc_num < driver_data->target_masks_num); 292 293 /* Return if the target mask is already populated */ 294 if (driver_data->target_masks[proc_num] != 0U) 295 return; 296 297 /* 298 * Update target register corresponding to this CPU and flush for it to 299 * be visible to other CPUs. 300 */ 301 if (driver_data->target_masks[proc_num] == 0U) { 302 driver_data->target_masks[proc_num] = 303 gicv2_get_cpuif_id(driver_data->gicd_base); 304 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 305 /* 306 * PEs only update their own masks. Primary updates it with 307 * caches on. But because secondaries does it with caches off, 308 * all updates go to memory directly, and there's no danger of 309 * secondaries overwriting each others' mask, despite 310 * target_masks[] not being cache line aligned. 311 */ 312 flush_dcache_range((uintptr_t) 313 &driver_data->target_masks[proc_num], 314 sizeof(driver_data->target_masks[proc_num])); 315 #endif 316 } 317 } 318 319 /******************************************************************************* 320 * This function returns the active status of the interrupt (either because the 321 * state is active, or active and pending). 322 ******************************************************************************/ 323 unsigned int gicv2_get_interrupt_active(unsigned int id) 324 { 325 assert(driver_data != NULL); 326 assert(driver_data->gicd_base != 0U); 327 assert(id <= MAX_SPI_ID); 328 329 return gicd_get_isactiver(driver_data->gicd_base, id); 330 } 331 332 /******************************************************************************* 333 * This function enables the interrupt identified by id. 334 ******************************************************************************/ 335 void gicv2_enable_interrupt(unsigned int id) 336 { 337 assert(driver_data != NULL); 338 assert(driver_data->gicd_base != 0U); 339 assert(id <= MAX_SPI_ID); 340 341 /* 342 * Ensure that any shared variable updates depending on out of band 343 * interrupt trigger are observed before enabling interrupt. 344 */ 345 dsbishst(); 346 gicd_set_isenabler(driver_data->gicd_base, id); 347 } 348 349 /******************************************************************************* 350 * This function disables the interrupt identified by id. 351 ******************************************************************************/ 352 void gicv2_disable_interrupt(unsigned int id) 353 { 354 assert(driver_data != NULL); 355 assert(driver_data->gicd_base != 0U); 356 assert(id <= MAX_SPI_ID); 357 358 /* 359 * Disable interrupt, and ensure that any shared variable updates 360 * depending on out of band interrupt trigger are observed afterwards. 361 */ 362 gicd_set_icenabler(driver_data->gicd_base, id); 363 dsbishst(); 364 } 365 366 /******************************************************************************* 367 * This function sets the interrupt priority as supplied for the given interrupt 368 * id. 369 ******************************************************************************/ 370 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) 371 { 372 assert(driver_data != NULL); 373 assert(driver_data->gicd_base != 0U); 374 assert(id <= MAX_SPI_ID); 375 376 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); 377 } 378 379 /******************************************************************************* 380 * This function assigns group for the interrupt identified by id. The group can 381 * be any of GICV2_INTR_GROUP* 382 ******************************************************************************/ 383 void gicv2_set_interrupt_type(unsigned int id, unsigned int type) 384 { 385 assert(driver_data != NULL); 386 assert(driver_data->gicd_base != 0U); 387 assert(id <= MAX_SPI_ID); 388 389 /* Serialize read-modify-write to Distributor registers */ 390 spin_lock(&gic_lock); 391 switch (type) { 392 case GICV2_INTR_GROUP1: 393 gicd_set_igroupr(driver_data->gicd_base, id); 394 break; 395 case GICV2_INTR_GROUP0: 396 gicd_clr_igroupr(driver_data->gicd_base, id); 397 break; 398 default: 399 assert(false); 400 break; 401 } 402 spin_unlock(&gic_lock); 403 } 404 405 /******************************************************************************* 406 * This function raises the specified SGI to requested targets. 407 * 408 * The proc_num parameter must be the linear index of the target PE in the 409 * system. 410 ******************************************************************************/ 411 void gicv2_raise_sgi(int sgi_num, int proc_num) 412 { 413 unsigned int sgir_val, target; 414 415 assert(driver_data != NULL); 416 assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); 417 assert(driver_data->gicd_base != 0U); 418 419 /* 420 * Target masks array must have been supplied, and the core position 421 * should be valid. 422 */ 423 assert(driver_data->target_masks != NULL); 424 assert((unsigned int)proc_num < driver_data->target_masks_num); 425 426 /* Don't raise SGI if the mask hasn't been populated */ 427 target = driver_data->target_masks[proc_num]; 428 assert(target != 0U); 429 430 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num); 431 432 /* 433 * Ensure that any shared variable updates depending on out of band 434 * interrupt trigger are observed before raising SGI. 435 */ 436 dsbishst(); 437 gicd_write_sgir(driver_data->gicd_base, sgir_val); 438 } 439 440 /******************************************************************************* 441 * This function sets the interrupt routing for the given SPI interrupt id. 442 * The interrupt routing is specified in routing mode. The proc_num parameter is 443 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target 444 * all PEs. 445 ******************************************************************************/ 446 void gicv2_set_spi_routing(unsigned int id, int proc_num) 447 { 448 unsigned int target; 449 450 assert(driver_data != NULL); 451 assert(driver_data->gicd_base != 0U); 452 453 assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID)); 454 455 /* 456 * Target masks array must have been supplied, and the core position 457 * should be valid. 458 */ 459 assert(driver_data->target_masks != NULL); 460 assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); 461 assert((unsigned int)proc_num < driver_data->target_masks_num); 462 463 if (proc_num < 0) { 464 /* Target all PEs */ 465 target = GIC_TARGET_CPU_MASK; 466 } else { 467 /* Don't route interrupt if the mask hasn't been populated */ 468 target = driver_data->target_masks[proc_num]; 469 assert(target != 0U); 470 } 471 472 gicd_set_itargetsr(driver_data->gicd_base, id, target); 473 } 474 475 /******************************************************************************* 476 * This function clears the pending status of an interrupt identified by id. 477 ******************************************************************************/ 478 void gicv2_clear_interrupt_pending(unsigned int id) 479 { 480 assert(driver_data != NULL); 481 assert(driver_data->gicd_base != 0U); 482 483 /* SGIs can't be cleared pending */ 484 assert(id >= MIN_PPI_ID); 485 486 /* 487 * Clear pending interrupt, and ensure that any shared variable updates 488 * depending on out of band interrupt trigger are observed afterwards. 489 */ 490 gicd_set_icpendr(driver_data->gicd_base, id); 491 dsbishst(); 492 } 493 494 /******************************************************************************* 495 * This function sets the pending status of an interrupt identified by id. 496 ******************************************************************************/ 497 void gicv2_set_interrupt_pending(unsigned int id) 498 { 499 assert(driver_data != NULL); 500 assert(driver_data->gicd_base != 0U); 501 502 /* SGIs can't be cleared pending */ 503 assert(id >= MIN_PPI_ID); 504 505 /* 506 * Ensure that any shared variable updates depending on out of band 507 * interrupt trigger are observed before setting interrupt pending. 508 */ 509 dsbishst(); 510 gicd_set_ispendr(driver_data->gicd_base, id); 511 } 512 513 /******************************************************************************* 514 * This function sets the PMR register with the supplied value. Returns the 515 * original PMR. 516 ******************************************************************************/ 517 unsigned int gicv2_set_pmr(unsigned int mask) 518 { 519 unsigned int old_mask; 520 521 assert(driver_data != NULL); 522 assert(driver_data->gicc_base != 0U); 523 524 old_mask = gicc_read_pmr(driver_data->gicc_base); 525 526 /* 527 * Order memory updates w.r.t. PMR write, and ensure they're visible 528 * before potential out of band interrupt trigger because of PMR update. 529 */ 530 dmbishst(); 531 gicc_write_pmr(driver_data->gicc_base, mask); 532 dsbishst(); 533 534 return old_mask; 535 } 536 537 /******************************************************************************* 538 * This function updates single interrupt configuration to be level/edge 539 * triggered 540 ******************************************************************************/ 541 void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg) 542 { 543 gicd_set_icfgr(driver_data->gicd_base, id, cfg); 544 } 545