1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include <gicv2.h> 13 #include <interrupt_props.h> 14 #include <spinlock.h> 15 #include "../common/gic_common_private.h" 16 #include "gicv2_private.h" 17 18 static const gicv2_driver_data_t *driver_data; 19 20 /* 21 * Spinlock to guard registers needing read-modify-write. APIs protected by this 22 * spinlock are used either at boot time (when only a single CPU is active), or 23 * when the system is fully coherent. 24 */ 25 spinlock_t gic_lock; 26 27 /******************************************************************************* 28 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass 29 * and set the priority mask register to allow all interrupts to trickle in. 30 ******************************************************************************/ 31 void gicv2_cpuif_enable(void) 32 { 33 unsigned int val; 34 35 assert(driver_data); 36 assert(driver_data->gicc_base); 37 38 /* 39 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 40 * bypass. 41 */ 42 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; 43 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; 44 45 /* Program the idle priority in the PMR */ 46 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); 47 gicc_write_ctlr(driver_data->gicc_base, val); 48 } 49 50 /******************************************************************************* 51 * Place the cpu interface in a state where it can never make a cpu exit wfi as 52 * as result of an asserted interrupt. This is critical for powering down a cpu 53 ******************************************************************************/ 54 void gicv2_cpuif_disable(void) 55 { 56 unsigned int val; 57 58 assert(driver_data); 59 assert(driver_data->gicc_base); 60 61 /* Disable secure, non-secure interrupts and disable their bypass */ 62 val = gicc_read_ctlr(driver_data->gicc_base); 63 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); 64 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; 65 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; 66 gicc_write_ctlr(driver_data->gicc_base, val); 67 } 68 69 /******************************************************************************* 70 * Per cpu gic distributor setup which will be done by all cpus after a cold 71 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. 72 ******************************************************************************/ 73 void gicv2_pcpu_distif_init(void) 74 { 75 unsigned int ctlr; 76 77 assert(driver_data); 78 assert(driver_data->gicd_base); 79 80 #if !ERROR_DEPRECATED 81 if (driver_data->interrupt_props != NULL) { 82 #endif 83 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, 84 driver_data->interrupt_props, 85 driver_data->interrupt_props_num); 86 #if !ERROR_DEPRECATED 87 } else { 88 assert(driver_data->g0_interrupt_array); 89 gicv2_secure_ppi_sgi_setup(driver_data->gicd_base, 90 driver_data->g0_interrupt_num, 91 driver_data->g0_interrupt_array); 92 } 93 #endif 94 95 /* Enable G0 interrupts if not already */ 96 ctlr = gicd_read_ctlr(driver_data->gicd_base); 97 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0) { 98 gicd_write_ctlr(driver_data->gicd_base, 99 ctlr | CTLR_ENABLE_G0_BIT); 100 } 101 } 102 103 /******************************************************************************* 104 * Global gic distributor init which will be done by the primary cpu after a 105 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It 106 * then enables the secure GIC distributor interface. 107 ******************************************************************************/ 108 void gicv2_distif_init(void) 109 { 110 unsigned int ctlr; 111 112 assert(driver_data); 113 assert(driver_data->gicd_base); 114 115 /* Disable the distributor before going further */ 116 ctlr = gicd_read_ctlr(driver_data->gicd_base); 117 gicd_write_ctlr(driver_data->gicd_base, 118 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); 119 120 /* Set the default attribute of all SPIs */ 121 gicv2_spis_configure_defaults(driver_data->gicd_base); 122 123 #if !ERROR_DEPRECATED 124 if (driver_data->interrupt_props != NULL) { 125 #endif 126 gicv2_secure_spis_configure_props(driver_data->gicd_base, 127 driver_data->interrupt_props, 128 driver_data->interrupt_props_num); 129 #if !ERROR_DEPRECATED 130 } else { 131 assert(driver_data->g0_interrupt_array); 132 133 /* Configure the G0 SPIs */ 134 gicv2_secure_spis_configure(driver_data->gicd_base, 135 driver_data->g0_interrupt_num, 136 driver_data->g0_interrupt_array); 137 } 138 #endif 139 140 /* Re-enable the secure SPIs now that they have been configured */ 141 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); 142 } 143 144 /******************************************************************************* 145 * Initialize the ARM GICv2 driver with the provided platform inputs 146 ******************************************************************************/ 147 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) 148 { 149 unsigned int gic_version; 150 assert(plat_driver_data); 151 assert(plat_driver_data->gicd_base); 152 assert(plat_driver_data->gicc_base); 153 154 #if !ERROR_DEPRECATED 155 if (plat_driver_data->interrupt_props == NULL) { 156 /* Interrupt properties array size must be 0 */ 157 assert(plat_driver_data->interrupt_props_num == 0); 158 159 /* The platform should provide a list of secure interrupts */ 160 assert(plat_driver_data->g0_interrupt_array); 161 162 /* 163 * If there are no interrupts of a particular type, then the 164 * number of interrupts of that type should be 0 and vice-versa. 165 */ 166 assert(plat_driver_data->g0_interrupt_array ? 167 plat_driver_data->g0_interrupt_num : 168 plat_driver_data->g0_interrupt_num == 0); 169 } 170 #else 171 assert(plat_driver_data->interrupt_props != NULL); 172 assert(plat_driver_data->interrupt_props_num > 0); 173 #endif 174 175 /* Ensure that this is a GICv2 system */ 176 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 177 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) 178 & PIDR2_ARCH_REV_MASK; 179 assert(gic_version == ARCH_REV_GICV2); 180 181 driver_data = plat_driver_data; 182 183 /* 184 * The GIC driver data is initialized by the primary CPU with caches 185 * enabled. When the secondary CPU boots up, it initializes the 186 * GICC/GICR interface with the caches disabled. Hence flush the 187 * driver_data to ensure coherency. This is not required if the 188 * platform has HW_ASSISTED_COHERENCY enabled. 189 */ 190 #if !HW_ASSISTED_COHERENCY 191 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 192 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 193 #endif 194 INFO("ARM GICv2 driver initialized\n"); 195 } 196 197 /****************************************************************************** 198 * This function returns whether FIQ is enabled in the GIC CPU interface. 199 *****************************************************************************/ 200 unsigned int gicv2_is_fiq_enabled(void) 201 { 202 unsigned int gicc_ctlr; 203 204 assert(driver_data); 205 assert(driver_data->gicc_base); 206 207 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); 208 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1; 209 } 210 211 /******************************************************************************* 212 * This function returns the type of the highest priority pending interrupt at 213 * the GIC cpu interface. The return values can be one of the following : 214 * PENDING_G1_INTID : The interrupt type is non secure Group 1. 215 * 0 - 1019 : The interrupt type is secure Group 0. 216 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 217 * sufficient priority to be signaled 218 ******************************************************************************/ 219 unsigned int gicv2_get_pending_interrupt_type(void) 220 { 221 assert(driver_data); 222 assert(driver_data->gicc_base); 223 224 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 225 } 226 227 /******************************************************************************* 228 * This function returns the id of the highest priority pending interrupt at 229 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no 230 * interrupt pending. 231 ******************************************************************************/ 232 unsigned int gicv2_get_pending_interrupt_id(void) 233 { 234 unsigned int id; 235 236 assert(driver_data); 237 assert(driver_data->gicc_base); 238 239 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 240 241 /* 242 * Find out which non-secure interrupt it is under the assumption that 243 * the GICC_CTLR.AckCtl bit is 0. 244 */ 245 if (id == PENDING_G1_INTID) 246 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; 247 248 return id; 249 } 250 251 /******************************************************************************* 252 * This functions reads the GIC cpu interface Interrupt Acknowledge register 253 * to start handling the pending secure 0 interrupt. It returns the 254 * contents of the IAR. 255 ******************************************************************************/ 256 unsigned int gicv2_acknowledge_interrupt(void) 257 { 258 assert(driver_data); 259 assert(driver_data->gicc_base); 260 261 return gicc_read_IAR(driver_data->gicc_base); 262 } 263 264 /******************************************************************************* 265 * This functions writes the GIC cpu interface End Of Interrupt register with 266 * the passed value to finish handling the active secure group 0 interrupt. 267 ******************************************************************************/ 268 void gicv2_end_of_interrupt(unsigned int id) 269 { 270 assert(driver_data); 271 assert(driver_data->gicc_base); 272 273 gicc_write_EOIR(driver_data->gicc_base, id); 274 } 275 276 /******************************************************************************* 277 * This function returns the type of the interrupt id depending upon the group 278 * this interrupt has been configured under by the interrupt controller i.e. 279 * group0 secure or group1 non secure. It returns zero for Group 0 secure and 280 * one for Group 1 non secure interrupt. 281 ******************************************************************************/ 282 unsigned int gicv2_get_interrupt_group(unsigned int id) 283 { 284 assert(driver_data); 285 assert(driver_data->gicd_base); 286 287 return gicd_get_igroupr(driver_data->gicd_base, id); 288 } 289 290 /******************************************************************************* 291 * This function returns the priority of the interrupt the processor is 292 * currently servicing. 293 ******************************************************************************/ 294 unsigned int gicv2_get_running_priority(void) 295 { 296 assert(driver_data); 297 assert(driver_data->gicc_base); 298 299 return gicc_read_rpr(driver_data->gicc_base); 300 } 301 302 /******************************************************************************* 303 * This function sets the GICv2 target mask pattern for the current PE. The PE 304 * target mask is used to translate linear PE index (returned by platform core 305 * position) to a bit mask used when targeting interrupts to a PE, viz. when 306 * raising SGIs and routing SPIs. 307 ******************************************************************************/ 308 void gicv2_set_pe_target_mask(unsigned int proc_num) 309 { 310 assert(driver_data); 311 assert(driver_data->gicd_base); 312 assert(driver_data->target_masks); 313 assert(proc_num < GICV2_MAX_TARGET_PE); 314 assert(proc_num < driver_data->target_masks_num); 315 316 /* Return if the target mask is already populated */ 317 if (driver_data->target_masks[proc_num]) 318 return; 319 320 /* 321 * Update target register corresponding to this CPU and flush for it to 322 * be visible to other CPUs. 323 */ 324 if (driver_data->target_masks[proc_num] == 0) { 325 driver_data->target_masks[proc_num] = 326 gicv2_get_cpuif_id(driver_data->gicd_base); 327 #if !HW_ASSISTED_COHERENCY 328 /* 329 * PEs only update their own masks. Primary updates it with 330 * caches on. But because secondaries does it with caches off, 331 * all updates go to memory directly, and there's no danger of 332 * secondaries overwriting each others' mask, despite 333 * target_masks[] not being cache line aligned. 334 */ 335 flush_dcache_range((uintptr_t) 336 &driver_data->target_masks[proc_num], 337 sizeof(driver_data->target_masks[proc_num])); 338 #endif 339 } 340 } 341 342 /******************************************************************************* 343 * This function returns the active status of the interrupt (either because the 344 * state is active, or active and pending). 345 ******************************************************************************/ 346 unsigned int gicv2_get_interrupt_active(unsigned int id) 347 { 348 assert(driver_data); 349 assert(driver_data->gicd_base); 350 assert(id <= MAX_SPI_ID); 351 352 return gicd_get_isactiver(driver_data->gicd_base, id); 353 } 354 355 /******************************************************************************* 356 * This function enables the interrupt identified by id. 357 ******************************************************************************/ 358 void gicv2_enable_interrupt(unsigned int id) 359 { 360 assert(driver_data); 361 assert(driver_data->gicd_base); 362 assert(id <= MAX_SPI_ID); 363 364 /* 365 * Ensure that any shared variable updates depending on out of band 366 * interrupt trigger are observed before enabling interrupt. 367 */ 368 dsbishst(); 369 gicd_set_isenabler(driver_data->gicd_base, id); 370 } 371 372 /******************************************************************************* 373 * This function disables the interrupt identified by id. 374 ******************************************************************************/ 375 void gicv2_disable_interrupt(unsigned int id) 376 { 377 assert(driver_data); 378 assert(driver_data->gicd_base); 379 assert(id <= MAX_SPI_ID); 380 381 /* 382 * Disable interrupt, and ensure that any shared variable updates 383 * depending on out of band interrupt trigger are observed afterwards. 384 */ 385 gicd_set_icenabler(driver_data->gicd_base, id); 386 dsbishst(); 387 } 388 389 /******************************************************************************* 390 * This function sets the interrupt priority as supplied for the given interrupt 391 * id. 392 ******************************************************************************/ 393 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) 394 { 395 assert(driver_data); 396 assert(driver_data->gicd_base); 397 assert(id <= MAX_SPI_ID); 398 399 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); 400 } 401 402 /******************************************************************************* 403 * This function assigns group for the interrupt identified by id. The group can 404 * be any of GICV2_INTR_GROUP* 405 ******************************************************************************/ 406 void gicv2_set_interrupt_type(unsigned int id, unsigned int type) 407 { 408 assert(driver_data); 409 assert(driver_data->gicd_base); 410 assert(id <= MAX_SPI_ID); 411 412 /* Serialize read-modify-write to Distributor registers */ 413 spin_lock(&gic_lock); 414 switch (type) { 415 case GICV2_INTR_GROUP1: 416 gicd_set_igroupr(driver_data->gicd_base, id); 417 break; 418 case GICV2_INTR_GROUP0: 419 gicd_clr_igroupr(driver_data->gicd_base, id); 420 break; 421 default: 422 assert(0); 423 } 424 spin_unlock(&gic_lock); 425 } 426 427 /******************************************************************************* 428 * This function raises the specified SGI to requested targets. 429 * 430 * The proc_num parameter must be the linear index of the target PE in the 431 * system. 432 ******************************************************************************/ 433 void gicv2_raise_sgi(int sgi_num, int proc_num) 434 { 435 unsigned int sgir_val, target; 436 437 assert(driver_data); 438 assert(proc_num < GICV2_MAX_TARGET_PE); 439 assert(driver_data->gicd_base); 440 441 /* 442 * Target masks array must have been supplied, and the core position 443 * should be valid. 444 */ 445 assert(driver_data->target_masks); 446 assert(proc_num < driver_data->target_masks_num); 447 448 /* Don't raise SGI if the mask hasn't been populated */ 449 target = driver_data->target_masks[proc_num]; 450 assert(target != 0); 451 452 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num); 453 454 /* 455 * Ensure that any shared variable updates depending on out of band 456 * interrupt trigger are observed before raising SGI. 457 */ 458 dsbishst(); 459 gicd_write_sgir(driver_data->gicd_base, sgir_val); 460 } 461 462 /******************************************************************************* 463 * This function sets the interrupt routing for the given SPI interrupt id. 464 * The interrupt routing is specified in routing mode. The proc_num parameter is 465 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target 466 * all PEs. 467 ******************************************************************************/ 468 void gicv2_set_spi_routing(unsigned int id, int proc_num) 469 { 470 int target; 471 472 assert(driver_data); 473 assert(driver_data->gicd_base); 474 475 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID); 476 477 /* 478 * Target masks array must have been supplied, and the core position 479 * should be valid. 480 */ 481 assert(driver_data->target_masks); 482 assert(proc_num < GICV2_MAX_TARGET_PE); 483 assert(proc_num < driver_data->target_masks_num); 484 485 if (proc_num < 0) { 486 /* Target all PEs */ 487 target = GIC_TARGET_CPU_MASK; 488 } else { 489 /* Don't route interrupt if the mask hasn't been populated */ 490 target = driver_data->target_masks[proc_num]; 491 assert(target != 0); 492 } 493 494 gicd_set_itargetsr(driver_data->gicd_base, id, target); 495 } 496 497 /******************************************************************************* 498 * This function clears the pending status of an interrupt identified by id. 499 ******************************************************************************/ 500 void gicv2_clear_interrupt_pending(unsigned int id) 501 { 502 assert(driver_data); 503 assert(driver_data->gicd_base); 504 505 /* SGIs can't be cleared pending */ 506 assert(id >= MIN_PPI_ID); 507 508 /* 509 * Clear pending interrupt, and ensure that any shared variable updates 510 * depending on out of band interrupt trigger are observed afterwards. 511 */ 512 gicd_set_icpendr(driver_data->gicd_base, id); 513 dsbishst(); 514 } 515 516 /******************************************************************************* 517 * This function sets the pending status of an interrupt identified by id. 518 ******************************************************************************/ 519 void gicv2_set_interrupt_pending(unsigned int id) 520 { 521 assert(driver_data); 522 assert(driver_data->gicd_base); 523 524 /* SGIs can't be cleared pending */ 525 assert(id >= MIN_PPI_ID); 526 527 /* 528 * Ensure that any shared variable updates depending on out of band 529 * interrupt trigger are observed before setting interrupt pending. 530 */ 531 dsbishst(); 532 gicd_set_ispendr(driver_data->gicd_base, id); 533 } 534 535 /******************************************************************************* 536 * This function sets the PMR register with the supplied value. Returns the 537 * original PMR. 538 ******************************************************************************/ 539 unsigned int gicv2_set_pmr(unsigned int mask) 540 { 541 unsigned int old_mask; 542 543 assert(driver_data); 544 assert(driver_data->gicc_base); 545 546 old_mask = gicc_read_pmr(driver_data->gicc_base); 547 548 /* 549 * Order memory updates w.r.t. PMR write, and ensure they're visible 550 * before potential out of band interrupt trigger because of PMR update. 551 */ 552 dmbishst(); 553 gicc_write_pmr(driver_data->gicc_base, mask); 554 dsbishst(); 555 556 return old_mask; 557 } 558