1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include <gicv2.h> 13 #include <interrupt_props.h> 14 #include <spinlock.h> 15 #include "../common/gic_common_private.h" 16 #include "gicv2_private.h" 17 18 static const gicv2_driver_data_t *driver_data; 19 20 /* 21 * Spinlock to guard registers needing read-modify-write. APIs protected by this 22 * spinlock are used either at boot time (when only a single CPU is active), or 23 * when the system is fully coherent. 24 */ 25 static spinlock_t gic_lock; 26 27 /******************************************************************************* 28 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass 29 * and set the priority mask register to allow all interrupts to trickle in. 30 ******************************************************************************/ 31 void gicv2_cpuif_enable(void) 32 { 33 unsigned int val; 34 35 assert(driver_data); 36 assert(driver_data->gicc_base); 37 38 /* 39 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 40 * bypass. 41 */ 42 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; 43 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; 44 45 /* Program the idle priority in the PMR */ 46 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); 47 gicc_write_ctlr(driver_data->gicc_base, val); 48 } 49 50 /******************************************************************************* 51 * Place the cpu interface in a state where it can never make a cpu exit wfi as 52 * as result of an asserted interrupt. This is critical for powering down a cpu 53 ******************************************************************************/ 54 void gicv2_cpuif_disable(void) 55 { 56 unsigned int val; 57 58 assert(driver_data); 59 assert(driver_data->gicc_base); 60 61 /* Disable secure, non-secure interrupts and disable their bypass */ 62 val = gicc_read_ctlr(driver_data->gicc_base); 63 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); 64 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; 65 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; 66 gicc_write_ctlr(driver_data->gicc_base, val); 67 } 68 69 /******************************************************************************* 70 * Per cpu gic distributor setup which will be done by all cpus after a cold 71 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. 72 ******************************************************************************/ 73 void gicv2_pcpu_distif_init(void) 74 { 75 unsigned int ctlr; 76 77 assert(driver_data); 78 assert(driver_data->gicd_base); 79 80 #if !ERROR_DEPRECATED 81 if (driver_data->interrupt_props != NULL) { 82 #endif 83 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, 84 driver_data->interrupt_props, 85 driver_data->interrupt_props_num); 86 #if !ERROR_DEPRECATED 87 } else { 88 /* 89 * Suppress deprecated declaration warnings in compatibility 90 * function 91 */ 92 #pragma GCC diagnostic push 93 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 94 assert(driver_data->g0_interrupt_array); 95 gicv2_secure_ppi_sgi_setup(driver_data->gicd_base, 96 driver_data->g0_interrupt_num, 97 driver_data->g0_interrupt_array); 98 #pragma GCC diagnostic pop 99 } 100 #endif 101 102 /* Enable G0 interrupts if not already */ 103 ctlr = gicd_read_ctlr(driver_data->gicd_base); 104 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0) { 105 gicd_write_ctlr(driver_data->gicd_base, 106 ctlr | CTLR_ENABLE_G0_BIT); 107 } 108 } 109 110 /******************************************************************************* 111 * Global gic distributor init which will be done by the primary cpu after a 112 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It 113 * then enables the secure GIC distributor interface. 114 ******************************************************************************/ 115 void gicv2_distif_init(void) 116 { 117 unsigned int ctlr; 118 119 assert(driver_data); 120 assert(driver_data->gicd_base); 121 122 /* Disable the distributor before going further */ 123 ctlr = gicd_read_ctlr(driver_data->gicd_base); 124 gicd_write_ctlr(driver_data->gicd_base, 125 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); 126 127 /* Set the default attribute of all SPIs */ 128 gicv2_spis_configure_defaults(driver_data->gicd_base); 129 130 #if !ERROR_DEPRECATED 131 if (driver_data->interrupt_props != NULL) { 132 #endif 133 gicv2_secure_spis_configure_props(driver_data->gicd_base, 134 driver_data->interrupt_props, 135 driver_data->interrupt_props_num); 136 #if !ERROR_DEPRECATED 137 } else { 138 /* 139 * Suppress deprecated declaration warnings in compatibility 140 * function 141 */ 142 #pragma GCC diagnostic push 143 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 144 145 assert(driver_data->g0_interrupt_array); 146 147 /* Configure the G0 SPIs */ 148 gicv2_secure_spis_configure(driver_data->gicd_base, 149 driver_data->g0_interrupt_num, 150 driver_data->g0_interrupt_array); 151 #pragma GCC diagnostic pop 152 } 153 #endif 154 155 /* Re-enable the secure SPIs now that they have been configured */ 156 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); 157 } 158 159 /******************************************************************************* 160 * Initialize the ARM GICv2 driver with the provided platform inputs 161 ******************************************************************************/ 162 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) 163 { 164 unsigned int gic_version; 165 assert(plat_driver_data); 166 assert(plat_driver_data->gicd_base); 167 assert(plat_driver_data->gicc_base); 168 169 #if !ERROR_DEPRECATED 170 if (plat_driver_data->interrupt_props == NULL) { 171 /* Interrupt properties array size must be 0 */ 172 assert(plat_driver_data->interrupt_props_num == 0); 173 174 /* 175 * Suppress deprecated declaration warnings in compatibility 176 * function 177 */ 178 #pragma GCC diagnostic push 179 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 180 181 /* 182 * If there are no interrupts of a particular type, then the 183 * number of interrupts of that type should be 0 and vice-versa. 184 */ 185 assert(plat_driver_data->g0_interrupt_array ? 186 plat_driver_data->g0_interrupt_num : 187 plat_driver_data->g0_interrupt_num == 0); 188 #pragma GCC diagnostic pop 189 190 WARN("Using deprecated integer interrupt array in " 191 "gicv2_driver_data_t\n"); 192 WARN("Please migrate to using an interrupt_prop_t array\n"); 193 } 194 #else 195 assert(plat_driver_data->interrupt_props_num > 0 ? 196 plat_driver_data->interrupt_props != NULL : 1); 197 #endif 198 199 /* Ensure that this is a GICv2 system */ 200 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 201 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) 202 & PIDR2_ARCH_REV_MASK; 203 204 /* 205 * GICv1 with security extension complies with trusted firmware 206 * GICv2 driver as far as virtualization and few tricky power 207 * features are not used. GICv2 features that are not supported 208 * by GICv1 with Security Extensions are: 209 * - virtual interrupt support. 210 * - wake up events. 211 * - writeable GIC state register (for power sequences) 212 * - interrupt priority drop. 213 * - interrupt signal bypass. 214 */ 215 assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1); 216 217 driver_data = plat_driver_data; 218 219 /* 220 * The GIC driver data is initialized by the primary CPU with caches 221 * enabled. When the secondary CPU boots up, it initializes the 222 * GICC/GICR interface with the caches disabled. Hence flush the 223 * driver_data to ensure coherency. This is not required if the 224 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY 225 * enabled. 226 */ 227 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 228 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 229 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 230 #endif 231 INFO("ARM GICv2 driver initialized\n"); 232 } 233 234 /****************************************************************************** 235 * This function returns whether FIQ is enabled in the GIC CPU interface. 236 *****************************************************************************/ 237 unsigned int gicv2_is_fiq_enabled(void) 238 { 239 unsigned int gicc_ctlr; 240 241 assert(driver_data); 242 assert(driver_data->gicc_base); 243 244 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); 245 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1; 246 } 247 248 /******************************************************************************* 249 * This function returns the type of the highest priority pending interrupt at 250 * the GIC cpu interface. The return values can be one of the following : 251 * PENDING_G1_INTID : The interrupt type is non secure Group 1. 252 * 0 - 1019 : The interrupt type is secure Group 0. 253 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 254 * sufficient priority to be signaled 255 ******************************************************************************/ 256 unsigned int gicv2_get_pending_interrupt_type(void) 257 { 258 assert(driver_data); 259 assert(driver_data->gicc_base); 260 261 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 262 } 263 264 /******************************************************************************* 265 * This function returns the id of the highest priority pending interrupt at 266 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no 267 * interrupt pending. 268 ******************************************************************************/ 269 unsigned int gicv2_get_pending_interrupt_id(void) 270 { 271 unsigned int id; 272 273 assert(driver_data); 274 assert(driver_data->gicc_base); 275 276 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 277 278 /* 279 * Find out which non-secure interrupt it is under the assumption that 280 * the GICC_CTLR.AckCtl bit is 0. 281 */ 282 if (id == PENDING_G1_INTID) 283 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; 284 285 return id; 286 } 287 288 /******************************************************************************* 289 * This functions reads the GIC cpu interface Interrupt Acknowledge register 290 * to start handling the pending secure 0 interrupt. It returns the 291 * contents of the IAR. 292 ******************************************************************************/ 293 unsigned int gicv2_acknowledge_interrupt(void) 294 { 295 assert(driver_data); 296 assert(driver_data->gicc_base); 297 298 return gicc_read_IAR(driver_data->gicc_base); 299 } 300 301 /******************************************************************************* 302 * This functions writes the GIC cpu interface End Of Interrupt register with 303 * the passed value to finish handling the active secure group 0 interrupt. 304 ******************************************************************************/ 305 void gicv2_end_of_interrupt(unsigned int id) 306 { 307 assert(driver_data); 308 assert(driver_data->gicc_base); 309 310 gicc_write_EOIR(driver_data->gicc_base, id); 311 } 312 313 /******************************************************************************* 314 * This function returns the type of the interrupt id depending upon the group 315 * this interrupt has been configured under by the interrupt controller i.e. 316 * group0 secure or group1 non secure. It returns zero for Group 0 secure and 317 * one for Group 1 non secure interrupt. 318 ******************************************************************************/ 319 unsigned int gicv2_get_interrupt_group(unsigned int id) 320 { 321 assert(driver_data); 322 assert(driver_data->gicd_base); 323 324 return gicd_get_igroupr(driver_data->gicd_base, id); 325 } 326 327 /******************************************************************************* 328 * This function returns the priority of the interrupt the processor is 329 * currently servicing. 330 ******************************************************************************/ 331 unsigned int gicv2_get_running_priority(void) 332 { 333 assert(driver_data); 334 assert(driver_data->gicc_base); 335 336 return gicc_read_rpr(driver_data->gicc_base); 337 } 338 339 /******************************************************************************* 340 * This function sets the GICv2 target mask pattern for the current PE. The PE 341 * target mask is used to translate linear PE index (returned by platform core 342 * position) to a bit mask used when targeting interrupts to a PE, viz. when 343 * raising SGIs and routing SPIs. 344 ******************************************************************************/ 345 void gicv2_set_pe_target_mask(unsigned int proc_num) 346 { 347 assert(driver_data); 348 assert(driver_data->gicd_base); 349 assert(driver_data->target_masks); 350 assert(proc_num < GICV2_MAX_TARGET_PE); 351 assert(proc_num < driver_data->target_masks_num); 352 353 /* Return if the target mask is already populated */ 354 if (driver_data->target_masks[proc_num]) 355 return; 356 357 /* 358 * Update target register corresponding to this CPU and flush for it to 359 * be visible to other CPUs. 360 */ 361 if (driver_data->target_masks[proc_num] == 0) { 362 driver_data->target_masks[proc_num] = 363 gicv2_get_cpuif_id(driver_data->gicd_base); 364 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 365 /* 366 * PEs only update their own masks. Primary updates it with 367 * caches on. But because secondaries does it with caches off, 368 * all updates go to memory directly, and there's no danger of 369 * secondaries overwriting each others' mask, despite 370 * target_masks[] not being cache line aligned. 371 */ 372 flush_dcache_range((uintptr_t) 373 &driver_data->target_masks[proc_num], 374 sizeof(driver_data->target_masks[proc_num])); 375 #endif 376 } 377 } 378 379 /******************************************************************************* 380 * This function returns the active status of the interrupt (either because the 381 * state is active, or active and pending). 382 ******************************************************************************/ 383 unsigned int gicv2_get_interrupt_active(unsigned int id) 384 { 385 assert(driver_data); 386 assert(driver_data->gicd_base); 387 assert(id <= MAX_SPI_ID); 388 389 return gicd_get_isactiver(driver_data->gicd_base, id); 390 } 391 392 /******************************************************************************* 393 * This function enables the interrupt identified by id. 394 ******************************************************************************/ 395 void gicv2_enable_interrupt(unsigned int id) 396 { 397 assert(driver_data); 398 assert(driver_data->gicd_base); 399 assert(id <= MAX_SPI_ID); 400 401 /* 402 * Ensure that any shared variable updates depending on out of band 403 * interrupt trigger are observed before enabling interrupt. 404 */ 405 dsbishst(); 406 gicd_set_isenabler(driver_data->gicd_base, id); 407 } 408 409 /******************************************************************************* 410 * This function disables the interrupt identified by id. 411 ******************************************************************************/ 412 void gicv2_disable_interrupt(unsigned int id) 413 { 414 assert(driver_data); 415 assert(driver_data->gicd_base); 416 assert(id <= MAX_SPI_ID); 417 418 /* 419 * Disable interrupt, and ensure that any shared variable updates 420 * depending on out of band interrupt trigger are observed afterwards. 421 */ 422 gicd_set_icenabler(driver_data->gicd_base, id); 423 dsbishst(); 424 } 425 426 /******************************************************************************* 427 * This function sets the interrupt priority as supplied for the given interrupt 428 * id. 429 ******************************************************************************/ 430 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) 431 { 432 assert(driver_data); 433 assert(driver_data->gicd_base); 434 assert(id <= MAX_SPI_ID); 435 436 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); 437 } 438 439 /******************************************************************************* 440 * This function assigns group for the interrupt identified by id. The group can 441 * be any of GICV2_INTR_GROUP* 442 ******************************************************************************/ 443 void gicv2_set_interrupt_type(unsigned int id, unsigned int type) 444 { 445 assert(driver_data); 446 assert(driver_data->gicd_base); 447 assert(id <= MAX_SPI_ID); 448 449 /* Serialize read-modify-write to Distributor registers */ 450 spin_lock(&gic_lock); 451 switch (type) { 452 case GICV2_INTR_GROUP1: 453 gicd_set_igroupr(driver_data->gicd_base, id); 454 break; 455 case GICV2_INTR_GROUP0: 456 gicd_clr_igroupr(driver_data->gicd_base, id); 457 break; 458 default: 459 assert(0); 460 break; 461 } 462 spin_unlock(&gic_lock); 463 } 464 465 /******************************************************************************* 466 * This function raises the specified SGI to requested targets. 467 * 468 * The proc_num parameter must be the linear index of the target PE in the 469 * system. 470 ******************************************************************************/ 471 void gicv2_raise_sgi(int sgi_num, int proc_num) 472 { 473 unsigned int sgir_val, target; 474 475 assert(driver_data); 476 assert(proc_num < GICV2_MAX_TARGET_PE); 477 assert(driver_data->gicd_base); 478 479 /* 480 * Target masks array must have been supplied, and the core position 481 * should be valid. 482 */ 483 assert(driver_data->target_masks); 484 assert(proc_num < driver_data->target_masks_num); 485 486 /* Don't raise SGI if the mask hasn't been populated */ 487 target = driver_data->target_masks[proc_num]; 488 assert(target != 0); 489 490 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num); 491 492 /* 493 * Ensure that any shared variable updates depending on out of band 494 * interrupt trigger are observed before raising SGI. 495 */ 496 dsbishst(); 497 gicd_write_sgir(driver_data->gicd_base, sgir_val); 498 } 499 500 /******************************************************************************* 501 * This function sets the interrupt routing for the given SPI interrupt id. 502 * The interrupt routing is specified in routing mode. The proc_num parameter is 503 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target 504 * all PEs. 505 ******************************************************************************/ 506 void gicv2_set_spi_routing(unsigned int id, int proc_num) 507 { 508 int target; 509 510 assert(driver_data); 511 assert(driver_data->gicd_base); 512 513 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID); 514 515 /* 516 * Target masks array must have been supplied, and the core position 517 * should be valid. 518 */ 519 assert(driver_data->target_masks); 520 assert(proc_num < GICV2_MAX_TARGET_PE); 521 assert(proc_num < driver_data->target_masks_num); 522 523 if (proc_num < 0) { 524 /* Target all PEs */ 525 target = GIC_TARGET_CPU_MASK; 526 } else { 527 /* Don't route interrupt if the mask hasn't been populated */ 528 target = driver_data->target_masks[proc_num]; 529 assert(target != 0); 530 } 531 532 gicd_set_itargetsr(driver_data->gicd_base, id, target); 533 } 534 535 /******************************************************************************* 536 * This function clears the pending status of an interrupt identified by id. 537 ******************************************************************************/ 538 void gicv2_clear_interrupt_pending(unsigned int id) 539 { 540 assert(driver_data); 541 assert(driver_data->gicd_base); 542 543 /* SGIs can't be cleared pending */ 544 assert(id >= MIN_PPI_ID); 545 546 /* 547 * Clear pending interrupt, and ensure that any shared variable updates 548 * depending on out of band interrupt trigger are observed afterwards. 549 */ 550 gicd_set_icpendr(driver_data->gicd_base, id); 551 dsbishst(); 552 } 553 554 /******************************************************************************* 555 * This function sets the pending status of an interrupt identified by id. 556 ******************************************************************************/ 557 void gicv2_set_interrupt_pending(unsigned int id) 558 { 559 assert(driver_data); 560 assert(driver_data->gicd_base); 561 562 /* SGIs can't be cleared pending */ 563 assert(id >= MIN_PPI_ID); 564 565 /* 566 * Ensure that any shared variable updates depending on out of band 567 * interrupt trigger are observed before setting interrupt pending. 568 */ 569 dsbishst(); 570 gicd_set_ispendr(driver_data->gicd_base, id); 571 } 572 573 /******************************************************************************* 574 * This function sets the PMR register with the supplied value. Returns the 575 * original PMR. 576 ******************************************************************************/ 577 unsigned int gicv2_set_pmr(unsigned int mask) 578 { 579 unsigned int old_mask; 580 581 assert(driver_data); 582 assert(driver_data->gicc_base); 583 584 old_mask = gicc_read_pmr(driver_data->gicc_base); 585 586 /* 587 * Order memory updates w.r.t. PMR write, and ensure they're visible 588 * before potential out of band interrupt trigger because of PMR update. 589 */ 590 dmbishst(); 591 gicc_write_pmr(driver_data->gicc_base, mask); 592 dsbishst(); 593 594 return old_mask; 595 } 596