1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include <gicv2.h> 13 #include <interrupt_props.h> 14 #include <spinlock.h> 15 #include <stdbool.h> 16 17 #include "../common/gic_common_private.h" 18 #include "gicv2_private.h" 19 20 static const gicv2_driver_data_t *driver_data; 21 22 /* 23 * Spinlock to guard registers needing read-modify-write. APIs protected by this 24 * spinlock are used either at boot time (when only a single CPU is active), or 25 * when the system is fully coherent. 26 */ 27 static spinlock_t gic_lock; 28 29 /******************************************************************************* 30 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass 31 * and set the priority mask register to allow all interrupts to trickle in. 32 ******************************************************************************/ 33 void gicv2_cpuif_enable(void) 34 { 35 unsigned int val; 36 37 assert(driver_data != NULL); 38 assert(driver_data->gicc_base != 0U); 39 40 /* 41 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 42 * bypass. 43 */ 44 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; 45 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; 46 47 /* Program the idle priority in the PMR */ 48 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); 49 gicc_write_ctlr(driver_data->gicc_base, val); 50 } 51 52 /******************************************************************************* 53 * Place the cpu interface in a state where it can never make a cpu exit wfi as 54 * as result of an asserted interrupt. This is critical for powering down a cpu 55 ******************************************************************************/ 56 void gicv2_cpuif_disable(void) 57 { 58 unsigned int val; 59 60 assert(driver_data != NULL); 61 assert(driver_data->gicc_base != 0U); 62 63 /* Disable secure, non-secure interrupts and disable their bypass */ 64 val = gicc_read_ctlr(driver_data->gicc_base); 65 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); 66 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; 67 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; 68 gicc_write_ctlr(driver_data->gicc_base, val); 69 } 70 71 /******************************************************************************* 72 * Per cpu gic distributor setup which will be done by all cpus after a cold 73 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. 74 ******************************************************************************/ 75 void gicv2_pcpu_distif_init(void) 76 { 77 unsigned int ctlr; 78 79 assert(driver_data != NULL); 80 assert(driver_data->gicd_base != 0U); 81 82 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, 83 driver_data->interrupt_props, 84 driver_data->interrupt_props_num); 85 86 /* Enable G0 interrupts if not already */ 87 ctlr = gicd_read_ctlr(driver_data->gicd_base); 88 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) { 89 gicd_write_ctlr(driver_data->gicd_base, 90 ctlr | CTLR_ENABLE_G0_BIT); 91 } 92 } 93 94 /******************************************************************************* 95 * Global gic distributor init which will be done by the primary cpu after a 96 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It 97 * then enables the secure GIC distributor interface. 98 ******************************************************************************/ 99 void gicv2_distif_init(void) 100 { 101 unsigned int ctlr; 102 103 assert(driver_data != NULL); 104 assert(driver_data->gicd_base != 0U); 105 106 /* Disable the distributor before going further */ 107 ctlr = gicd_read_ctlr(driver_data->gicd_base); 108 gicd_write_ctlr(driver_data->gicd_base, 109 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); 110 111 /* Set the default attribute of all SPIs */ 112 gicv2_spis_configure_defaults(driver_data->gicd_base); 113 114 gicv2_secure_spis_configure_props(driver_data->gicd_base, 115 driver_data->interrupt_props, 116 driver_data->interrupt_props_num); 117 118 119 /* Re-enable the secure SPIs now that they have been configured */ 120 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); 121 } 122 123 /******************************************************************************* 124 * Initialize the ARM GICv2 driver with the provided platform inputs 125 ******************************************************************************/ 126 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) 127 { 128 unsigned int gic_version; 129 130 assert(plat_driver_data != NULL); 131 assert(plat_driver_data->gicd_base != 0U); 132 assert(plat_driver_data->gicc_base != 0U); 133 134 assert(plat_driver_data->interrupt_props_num > 0 ? 135 plat_driver_data->interrupt_props != NULL : 1); 136 137 /* Ensure that this is a GICv2 system */ 138 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 139 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) 140 & PIDR2_ARCH_REV_MASK; 141 142 /* 143 * GICv1 with security extension complies with trusted firmware 144 * GICv2 driver as far as virtualization and few tricky power 145 * features are not used. GICv2 features that are not supported 146 * by GICv1 with Security Extensions are: 147 * - virtual interrupt support. 148 * - wake up events. 149 * - writeable GIC state register (for power sequences) 150 * - interrupt priority drop. 151 * - interrupt signal bypass. 152 */ 153 assert((gic_version == ARCH_REV_GICV2) || 154 (gic_version == ARCH_REV_GICV1)); 155 156 driver_data = plat_driver_data; 157 158 /* 159 * The GIC driver data is initialized by the primary CPU with caches 160 * enabled. When the secondary CPU boots up, it initializes the 161 * GICC/GICR interface with the caches disabled. Hence flush the 162 * driver_data to ensure coherency. This is not required if the 163 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY 164 * enabled. 165 */ 166 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 167 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 168 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 169 #endif 170 INFO("ARM GICv2 driver initialized\n"); 171 } 172 173 /****************************************************************************** 174 * This function returns whether FIQ is enabled in the GIC CPU interface. 175 *****************************************************************************/ 176 unsigned int gicv2_is_fiq_enabled(void) 177 { 178 unsigned int gicc_ctlr; 179 180 assert(driver_data != NULL); 181 assert(driver_data->gicc_base != 0U); 182 183 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); 184 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1U; 185 } 186 187 /******************************************************************************* 188 * This function returns the type of the highest priority pending interrupt at 189 * the GIC cpu interface. The return values can be one of the following : 190 * PENDING_G1_INTID : The interrupt type is non secure Group 1. 191 * 0 - 1019 : The interrupt type is secure Group 0. 192 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 193 * sufficient priority to be signaled 194 ******************************************************************************/ 195 unsigned int gicv2_get_pending_interrupt_type(void) 196 { 197 assert(driver_data != NULL); 198 assert(driver_data->gicc_base != 0U); 199 200 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 201 } 202 203 /******************************************************************************* 204 * This function returns the id of the highest priority pending interrupt at 205 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no 206 * interrupt pending. 207 ******************************************************************************/ 208 unsigned int gicv2_get_pending_interrupt_id(void) 209 { 210 unsigned int id; 211 212 assert(driver_data != NULL); 213 assert(driver_data->gicc_base != 0U); 214 215 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 216 217 /* 218 * Find out which non-secure interrupt it is under the assumption that 219 * the GICC_CTLR.AckCtl bit is 0. 220 */ 221 if (id == PENDING_G1_INTID) 222 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; 223 224 return id; 225 } 226 227 /******************************************************************************* 228 * This functions reads the GIC cpu interface Interrupt Acknowledge register 229 * to start handling the pending secure 0 interrupt. It returns the 230 * contents of the IAR. 231 ******************************************************************************/ 232 unsigned int gicv2_acknowledge_interrupt(void) 233 { 234 assert(driver_data != NULL); 235 assert(driver_data->gicc_base != 0U); 236 237 return gicc_read_IAR(driver_data->gicc_base); 238 } 239 240 /******************************************************************************* 241 * This functions writes the GIC cpu interface End Of Interrupt register with 242 * the passed value to finish handling the active secure group 0 interrupt. 243 ******************************************************************************/ 244 void gicv2_end_of_interrupt(unsigned int id) 245 { 246 assert(driver_data != NULL); 247 assert(driver_data->gicc_base != 0U); 248 249 gicc_write_EOIR(driver_data->gicc_base, id); 250 } 251 252 /******************************************************************************* 253 * This function returns the type of the interrupt id depending upon the group 254 * this interrupt has been configured under by the interrupt controller i.e. 255 * group0 secure or group1 non secure. It returns zero for Group 0 secure and 256 * one for Group 1 non secure interrupt. 257 ******************************************************************************/ 258 unsigned int gicv2_get_interrupt_group(unsigned int id) 259 { 260 assert(driver_data != NULL); 261 assert(driver_data->gicd_base != 0U); 262 263 return gicd_get_igroupr(driver_data->gicd_base, id); 264 } 265 266 /******************************************************************************* 267 * This function returns the priority of the interrupt the processor is 268 * currently servicing. 269 ******************************************************************************/ 270 unsigned int gicv2_get_running_priority(void) 271 { 272 assert(driver_data != NULL); 273 assert(driver_data->gicc_base != 0U); 274 275 return gicc_read_rpr(driver_data->gicc_base); 276 } 277 278 /******************************************************************************* 279 * This function sets the GICv2 target mask pattern for the current PE. The PE 280 * target mask is used to translate linear PE index (returned by platform core 281 * position) to a bit mask used when targeting interrupts to a PE, viz. when 282 * raising SGIs and routing SPIs. 283 ******************************************************************************/ 284 void gicv2_set_pe_target_mask(unsigned int proc_num) 285 { 286 assert(driver_data != NULL); 287 assert(driver_data->gicd_base != 0U); 288 assert(driver_data->target_masks != NULL); 289 assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); 290 assert((unsigned int)proc_num < driver_data->target_masks_num); 291 292 /* Return if the target mask is already populated */ 293 if (driver_data->target_masks[proc_num] != 0U) 294 return; 295 296 /* 297 * Update target register corresponding to this CPU and flush for it to 298 * be visible to other CPUs. 299 */ 300 if (driver_data->target_masks[proc_num] == 0U) { 301 driver_data->target_masks[proc_num] = 302 gicv2_get_cpuif_id(driver_data->gicd_base); 303 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 304 /* 305 * PEs only update their own masks. Primary updates it with 306 * caches on. But because secondaries does it with caches off, 307 * all updates go to memory directly, and there's no danger of 308 * secondaries overwriting each others' mask, despite 309 * target_masks[] not being cache line aligned. 310 */ 311 flush_dcache_range((uintptr_t) 312 &driver_data->target_masks[proc_num], 313 sizeof(driver_data->target_masks[proc_num])); 314 #endif 315 } 316 } 317 318 /******************************************************************************* 319 * This function returns the active status of the interrupt (either because the 320 * state is active, or active and pending). 321 ******************************************************************************/ 322 unsigned int gicv2_get_interrupt_active(unsigned int id) 323 { 324 assert(driver_data != NULL); 325 assert(driver_data->gicd_base != 0U); 326 assert(id <= MAX_SPI_ID); 327 328 return gicd_get_isactiver(driver_data->gicd_base, id); 329 } 330 331 /******************************************************************************* 332 * This function enables the interrupt identified by id. 333 ******************************************************************************/ 334 void gicv2_enable_interrupt(unsigned int id) 335 { 336 assert(driver_data != NULL); 337 assert(driver_data->gicd_base != 0U); 338 assert(id <= MAX_SPI_ID); 339 340 /* 341 * Ensure that any shared variable updates depending on out of band 342 * interrupt trigger are observed before enabling interrupt. 343 */ 344 dsbishst(); 345 gicd_set_isenabler(driver_data->gicd_base, id); 346 } 347 348 /******************************************************************************* 349 * This function disables the interrupt identified by id. 350 ******************************************************************************/ 351 void gicv2_disable_interrupt(unsigned int id) 352 { 353 assert(driver_data != NULL); 354 assert(driver_data->gicd_base != 0U); 355 assert(id <= MAX_SPI_ID); 356 357 /* 358 * Disable interrupt, and ensure that any shared variable updates 359 * depending on out of band interrupt trigger are observed afterwards. 360 */ 361 gicd_set_icenabler(driver_data->gicd_base, id); 362 dsbishst(); 363 } 364 365 /******************************************************************************* 366 * This function sets the interrupt priority as supplied for the given interrupt 367 * id. 368 ******************************************************************************/ 369 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) 370 { 371 assert(driver_data != NULL); 372 assert(driver_data->gicd_base != 0U); 373 assert(id <= MAX_SPI_ID); 374 375 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); 376 } 377 378 /******************************************************************************* 379 * This function assigns group for the interrupt identified by id. The group can 380 * be any of GICV2_INTR_GROUP* 381 ******************************************************************************/ 382 void gicv2_set_interrupt_type(unsigned int id, unsigned int type) 383 { 384 assert(driver_data != NULL); 385 assert(driver_data->gicd_base != 0U); 386 assert(id <= MAX_SPI_ID); 387 388 /* Serialize read-modify-write to Distributor registers */ 389 spin_lock(&gic_lock); 390 switch (type) { 391 case GICV2_INTR_GROUP1: 392 gicd_set_igroupr(driver_data->gicd_base, id); 393 break; 394 case GICV2_INTR_GROUP0: 395 gicd_clr_igroupr(driver_data->gicd_base, id); 396 break; 397 default: 398 assert(false); 399 break; 400 } 401 spin_unlock(&gic_lock); 402 } 403 404 /******************************************************************************* 405 * This function raises the specified SGI to requested targets. 406 * 407 * The proc_num parameter must be the linear index of the target PE in the 408 * system. 409 ******************************************************************************/ 410 void gicv2_raise_sgi(int sgi_num, int proc_num) 411 { 412 unsigned int sgir_val, target; 413 414 assert(driver_data != NULL); 415 assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); 416 assert(driver_data->gicd_base != 0U); 417 418 /* 419 * Target masks array must have been supplied, and the core position 420 * should be valid. 421 */ 422 assert(driver_data->target_masks != NULL); 423 assert((unsigned int)proc_num < driver_data->target_masks_num); 424 425 /* Don't raise SGI if the mask hasn't been populated */ 426 target = driver_data->target_masks[proc_num]; 427 assert(target != 0U); 428 429 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num); 430 431 /* 432 * Ensure that any shared variable updates depending on out of band 433 * interrupt trigger are observed before raising SGI. 434 */ 435 dsbishst(); 436 gicd_write_sgir(driver_data->gicd_base, sgir_val); 437 } 438 439 /******************************************************************************* 440 * This function sets the interrupt routing for the given SPI interrupt id. 441 * The interrupt routing is specified in routing mode. The proc_num parameter is 442 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target 443 * all PEs. 444 ******************************************************************************/ 445 void gicv2_set_spi_routing(unsigned int id, int proc_num) 446 { 447 unsigned int target; 448 449 assert(driver_data != NULL); 450 assert(driver_data->gicd_base != 0U); 451 452 assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID)); 453 454 /* 455 * Target masks array must have been supplied, and the core position 456 * should be valid. 457 */ 458 assert(driver_data->target_masks != NULL); 459 assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); 460 assert((unsigned int)proc_num < driver_data->target_masks_num); 461 462 if (proc_num < 0) { 463 /* Target all PEs */ 464 target = GIC_TARGET_CPU_MASK; 465 } else { 466 /* Don't route interrupt if the mask hasn't been populated */ 467 target = driver_data->target_masks[proc_num]; 468 assert(target != 0U); 469 } 470 471 gicd_set_itargetsr(driver_data->gicd_base, id, target); 472 } 473 474 /******************************************************************************* 475 * This function clears the pending status of an interrupt identified by id. 476 ******************************************************************************/ 477 void gicv2_clear_interrupt_pending(unsigned int id) 478 { 479 assert(driver_data != NULL); 480 assert(driver_data->gicd_base != 0U); 481 482 /* SGIs can't be cleared pending */ 483 assert(id >= MIN_PPI_ID); 484 485 /* 486 * Clear pending interrupt, and ensure that any shared variable updates 487 * depending on out of band interrupt trigger are observed afterwards. 488 */ 489 gicd_set_icpendr(driver_data->gicd_base, id); 490 dsbishst(); 491 } 492 493 /******************************************************************************* 494 * This function sets the pending status of an interrupt identified by id. 495 ******************************************************************************/ 496 void gicv2_set_interrupt_pending(unsigned int id) 497 { 498 assert(driver_data != NULL); 499 assert(driver_data->gicd_base != 0U); 500 501 /* SGIs can't be cleared pending */ 502 assert(id >= MIN_PPI_ID); 503 504 /* 505 * Ensure that any shared variable updates depending on out of band 506 * interrupt trigger are observed before setting interrupt pending. 507 */ 508 dsbishst(); 509 gicd_set_ispendr(driver_data->gicd_base, id); 510 } 511 512 /******************************************************************************* 513 * This function sets the PMR register with the supplied value. Returns the 514 * original PMR. 515 ******************************************************************************/ 516 unsigned int gicv2_set_pmr(unsigned int mask) 517 { 518 unsigned int old_mask; 519 520 assert(driver_data != NULL); 521 assert(driver_data->gicc_base != 0U); 522 523 old_mask = gicc_read_pmr(driver_data->gicc_base); 524 525 /* 526 * Order memory updates w.r.t. PMR write, and ensure they're visible 527 * before potential out of band interrupt trigger because of PMR update. 528 */ 529 dmbishst(); 530 gicc_write_pmr(driver_data->gicc_base, mask); 531 dsbishst(); 532 533 return old_mask; 534 } 535 536 /******************************************************************************* 537 * This function updates single interrupt configuration to be level/edge 538 * triggered 539 ******************************************************************************/ 540 void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg) 541 { 542 gicd_set_icfgr(driver_data->gicd_base, id, cfg); 543 } 544