1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <drivers/arm/gic.h> 10 #include <drivers/arm/gicv2.h> 11 #include <plat/arm/common/plat_arm.h> 12 #include <plat/common/platform.h> 13 14 #if USE_GIC_DRIVER != 2 15 #error "This file should only be used with USE_GIC_DRIVER=2" 16 #endif 17 18 /****************************************************************************** 19 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 20 * interrupts. 21 *****************************************************************************/ 22 static const interrupt_prop_t arm_interrupt_props[] = { 23 PLAT_ARM_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 24 PLAT_ARM_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 25 }; 26 27 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 28 29 static const gicv2_driver_data_t arm_gic_data = { 30 .gicd_base = PLAT_ARM_GICD_BASE, 31 .gicc_base = PLAT_ARM_GICC_BASE, 32 .interrupt_props = arm_interrupt_props, 33 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), 34 .target_masks = target_mask_array, 35 .target_masks_num = ARRAY_SIZE(target_mask_array), 36 }; 37 38 /****************************************************************************** 39 * ARM common helper to initialize the GICv2 only driver. 40 *****************************************************************************/ 41 void __init gic_init(unsigned int cpu_idx) 42 { 43 gicv2_driver_init(&arm_gic_data); 44 gicv2_distif_init(); 45 } 46 47 /****************************************************************************** 48 * ARM common helper to enable the GICv2 CPU interface 49 *****************************************************************************/ 50 void gic_cpuif_enable(unsigned int cpu_idx) 51 { 52 gicv2_cpuif_enable(); 53 } 54 55 /****************************************************************************** 56 * ARM common helper to disable the GICv2 CPU interface 57 *****************************************************************************/ 58 void gic_cpuif_disable(unsigned int cpu_idx) 59 { 60 gicv2_cpuif_disable(); 61 } 62 63 /****************************************************************************** 64 * ARM common helper to initialize the per cpu distributor interface in GICv2 65 *****************************************************************************/ 66 void gic_pcpu_init(unsigned int cpu_idx) 67 { 68 gicv2_pcpu_distif_init(); 69 gicv2_set_pe_target_mask(plat_my_core_pos()); 70 } 71 72 /****************************************************************************** 73 * Stubs for Redistributor power management. Although GICv2 doesn't have 74 * Redistributor interface, these are provided for the sake of uniform GIC API 75 *****************************************************************************/ 76 void gic_pcpu_off(unsigned int cpu_idx) 77 { 78 return; 79 } 80 81 /****************************************************************************** 82 * ARM common helper to save & restore the GICv3 on resume from system suspend. 83 * The normal world currently takes care of saving and restoring the GICv2 84 * registers due to legacy reasons. Hence we just initialize the Distributor 85 * on resume from system suspend. 86 *****************************************************************************/ 87 void gic_save(void) 88 { 89 return; 90 } 91 92 void gic_resume(void) 93 { 94 gicv2_distif_init(); 95 gicv2_pcpu_distif_init(); 96 } 97