1*5d893410SBoyan Karatotev /* 2*5d893410SBoyan Karatotev * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3*5d893410SBoyan Karatotev * 4*5d893410SBoyan Karatotev * SPDX-License-Identifier: BSD-3-Clause 5*5d893410SBoyan Karatotev */ 6*5d893410SBoyan Karatotev 7*5d893410SBoyan Karatotev #include <platform_def.h> 8*5d893410SBoyan Karatotev 9*5d893410SBoyan Karatotev #include <drivers/arm/gic.h> 10*5d893410SBoyan Karatotev #include <drivers/arm/gicv2.h> 11*5d893410SBoyan Karatotev #include <plat/arm/common/plat_arm.h> 12*5d893410SBoyan Karatotev #include <plat/common/platform.h> 13*5d893410SBoyan Karatotev 14*5d893410SBoyan Karatotev #if USE_GIC_DRIVER != 2 15*5d893410SBoyan Karatotev #error "This file should only be used with GENERIC_GIC_DRIVER=2" 16*5d893410SBoyan Karatotev #endif 17*5d893410SBoyan Karatotev 18*5d893410SBoyan Karatotev /****************************************************************************** 19*5d893410SBoyan Karatotev * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 20*5d893410SBoyan Karatotev * interrupts. 21*5d893410SBoyan Karatotev *****************************************************************************/ 22*5d893410SBoyan Karatotev static const interrupt_prop_t arm_interrupt_props[] = { 23*5d893410SBoyan Karatotev PLAT_ARM_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 24*5d893410SBoyan Karatotev PLAT_ARM_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 25*5d893410SBoyan Karatotev }; 26*5d893410SBoyan Karatotev 27*5d893410SBoyan Karatotev static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 28*5d893410SBoyan Karatotev 29*5d893410SBoyan Karatotev static const gicv2_driver_data_t arm_gic_data = { 30*5d893410SBoyan Karatotev .gicd_base = PLAT_ARM_GICD_BASE, 31*5d893410SBoyan Karatotev .gicc_base = PLAT_ARM_GICC_BASE, 32*5d893410SBoyan Karatotev .interrupt_props = arm_interrupt_props, 33*5d893410SBoyan Karatotev .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), 34*5d893410SBoyan Karatotev .target_masks = target_mask_array, 35*5d893410SBoyan Karatotev .target_masks_num = ARRAY_SIZE(target_mask_array), 36*5d893410SBoyan Karatotev }; 37*5d893410SBoyan Karatotev 38*5d893410SBoyan Karatotev /****************************************************************************** 39*5d893410SBoyan Karatotev * ARM common helper to initialize the GICv2 only driver. 40*5d893410SBoyan Karatotev *****************************************************************************/ 41*5d893410SBoyan Karatotev void __init gic_init(unsigned int cpu_idx) 42*5d893410SBoyan Karatotev { 43*5d893410SBoyan Karatotev gicv2_driver_init(&arm_gic_data); 44*5d893410SBoyan Karatotev gicv2_distif_init(); 45*5d893410SBoyan Karatotev } 46*5d893410SBoyan Karatotev 47*5d893410SBoyan Karatotev /****************************************************************************** 48*5d893410SBoyan Karatotev * ARM common helper to enable the GICv2 CPU interface 49*5d893410SBoyan Karatotev *****************************************************************************/ 50*5d893410SBoyan Karatotev void gic_cpuif_enable(unsigned int cpu_idx) 51*5d893410SBoyan Karatotev { 52*5d893410SBoyan Karatotev gicv2_cpuif_enable(); 53*5d893410SBoyan Karatotev } 54*5d893410SBoyan Karatotev 55*5d893410SBoyan Karatotev /****************************************************************************** 56*5d893410SBoyan Karatotev * ARM common helper to disable the GICv2 CPU interface 57*5d893410SBoyan Karatotev *****************************************************************************/ 58*5d893410SBoyan Karatotev void gic_cpuif_disable(unsigned int cpu_idx) 59*5d893410SBoyan Karatotev { 60*5d893410SBoyan Karatotev gicv2_cpuif_disable(); 61*5d893410SBoyan Karatotev } 62*5d893410SBoyan Karatotev 63*5d893410SBoyan Karatotev /****************************************************************************** 64*5d893410SBoyan Karatotev * ARM common helper to initialize the per cpu distributor interface in GICv2 65*5d893410SBoyan Karatotev *****************************************************************************/ 66*5d893410SBoyan Karatotev void gic_pcpu_init(unsigned int cpu_idx) 67*5d893410SBoyan Karatotev { 68*5d893410SBoyan Karatotev gicv2_pcpu_distif_init(); 69*5d893410SBoyan Karatotev gicv2_set_pe_target_mask(plat_my_core_pos()); 70*5d893410SBoyan Karatotev } 71*5d893410SBoyan Karatotev 72*5d893410SBoyan Karatotev /****************************************************************************** 73*5d893410SBoyan Karatotev * Stubs for Redistributor power management. Although GICv2 doesn't have 74*5d893410SBoyan Karatotev * Redistributor interface, these are provided for the sake of uniform GIC API 75*5d893410SBoyan Karatotev *****************************************************************************/ 76*5d893410SBoyan Karatotev void gic_pcpu_off(unsigned int cpu_idx) 77*5d893410SBoyan Karatotev { 78*5d893410SBoyan Karatotev return; 79*5d893410SBoyan Karatotev } 80*5d893410SBoyan Karatotev 81*5d893410SBoyan Karatotev /****************************************************************************** 82*5d893410SBoyan Karatotev * ARM common helper to save & restore the GICv3 on resume from system suspend. 83*5d893410SBoyan Karatotev * The normal world currently takes care of saving and restoring the GICv2 84*5d893410SBoyan Karatotev * registers due to legacy reasons. Hence we just initialize the Distributor 85*5d893410SBoyan Karatotev * on resume from system suspend. 86*5d893410SBoyan Karatotev *****************************************************************************/ 87*5d893410SBoyan Karatotev void gic_save(void) 88*5d893410SBoyan Karatotev { 89*5d893410SBoyan Karatotev return; 90*5d893410SBoyan Karatotev } 91*5d893410SBoyan Karatotev 92*5d893410SBoyan Karatotev void gic_resume(void) 93*5d893410SBoyan Karatotev { 94*5d893410SBoyan Karatotev gicv2_distif_init(); 95*5d893410SBoyan Karatotev gicv2_pcpu_distif_init(); 96*5d893410SBoyan Karatotev } 97