xref: /rk3399_ARM-atf/drivers/arm/gic/common/gic_common_private.h (revision e9ec3cec6519604b1c6fa7eb3834966e3bd10685)
1*e9ec3cecSSoby Mathew /*
2*e9ec3cecSSoby Mathew  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3*e9ec3cecSSoby Mathew  *
4*e9ec3cecSSoby Mathew  * Redistribution and use in source and binary forms, with or without
5*e9ec3cecSSoby Mathew  * modification, are permitted provided that the following conditions are met:
6*e9ec3cecSSoby Mathew  *
7*e9ec3cecSSoby Mathew  * Redistributions of source code must retain the above copyright notice, this
8*e9ec3cecSSoby Mathew  * list of conditions and the following disclaimer.
9*e9ec3cecSSoby Mathew  *
10*e9ec3cecSSoby Mathew  * Redistributions in binary form must reproduce the above copyright notice,
11*e9ec3cecSSoby Mathew  * this list of conditions and the following disclaimer in the documentation
12*e9ec3cecSSoby Mathew  * and/or other materials provided with the distribution.
13*e9ec3cecSSoby Mathew  *
14*e9ec3cecSSoby Mathew  * Neither the name of ARM nor the names of its contributors may be used
15*e9ec3cecSSoby Mathew  * to endorse or promote products derived from this software without specific
16*e9ec3cecSSoby Mathew  * prior written permission.
17*e9ec3cecSSoby Mathew  *
18*e9ec3cecSSoby Mathew  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19*e9ec3cecSSoby Mathew  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20*e9ec3cecSSoby Mathew  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21*e9ec3cecSSoby Mathew  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22*e9ec3cecSSoby Mathew  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23*e9ec3cecSSoby Mathew  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24*e9ec3cecSSoby Mathew  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25*e9ec3cecSSoby Mathew  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26*e9ec3cecSSoby Mathew  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27*e9ec3cecSSoby Mathew  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28*e9ec3cecSSoby Mathew  * POSSIBILITY OF SUCH DAMAGE.
29*e9ec3cecSSoby Mathew  */
30*e9ec3cecSSoby Mathew 
31*e9ec3cecSSoby Mathew #ifndef GIC_COMMON_PRIVATE_H_
32*e9ec3cecSSoby Mathew #define GIC_COMMON_PRIVATE_H_
33*e9ec3cecSSoby Mathew 
34*e9ec3cecSSoby Mathew #include <gic_common.h>
35*e9ec3cecSSoby Mathew #include <mmio.h>
36*e9ec3cecSSoby Mathew #include <stdint.h>
37*e9ec3cecSSoby Mathew 
38*e9ec3cecSSoby Mathew /*******************************************************************************
39*e9ec3cecSSoby Mathew  * GIC Distributor interface register accessors that are common to GICv3 & GICv2
40*e9ec3cecSSoby Mathew  ******************************************************************************/
41*e9ec3cecSSoby Mathew static inline unsigned int gicd_read_ctlr(uintptr_t base)
42*e9ec3cecSSoby Mathew {
43*e9ec3cecSSoby Mathew 	return mmio_read_32(base + GICD_CTLR);
44*e9ec3cecSSoby Mathew }
45*e9ec3cecSSoby Mathew 
46*e9ec3cecSSoby Mathew static inline unsigned int gicd_read_typer(uintptr_t base)
47*e9ec3cecSSoby Mathew {
48*e9ec3cecSSoby Mathew 	return mmio_read_32(base + GICD_TYPER);
49*e9ec3cecSSoby Mathew }
50*e9ec3cecSSoby Mathew 
51*e9ec3cecSSoby Mathew static inline unsigned int gicd_read_iidr(uintptr_t base)
52*e9ec3cecSSoby Mathew {
53*e9ec3cecSSoby Mathew 	return mmio_read_32(base + GICD_IIDR);
54*e9ec3cecSSoby Mathew }
55*e9ec3cecSSoby Mathew 
56*e9ec3cecSSoby Mathew static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
57*e9ec3cecSSoby Mathew {
58*e9ec3cecSSoby Mathew 	mmio_write_32(base + GICD_CTLR, val);
59*e9ec3cecSSoby Mathew }
60*e9ec3cecSSoby Mathew 
61*e9ec3cecSSoby Mathew /*******************************************************************************
62*e9ec3cecSSoby Mathew  * GIC Distributor function prototypes for accessing entire registers.
63*e9ec3cecSSoby Mathew  * Note: The raw register values correspond to multiple interrupt IDs and
64*e9ec3cecSSoby Mathew  * the number of interrupt IDs involved depends on the register accessed.
65*e9ec3cecSSoby Mathew  ******************************************************************************/
66*e9ec3cecSSoby Mathew unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id);
67*e9ec3cecSSoby Mathew unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id);
68*e9ec3cecSSoby Mathew unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id);
69*e9ec3cecSSoby Mathew unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id);
70*e9ec3cecSSoby Mathew unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id);
71*e9ec3cecSSoby Mathew unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id);
72*e9ec3cecSSoby Mathew unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id);
73*e9ec3cecSSoby Mathew unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id);
74*e9ec3cecSSoby Mathew unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id);
75*e9ec3cecSSoby Mathew unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id);
76*e9ec3cecSSoby Mathew void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val);
77*e9ec3cecSSoby Mathew void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val);
78*e9ec3cecSSoby Mathew void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val);
79*e9ec3cecSSoby Mathew void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val);
80*e9ec3cecSSoby Mathew void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val);
81*e9ec3cecSSoby Mathew void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val);
82*e9ec3cecSSoby Mathew void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val);
83*e9ec3cecSSoby Mathew void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
84*e9ec3cecSSoby Mathew void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val);
85*e9ec3cecSSoby Mathew void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val);
86*e9ec3cecSSoby Mathew 
87*e9ec3cecSSoby Mathew /*******************************************************************************
88*e9ec3cecSSoby Mathew  * GIC Distributor function prototypes for accessing the GIC registers
89*e9ec3cecSSoby Mathew  * corresponding to a single interrupt ID. These functions use bitwise
90*e9ec3cecSSoby Mathew  * operations or appropriate register accesses to modify or return
91*e9ec3cecSSoby Mathew  * the bit-field corresponding the single interrupt ID.
92*e9ec3cecSSoby Mathew  ******************************************************************************/
93*e9ec3cecSSoby Mathew unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id);
94*e9ec3cecSSoby Mathew void gicd_set_igroupr(uintptr_t base, unsigned int id);
95*e9ec3cecSSoby Mathew void gicd_clr_igroupr(uintptr_t base, unsigned int id);
96*e9ec3cecSSoby Mathew void gicd_set_isenabler(uintptr_t base, unsigned int id);
97*e9ec3cecSSoby Mathew void gicd_set_icenabler(uintptr_t base, unsigned int id);
98*e9ec3cecSSoby Mathew void gicd_set_ispendr(uintptr_t base, unsigned int id);
99*e9ec3cecSSoby Mathew void gicd_set_icpendr(uintptr_t base, unsigned int id);
100*e9ec3cecSSoby Mathew void gicd_set_isactiver(uintptr_t base, unsigned int id);
101*e9ec3cecSSoby Mathew void gicd_set_icactiver(uintptr_t base, unsigned int id);
102*e9ec3cecSSoby Mathew void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri);
103*e9ec3cecSSoby Mathew 
104*e9ec3cecSSoby Mathew #endif /* GIC_COMMON_PRIVATE_H_ */
105