1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #pragma message __FILE__ " is deprecated, use gicv2.mk instead" 8 9 #include <assert.h> 10 11 #include <drivers/arm/gic_common.h> 12 #include <lib/mmio.h> 13 14 #include "gic_common_private.h" 15 16 /******************************************************************************* 17 * GIC Distributor interface accessors for reading entire registers 18 ******************************************************************************/ 19 /* 20 * Accessor to read the GIC Distributor IGROUPR corresponding to the interrupt 21 * `id`, 32 interrupt ids at a time. 22 */ 23 unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) 24 { 25 unsigned int n = id >> IGROUPR_SHIFT; 26 27 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); 28 } 29 30 /* 31 * Accessor to read the GIC Distributor ISENABLER corresponding to the 32 * interrupt `id`, 32 interrupt ids at a time. 33 */ 34 unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) 35 { 36 unsigned int n = id >> ISENABLER_SHIFT; 37 38 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); 39 } 40 41 /* 42 * Accessor to read the GIC Distributor ICENABLER corresponding to the 43 * interrupt `id`, 32 interrupt IDs at a time. 44 */ 45 unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) 46 { 47 unsigned int n = id >> ICENABLER_SHIFT; 48 49 return mmio_read_32(base + GICD_ICENABLER + (n << 2)); 50 } 51 52 /* 53 * Accessor to read the GIC Distributor ISPENDR corresponding to the 54 * interrupt `id`, 32 interrupt IDs at a time. 55 */ 56 unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) 57 { 58 unsigned int n = id >> ISPENDR_SHIFT; 59 60 return mmio_read_32(base + GICD_ISPENDR + (n << 2)); 61 } 62 63 /* 64 * Accessor to read the GIC Distributor ICPENDR corresponding to the 65 * interrupt `id`, 32 interrupt IDs at a time. 66 */ 67 unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) 68 { 69 unsigned int n = id >> ICPENDR_SHIFT; 70 71 return mmio_read_32(base + GICD_ICPENDR + (n << 2)); 72 } 73 74 /* 75 * Accessor to read the GIC Distributor ISACTIVER corresponding to the 76 * interrupt `id`, 32 interrupt IDs at a time. 77 */ 78 unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id) 79 { 80 unsigned int n = id >> ISACTIVER_SHIFT; 81 82 return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); 83 } 84 85 /* 86 * Accessor to read the GIC Distributor ICACTIVER corresponding to the 87 * interrupt `id`, 32 interrupt IDs at a time. 88 */ 89 unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id) 90 { 91 unsigned int n = id >> ICACTIVER_SHIFT; 92 93 return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); 94 } 95 96 /* 97 * Accessor to read the GIC Distributor IPRIORITYR corresponding to the 98 * interrupt `id`, 4 interrupt IDs at a time. 99 */ 100 unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id) 101 { 102 unsigned int n = id >> IPRIORITYR_SHIFT; 103 104 return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); 105 } 106 107 /* 108 * Accessor to read the GIC Distributor ICGFR corresponding to the 109 * interrupt `id`, 16 interrupt IDs at a time. 110 */ 111 unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id) 112 { 113 unsigned int n = id >> ICFGR_SHIFT; 114 115 return mmio_read_32(base + GICD_ICFGR + (n << 2)); 116 } 117 118 /* 119 * Accessor to read the GIC Distributor NSACR corresponding to the 120 * interrupt `id`, 16 interrupt IDs at a time. 121 */ 122 unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id) 123 { 124 unsigned int n = id >> NSACR_SHIFT; 125 126 return mmio_read_32(base + GICD_NSACR + (n << 2)); 127 } 128 129 /******************************************************************************* 130 * GIC Distributor interface accessors for writing entire registers 131 ******************************************************************************/ 132 /* 133 * Accessor to write the GIC Distributor IGROUPR corresponding to the 134 * interrupt `id`, 32 interrupt IDs at a time. 135 */ 136 void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val) 137 { 138 unsigned int n = id >> IGROUPR_SHIFT; 139 140 mmio_write_32(base + GICD_IGROUPR + (n << 2), val); 141 } 142 143 /* 144 * Accessor to write the GIC Distributor ISENABLER corresponding to the 145 * interrupt `id`, 32 interrupt IDs at a time. 146 */ 147 void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val) 148 { 149 unsigned int n = id >> ISENABLER_SHIFT; 150 151 mmio_write_32(base + GICD_ISENABLER + (n << 2), val); 152 } 153 154 /* 155 * Accessor to write the GIC Distributor ICENABLER corresponding to the 156 * interrupt `id`, 32 interrupt IDs at a time. 157 */ 158 void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val) 159 { 160 unsigned int n = id >> ICENABLER_SHIFT; 161 162 mmio_write_32(base + GICD_ICENABLER + (n << 2), val); 163 } 164 165 /* 166 * Accessor to write the GIC Distributor ISPENDR corresponding to the 167 * interrupt `id`, 32 interrupt IDs at a time. 168 */ 169 void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val) 170 { 171 unsigned int n = id >> ISPENDR_SHIFT; 172 173 mmio_write_32(base + GICD_ISPENDR + (n << 2), val); 174 } 175 176 /* 177 * Accessor to write the GIC Distributor ICPENDR corresponding to the 178 * interrupt `id`, 32 interrupt IDs at a time. 179 */ 180 void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val) 181 { 182 unsigned int n = id >> ICPENDR_SHIFT; 183 184 mmio_write_32(base + GICD_ICPENDR + (n << 2), val); 185 } 186 187 /* 188 * Accessor to write the GIC Distributor ISACTIVER corresponding to the 189 * interrupt `id`, 32 interrupt IDs at a time. 190 */ 191 void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val) 192 { 193 unsigned int n = id >> ISACTIVER_SHIFT; 194 195 mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); 196 } 197 198 /* 199 * Accessor to write the GIC Distributor ICACTIVER corresponding to the 200 * interrupt `id`, 32 interrupt IDs at a time. 201 */ 202 void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val) 203 { 204 unsigned int n = id >> ICACTIVER_SHIFT; 205 206 mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); 207 } 208 209 /* 210 * Accessor to write the GIC Distributor IPRIORITYR corresponding to the 211 * interrupt `id`, 4 interrupt IDs at a time. 212 */ 213 void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) 214 { 215 unsigned int n = id >> IPRIORITYR_SHIFT; 216 217 mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); 218 } 219 220 /* 221 * Accessor to write the GIC Distributor ICFGR corresponding to the 222 * interrupt `id`, 16 interrupt IDs at a time. 223 */ 224 void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val) 225 { 226 unsigned int n = id >> ICFGR_SHIFT; 227 228 mmio_write_32(base + GICD_ICFGR + (n << 2), val); 229 } 230 231 /* 232 * Accessor to write the GIC Distributor NSACR corresponding to the 233 * interrupt `id`, 16 interrupt IDs at a time. 234 */ 235 void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val) 236 { 237 unsigned int n = id >> NSACR_SHIFT; 238 239 mmio_write_32(base + GICD_NSACR + (n << 2), val); 240 } 241 242 /******************************************************************************* 243 * GIC Distributor functions for accessing the GIC registers 244 * corresponding to a single interrupt ID. These functions use bitwise 245 * operations or appropriate register accesses to modify or return 246 * the bit-field corresponding the single interrupt ID. 247 ******************************************************************************/ 248 unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id) 249 { 250 unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U); 251 unsigned int reg_val = gicd_read_igroupr(base, id); 252 253 return (reg_val >> bit_num) & 0x1U; 254 } 255 256 void gicd_set_igroupr(uintptr_t base, unsigned int id) 257 { 258 unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U); 259 unsigned int reg_val = gicd_read_igroupr(base, id); 260 261 gicd_write_igroupr(base, id, reg_val | (1U << bit_num)); 262 } 263 264 void gicd_clr_igroupr(uintptr_t base, unsigned int id) 265 { 266 unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U); 267 unsigned int reg_val = gicd_read_igroupr(base, id); 268 269 gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num)); 270 } 271 272 void gicd_set_isenabler(uintptr_t base, unsigned int id) 273 { 274 unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U); 275 276 gicd_write_isenabler(base, id, (1U << bit_num)); 277 } 278 279 void gicd_set_icenabler(uintptr_t base, unsigned int id) 280 { 281 unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U); 282 283 gicd_write_icenabler(base, id, (1U << bit_num)); 284 } 285 286 void gicd_set_ispendr(uintptr_t base, unsigned int id) 287 { 288 unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U); 289 290 gicd_write_ispendr(base, id, (1U << bit_num)); 291 } 292 293 void gicd_set_icpendr(uintptr_t base, unsigned int id) 294 { 295 unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U); 296 297 gicd_write_icpendr(base, id, (1U << bit_num)); 298 } 299 300 unsigned int gicd_get_isactiver(uintptr_t base, unsigned int id) 301 { 302 unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U); 303 unsigned int reg_val = gicd_read_isactiver(base, id); 304 305 return (reg_val >> bit_num) & 0x1U; 306 } 307 308 void gicd_set_isactiver(uintptr_t base, unsigned int id) 309 { 310 unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U); 311 312 gicd_write_isactiver(base, id, (1U << bit_num)); 313 } 314 315 void gicd_set_icactiver(uintptr_t base, unsigned int id) 316 { 317 unsigned int bit_num = id & ((1U << ICACTIVER_SHIFT) - 1U); 318 319 gicd_write_icactiver(base, id, (1U << bit_num)); 320 } 321 322 void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) 323 { 324 uint8_t val = pri & GIC_PRI_MASK; 325 326 mmio_write_8(base + GICD_IPRIORITYR + id, val); 327 } 328 329 void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) 330 { 331 /* Interrupt configuration is a 2-bit field */ 332 unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U); 333 unsigned int bit_shift = bit_num << 1; 334 335 uint32_t reg_val = gicd_read_icfgr(base, id); 336 337 /* Clear the field, and insert required configuration */ 338 reg_val &= ~(GIC_CFG_MASK << bit_shift); 339 reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift); 340 341 gicd_write_icfgr(base, id, reg_val); 342 } 343