1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/arm/css/css_scp.h> 13 #include <drivers/arm/css/scmi.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/arm/css/common/css_pm.h> 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 /* 20 * This file implements the SCP helper functions using SCMI protocol. 21 */ 22 23 /* 24 * SCMI power state parameter bit field encoding for ARM CSS platforms. 25 * 26 * 31 20 19 16 15 12 11 8 7 4 3 0 27 * +-------------------------------------------------------------+ 28 * | SBZ | Max level | Level 3 | Level 2 | Level 1 | Level 0 | 29 * | | | state | state | state | state | 30 * +-------------------------------------------------------------+ 31 * 32 * `Max level` encodes the highest level that has a valid power state 33 * encoded in the power state. 34 */ 35 #define SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 16 36 #define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH 4 37 #define SCMI_PWR_STATE_MAX_PWR_LVL_MASK \ 38 ((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1) 39 #define SCMI_SET_PWR_STATE_MAX_PWR_LVL(_power_state, _max_level) \ 40 (_power_state) |= ((_max_level) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)\ 41 << SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 42 #define SCMI_GET_PWR_STATE_MAX_PWR_LVL(_power_state) \ 43 (((_power_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \ 44 & SCMI_PWR_STATE_MAX_PWR_LVL_MASK) 45 46 #define SCMI_PWR_STATE_LVL_WIDTH 4 47 #define SCMI_PWR_STATE_LVL_MASK \ 48 ((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1) 49 #define SCMI_SET_PWR_STATE_LVL(_power_state, _level, _level_state) \ 50 (_power_state) |= ((_level_state) & SCMI_PWR_STATE_LVL_MASK) \ 51 << (SCMI_PWR_STATE_LVL_WIDTH * (_level)) 52 #define SCMI_GET_PWR_STATE_LVL(_power_state, _level) \ 53 (((_power_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (_level))) & \ 54 SCMI_PWR_STATE_LVL_MASK) 55 56 /* 57 * The SCMI power state enumeration for a power domain level 58 */ 59 typedef enum { 60 scmi_power_state_off = 0, 61 scmi_power_state_on = 1, 62 scmi_power_state_sleep = 2, 63 } scmi_power_state_t; 64 65 /* 66 * The global handle for invoking the SCMI driver APIs after the driver 67 * has been initialized. 68 */ 69 static void *scmi_handle; 70 71 /* The SCMI channel global object */ 72 static scmi_channel_t channel; 73 74 ARM_SCMI_INSTANTIATE_LOCK; 75 76 /* 77 * Helper function to suspend a CPU power domain and its parent power domains 78 * if applicable. 79 */ 80 void css_scp_suspend(const struct psci_power_state *target_state) 81 { 82 int ret; 83 84 /* At least power domain level 0 should be specified to be suspended */ 85 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 86 ARM_LOCAL_STATE_OFF); 87 88 /* Check if power down at system power domain level is requested */ 89 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { 90 /* Issue SCMI command for SYSTEM_SUSPEND */ 91 ret = scmi_sys_pwr_state_set(scmi_handle, 92 SCMI_SYS_PWR_FORCEFUL_REQ, 93 SCMI_SYS_PWR_SUSPEND); 94 if (ret != SCMI_E_SUCCESS) { 95 ERROR("SCMI system power domain suspend return 0x%x unexpected\n", 96 ret); 97 panic(); 98 } 99 return; 100 } 101 #if !HW_ASSISTED_COHERENCY 102 int lvl; 103 uint32_t scmi_pwr_state = 0; 104 /* 105 * If we reach here, then assert that power down at system power domain 106 * level is running. 107 */ 108 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 109 110 /* For level 0, specify `scmi_power_state_sleep` as the power state */ 111 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, ARM_PWR_LVL0, 112 scmi_power_state_sleep); 113 114 for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 115 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) 116 break; 117 118 assert(target_state->pwr_domain_state[lvl] == 119 ARM_LOCAL_STATE_OFF); 120 /* 121 * Specify `scmi_power_state_off` as power state for higher 122 * levels. 123 */ 124 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, 125 scmi_power_state_off); 126 } 127 128 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); 129 130 ret = scmi_pwr_state_set(scmi_handle, 131 plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], 132 scmi_pwr_state); 133 134 if (ret != SCMI_E_SUCCESS) { 135 ERROR("SCMI set power state command return 0x%x unexpected\n", 136 ret); 137 panic(); 138 } 139 #endif 140 } 141 142 /* 143 * Helper function to turn off a CPU power domain and its parent power domains 144 * if applicable. 145 */ 146 void css_scp_off(const struct psci_power_state *target_state) 147 { 148 int lvl = 0, ret; 149 uint32_t scmi_pwr_state = 0; 150 151 /* At-least the CPU level should be specified to be OFF */ 152 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 153 ARM_LOCAL_STATE_OFF); 154 155 /* PSCI CPU OFF cannot be used to turn OFF system power domain */ 156 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 157 158 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 159 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) 160 break; 161 162 assert(target_state->pwr_domain_state[lvl] == 163 ARM_LOCAL_STATE_OFF); 164 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, 165 scmi_power_state_off); 166 } 167 168 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); 169 170 ret = scmi_pwr_state_set(scmi_handle, 171 plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], 172 scmi_pwr_state); 173 174 if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { 175 ERROR("SCMI set power state command return 0x%x unexpected\n", 176 ret); 177 panic(); 178 } 179 } 180 181 /* 182 * Helper function to turn ON a CPU power domain and its parent power domains 183 * if applicable. 184 */ 185 void css_scp_on(u_register_t mpidr) 186 { 187 int lvl = 0, ret, core_pos; 188 uint32_t scmi_pwr_state = 0; 189 190 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) 191 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, 192 scmi_power_state_on); 193 194 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); 195 196 core_pos = plat_core_pos_by_mpidr(mpidr); 197 assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT); 198 199 ret = scmi_pwr_state_set(scmi_handle, 200 plat_css_core_pos_to_scmi_dmn_id_map[core_pos], 201 scmi_pwr_state); 202 203 if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { 204 ERROR("SCMI set power state command return 0x%x unexpected\n", 205 ret); 206 panic(); 207 } 208 } 209 210 /* 211 * Helper function to get the power state of a power domain node as reported 212 * by the SCP. 213 */ 214 int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level) 215 { 216 int ret, cpu_idx; 217 uint32_t scmi_pwr_state = 0, lvl_state; 218 219 /* We don't support get power state at the system power domain level */ 220 if ((power_level > PLAT_MAX_PWR_LVL) || 221 (power_level == CSS_SYSTEM_PWR_DMN_LVL)) { 222 WARN("Invalid power level %u specified for SCMI get power state\n", 223 power_level); 224 return PSCI_E_INVALID_PARAMS; 225 } 226 227 cpu_idx = plat_core_pos_by_mpidr(mpidr); 228 assert(cpu_idx > -1); 229 230 ret = scmi_pwr_state_get(scmi_handle, 231 plat_css_core_pos_to_scmi_dmn_id_map[cpu_idx], 232 &scmi_pwr_state); 233 234 if (ret != SCMI_E_SUCCESS) { 235 WARN("SCMI get power state command return 0x%x unexpected\n", 236 ret); 237 return PSCI_E_INVALID_PARAMS; 238 } 239 240 /* 241 * Find the maximum power level described in the get power state 242 * command. If it is less than the requested power level, then assume 243 * the requested power level is ON. 244 */ 245 if (SCMI_GET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state) < power_level) 246 return HW_ON; 247 248 lvl_state = SCMI_GET_PWR_STATE_LVL(scmi_pwr_state, power_level); 249 if (lvl_state == scmi_power_state_on) 250 return HW_ON; 251 252 assert((lvl_state == scmi_power_state_off) || 253 (lvl_state == scmi_power_state_sleep)); 254 return HW_OFF; 255 } 256 257 void __dead2 css_scp_system_off(int state) 258 { 259 int ret; 260 261 /* 262 * Disable GIC CPU interface to prevent pending interrupt from waking 263 * up the AP from WFI. 264 */ 265 plat_arm_gic_cpuif_disable(); 266 267 /* 268 * Issue SCMI command. First issue a graceful 269 * request and if that fails force the request. 270 */ 271 ret = scmi_sys_pwr_state_set(scmi_handle, 272 SCMI_SYS_PWR_FORCEFUL_REQ, 273 state); 274 275 if (ret != SCMI_E_SUCCESS) { 276 ERROR("SCMI system power state set 0x%x returns unexpected 0x%x\n", 277 state, ret); 278 panic(); 279 } 280 wfi(); 281 ERROR("CSS set power state: operation not handled.\n"); 282 panic(); 283 } 284 285 /* 286 * Helper function to shutdown the system via SCMI. 287 */ 288 void __dead2 css_scp_sys_shutdown(void) 289 { 290 css_scp_system_off(SCMI_SYS_PWR_SHUTDOWN); 291 } 292 293 /* 294 * Helper function to reset the system via SCMI. 295 */ 296 void __dead2 css_scp_sys_reboot(void) 297 { 298 css_scp_system_off(SCMI_SYS_PWR_COLD_RESET); 299 } 300 301 static int scmi_ap_core_init(scmi_channel_t *ch) 302 { 303 #if PROGRAMMABLE_RESET_ADDRESS 304 uint32_t version; 305 int ret; 306 307 ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version); 308 if (ret != SCMI_E_SUCCESS) { 309 WARN("SCMI AP core protocol version message failed\n"); 310 return -1; 311 } 312 313 if (!is_scmi_version_compatible(SCMI_AP_CORE_PROTO_VER, version)) { 314 WARN("SCMI AP core protocol version 0x%x incompatible with driver version 0x%x\n", 315 version, SCMI_AP_CORE_PROTO_VER); 316 return -1; 317 } 318 INFO("SCMI AP core protocol version 0x%x detected\n", version); 319 #endif 320 return 0; 321 } 322 323 void __init plat_arm_pwrc_setup(void) 324 { 325 channel.info = plat_css_get_scmi_info(); 326 channel.lock = ARM_SCMI_LOCK_GET_INSTANCE; 327 scmi_handle = scmi_init(&channel); 328 if (scmi_handle == NULL) { 329 ERROR("SCMI Initialization failed\n"); 330 panic(); 331 } 332 if (scmi_ap_core_init(&channel) < 0) { 333 ERROR("SCMI AP core protocol initialization failed\n"); 334 panic(); 335 } 336 } 337 338 /****************************************************************************** 339 * This function overrides the default definition for ARM platforms. Initialize 340 * the SCMI driver, query capability via SCMI and modify the PSCI capability 341 * based on that. 342 *****************************************************************************/ 343 const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops) 344 { 345 uint32_t msg_attr; 346 int ret; 347 348 assert(scmi_handle); 349 350 /* Check that power domain POWER_STATE_SET message is supported */ 351 ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID, 352 SCMI_PWR_STATE_SET_MSG, &msg_attr); 353 if (ret != SCMI_E_SUCCESS) { 354 ERROR("Set power state command is not supported by SCMI\n"); 355 panic(); 356 } 357 358 /* 359 * Don't support PSCI NODE_HW_STATE call if SCMI doesn't support 360 * POWER_STATE_GET message. 361 */ 362 ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID, 363 SCMI_PWR_STATE_GET_MSG, &msg_attr); 364 if (ret != SCMI_E_SUCCESS) 365 ops->get_node_hw_state = NULL; 366 367 /* Check if the SCMI SYSTEM_POWER_STATE_SET message is supported */ 368 ret = scmi_proto_msg_attr(scmi_handle, SCMI_SYS_PWR_PROTO_ID, 369 SCMI_SYS_PWR_STATE_SET_MSG, &msg_attr); 370 if (ret != SCMI_E_SUCCESS) { 371 /* System power management operations are not supported */ 372 ops->system_off = NULL; 373 ops->system_reset = NULL; 374 ops->get_sys_suspend_power_state = NULL; 375 } else { 376 if (!(msg_attr & SCMI_SYS_PWR_SUSPEND_SUPPORTED)) { 377 /* 378 * System power management protocol is available, but 379 * it does not support SYSTEM SUSPEND. 380 */ 381 ops->get_sys_suspend_power_state = NULL; 382 } 383 if (!(msg_attr & SCMI_SYS_PWR_WARM_RESET_SUPPORTED)) { 384 /* 385 * WARM reset is not available. 386 */ 387 ops->system_reset2 = NULL; 388 } 389 } 390 391 return ops; 392 } 393 394 int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie) 395 { 396 if (is_vendor || (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET)) 397 return PSCI_E_INVALID_PARAMS; 398 399 css_scp_system_off(SCMI_SYS_PWR_WARM_RESET); 400 /* 401 * css_scp_system_off cannot return (it is a __dead function), 402 * but css_system_reset2 has to return some value, even in 403 * this case. 404 */ 405 return 0; 406 } 407 408 #if PROGRAMMABLE_RESET_ADDRESS 409 void plat_arm_program_trusted_mailbox(uintptr_t address) 410 { 411 int ret; 412 413 assert(scmi_handle); 414 ret = scmi_ap_core_set_reset_addr(scmi_handle, address, 415 SCMI_AP_CORE_LOCK_ATTR); 416 if (ret != SCMI_E_SUCCESS) { 417 ERROR("CSS: Failed to program reset address: %d\n", ret); 418 panic(); 419 } 420 } 421 #endif 422