1*f6d9c4caSSamuel Holland /* 2*f6d9c4caSSamuel Holland * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*f6d9c4caSSamuel Holland * 4*f6d9c4caSSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 5*f6d9c4caSSamuel Holland */ 6*f6d9c4caSSamuel Holland 7*f6d9c4caSSamuel Holland #include <drivers/allwinner/axp.h> 8*f6d9c4caSSamuel Holland 9*f6d9c4caSSamuel Holland const uint8_t axp_chip_id = AXP805_CHIP_ID; 10*f6d9c4caSSamuel Holland const char *const axp_compatible = "x-powers,axp805"; 11*f6d9c4caSSamuel Holland 12*f6d9c4caSSamuel Holland /* 13*f6d9c4caSSamuel Holland * The "dcdcd" split changes the step size by a factor of 5, not 2; 14*f6d9c4caSSamuel Holland * disallow values above the split to maintain accuracy. 15*f6d9c4caSSamuel Holland */ 16*f6d9c4caSSamuel Holland const struct axp_regulator axp_regulators[] = { 17*f6d9c4caSSamuel Holland {"dcdca", 600, 1520, 10, 50, 0x12, 0x10, 0}, 18*f6d9c4caSSamuel Holland {"dcdcb", 1000, 2550, 50, NA, 0x13, 0x10, 1}, 19*f6d9c4caSSamuel Holland {"dcdcc", 600, 1520, 10, 50, 0x14, 0x10, 2}, 20*f6d9c4caSSamuel Holland {"dcdcd", 600, 1500, 20, NA, 0x15, 0x10, 3}, 21*f6d9c4caSSamuel Holland {"dcdce", 1100, 3400, 100, NA, 0x16, 0x10, 4}, 22*f6d9c4caSSamuel Holland {"aldo1", 700, 3300, 100, NA, 0x17, 0x10, 5}, 23*f6d9c4caSSamuel Holland {"aldo2", 700, 3300, 100, NA, 0x18, 0x10, 6}, 24*f6d9c4caSSamuel Holland {"aldo3", 700, 3300, 100, NA, 0x19, 0x10, 7}, 25*f6d9c4caSSamuel Holland {"bldo1", 700, 1900, 100, NA, 0x20, 0x11, 0}, 26*f6d9c4caSSamuel Holland {"bldo2", 700, 1900, 100, NA, 0x21, 0x11, 1}, 27*f6d9c4caSSamuel Holland {"bldo3", 700, 1900, 100, NA, 0x22, 0x11, 2}, 28*f6d9c4caSSamuel Holland {"bldo4", 700, 1900, 100, NA, 0x23, 0x11, 3}, 29*f6d9c4caSSamuel Holland {"cldo1", 700, 3300, 100, NA, 0x24, 0x11, 4}, 30*f6d9c4caSSamuel Holland {"cldo2", 700, 4200, 100, 27, 0x25, 0x11, 5}, 31*f6d9c4caSSamuel Holland {"cldo3", 700, 3300, 100, NA, 0x26, 0x11, 6}, 32*f6d9c4caSSamuel Holland {} 33*f6d9c4caSSamuel Holland }; 34