1Generic Threat Model 2******************** 3 4************ 5Introduction 6************ 7 8This document provides a generic threat model for TF-A firmware. 9 10.. _Target of Evaluation: 11 12******************** 13Target of Evaluation 14******************** 15 16In this threat model, the target of evaluation is the Trusted 17Firmware for A-class Processors (TF-A). This includes the boot ROM (BL1), 18the trusted boot firmware (BL2) and the runtime EL3 firmware (BL31) as 19shown on Figure 1. Everything else on Figure 1 is outside of the scope of 20the evaluation. 21 22TF-A can be configured in various ways. In this threat model we consider 23only the most basic configuration. To that end we make the following 24assumptions: 25 26- All TF-A images are run from either ROM or on-chip trusted SRAM. This means 27 TF-A is not vulnerable to an attacker that can probe or tamper with off-chip 28 memory. 29 30- Trusted boot is enabled. This means an attacker can't boot arbitrary images 31 that are not approved by platform providers. 32 33- There is no Secure-EL2. We don't consider threats that may come with 34 Secure-EL2 software. 35 36- There are no Root and Realm worlds. These are introduced by :ref:`Realm 37 Management Extension (RME)`. 38 39 The :ref:`Threat Model for TF-A with Arm CCA support` covers these types of 40 configurations. 41 42- No experimental features are enabled. We do not consider threats that may come 43 from them. 44 45- The platform's hardware complies with the `PSR specification`_, defining the 46 bare-minimum security prerequisites for System-on-Chips (SoC). 47 48Data Flow Diagram 49================= 50 51Figure 1 shows a high-level data flow diagram for TF-A. The diagram 52shows a model of the different components of a TF-A-based system and 53their interactions with TF-A. A description of each diagram element 54is given on Table 1. On the diagram, the red broken lines indicate 55trust boundaries. Components outside of the broken lines 56are considered untrusted by TF-A. 57 58.. uml:: ../../resources/diagrams/plantuml/tfa_dfd.puml 59 :caption: Figure 1: TF-A Data Flow Diagram 60 61.. table:: Table 1: TF-A Data Flow Diagram Description 62 63 +-----------------+--------------------------------------------------------+ 64 | Diagram Element | Description | 65 +=================+========================================================+ 66 | DF1 | | At boot time, images are loaded from non-volatile | 67 | | memory and verified by TF-A boot firmware. These | 68 | | images include TF-A BL2 and BL31 images, as well as | 69 | | other secure and non-secure images. | 70 +-----------------+--------------------------------------------------------+ 71 | DF2 | | TF-A log system framework outputs debug or | 72 | | informative messages over a UART interface. | 73 | | | 74 | | | Also, characters can be read from a UART interface. | 75 +-----------------+--------------------------------------------------------+ 76 | DF3 | | Debug and trace IP on a platform can allow access | 77 | | to registers and memory of TF-A. | 78 +-----------------+--------------------------------------------------------+ 79 | DF4 | | Secure world software (e.g. trusted OS) interact | 80 | | with TF-A through SMC call interface and/or shared | 81 | | memory. | 82 +-----------------+--------------------------------------------------------+ 83 | DF5 | | Non-secure world software (e.g. rich OS) interact | 84 | | with TF-A through SMC call interface and/or shared | 85 | | memory. | 86 +-----------------+--------------------------------------------------------+ 87 | DF6 | | This path represents the interaction between TF-A and| 88 | | various hardware IPs such as TrustZone controller | 89 | | and GIC. At boot time TF-A configures/initializes the| 90 | | IPs and interacts with them at runtime through | 91 | | interrupts and registers. | 92 +-----------------+--------------------------------------------------------+ 93 94 95.. _threat_analysis: 96 97*************** 98Threat Analysis 99*************** 100 101In this section we identify and provide assessment of potential threats to TF-A 102firmware. The threats are identified for each diagram element on the 103data flow diagram above. 104 105For each threat, we identify the *asset* that is under threat, the 106*threat agent* and the *threat type*. Each threat is given a *risk rating* 107that represents the impact and likelihood of that threat. We also discuss 108potential mitigations. 109 110Assets 111====== 112 113We have identified the following assets for TF-A: 114 115.. table:: Table 2: TF-A Assets 116 117 +--------------------+---------------------------------------------------+ 118 | Asset | Description | 119 +====================+===================================================+ 120 | Sensitive Data | | These include sensitive data that an attacker | 121 | | must not be able to tamper with (e.g. the Root | 122 | | of Trust Public Key) or see (e.g. secure logs, | 123 | | debugging information such as crash reports). | 124 +--------------------+---------------------------------------------------+ 125 | Code Execution | | This represents the requirement that the | 126 | | platform should run only TF-A code approved by | 127 | | the platform provider. | 128 +--------------------+---------------------------------------------------+ 129 | Availability | | This represents the requirement that TF-A | 130 | | services should always be available for use. | 131 +--------------------+---------------------------------------------------+ 132 133Threat Agents 134============= 135 136To understand the attack surface, it is important to identify potential 137attackers, i.e. attack entry points. The following threat agents are 138in scope of this threat model. 139 140.. table:: Table 3: Threat Agents 141 142 +-------------------+-------------------------------------------------------+ 143 | Threat Agent | Description | 144 +===================+=======================================================+ 145 | NSCode | | Malicious or faulty code running in the Non-secure | 146 | | world, including NS-EL0 NS-EL1 and NS-EL2 levels | 147 +-------------------+-------------------------------------------------------+ 148 | SecCode | | Malicious or faulty code running in the secure | 149 | | world, including S-EL0 and S-EL1 levels | 150 +-------------------+-------------------------------------------------------+ 151 | AppDebug | | Physical attacker using debug signals to access | 152 | | TF-A resources | 153 +-------------------+-------------------------------------------------------+ 154 | PhysicalAccess | | Physical attacker having access to external device | 155 | | communication bus and to external flash | 156 | | communication bus using common hardware | 157 +-------------------+-------------------------------------------------------+ 158 159.. note:: 160 161 In this threat model an advanced physical attacker that has the capability 162 to tamper with a hardware (e.g. "rewiring" a chip using a focused 163 ion beam (FIB) workstation or decapsulate the chip using chemicals) is 164 considered out-of-scope. 165 166 Certain non-invasive physical attacks that do not need modifications to the 167 chip, notably those like Power Analysis Attacks, are out-of-scope. Power 168 analysis side-channel attacks represent a category of security threats that 169 capitalize on information leakage through a device's power consumption during 170 its normal operation. These attacks leverage the correlation between a 171 device's power usage and its internal data processing activities. This 172 correlation provides attackers with the means to extract sensitive 173 information, including cryptographic keys. 174 175Threat Types 176============ 177 178In this threat model we categorize threats using the `STRIDE threat 179analysis technique`_. In this technique a threat is categorized as one 180or more of these types: ``Spoofing``, ``Tampering``, ``Repudiation``, 181``Information disclosure``, ``Denial of service`` or 182``Elevation of privilege``. 183 184Threat Risk Ratings 185=================== 186 187For each threat identified, a risk rating that ranges 188from *informational* to *critical* is given based on the likelihood of the 189threat occurring if a mitigation is not in place, and the impact of the 190threat (i.e. how severe the consequences could be). Table 4 explains each 191rating in terms of score, impact and likelihood. 192 193.. table:: Table 4: Rating and score as applied to impact and likelihood 194 195 +-----------------------+-------------------------+---------------------------+ 196 | **Rating (Score)** | **Impact** | **Likelihood** | 197 +=======================+=========================+===========================+ 198 | Critical (5) | | Extreme impact to | | Threat is almost | 199 | | entire organization | certain to be exploited.| 200 | | if exploited. | | 201 | | | | Knowledge of the threat | 202 | | | and how to exploit it | 203 | | | are in the public | 204 | | | domain. | 205 +-----------------------+-------------------------+---------------------------+ 206 | High (4) | | Major impact to entire| | Threat is relatively | 207 | | organization or single| easy to detect and | 208 | | line of business if | exploit by an attacker | 209 | | exploited | with little skill. | 210 +-----------------------+-------------------------+---------------------------+ 211 | Medium (3) | | Noticeable impact to | | A knowledgeable insider | 212 | | line of business if | or expert attacker could| 213 | | exploited. | exploit the threat | 214 | | | without much difficulty.| 215 +-----------------------+-------------------------+---------------------------+ 216 | Low (2) | | Minor damage if | | Exploiting the threat | 217 | | exploited or could | would require | 218 | | be used in conjunction| considerable expertise | 219 | | with other | and resources | 220 | | vulnerabilities to | | 221 | | perform a more serious| | 222 | | attack | | 223 +-----------------------+-------------------------+---------------------------+ 224 | Informational (1) | | Poor programming | | Threat is not likely | 225 | | practice or poor | to be exploited on its | 226 | | design decision that | own, but may be used to | 227 | | may not represent an | gain information for | 228 | | immediate risk on its | launching another | 229 | | own, but may have | attack | 230 | | security implications | | 231 | | if multiplied and/or | | 232 | | combined with other | | 233 | | threats. | | 234 +-----------------------+-------------------------+---------------------------+ 235 236Aggregate risk scores are assigned to identified threats; 237specifically, the impact score multiplied by the likelihood score. 238For example, a threat with high likelihood and low impact would have an 239aggregate risk score of eight (8); that is, four (4) for high likelihood 240multiplied by two (2) for low impact. The aggregate risk score determines 241the finding's overall risk level, as shown in the following table. 242 243.. table:: Table 5: Overall risk levels and corresponding aggregate scores 244 245 +---------------------+-----------------------------------+ 246 | Overall Risk Level | Aggregate Risk Score | 247 | | (Impact multiplied by Likelihood) | 248 +=====================+===================================+ 249 | Critical | 20–25 | 250 +---------------------+-----------------------------------+ 251 | High | 12–19 | 252 +---------------------+-----------------------------------+ 253 | Medium | 6–11 | 254 +---------------------+-----------------------------------+ 255 | Low | 2–5 | 256 +---------------------+-----------------------------------+ 257 | Informational | 1 | 258 +---------------------+-----------------------------------+ 259 260The likelihood and impact of a threat depends on the 261target environment in which TF-A is running. For example, attacks 262that require physical access are unlikely in server environments while 263they are more common in Internet of Things(IoT) environments. 264In this threat model we consider three target environments: 265``Internet of Things(IoT)``, ``Mobile`` and ``Server``. 266 267Threat Assessment 268================= 269 270The following threats were identified by applying STRIDE analysis on 271each diagram element of the data flow diagram. 272 273For each threat, we strive to indicate whether the mitigations are currently 274implemented or not. However, the answer to this question is not always straight 275forward. Some mitigations are partially implemented in the generic code but also 276rely on the platform code to implement some bits of it. This threat model aims 277to be platform-independent and it is important to keep in mind that such threats 278only get mitigated if the platform code properly fulfills its responsibilities. 279 280Also, some mitigations require enabling specific features, which must be 281explicitly turned on via a build flag. 282 283When such conditions must be met, these are highlighted in the ``Mitigations 284implemented?`` box. 285 286As our :ref:`Target of Evaluation` is made of several, distinct firmware images, 287some threats are confined in specific images, while others apply to each of 288them. To help developers implement mitigations in the right place, threats below 289are categorized based on the firmware image that should mitigate them. 290 291.. _General Threats: 292 293General Threats for All Firmware Images 294--------------------------------------- 295 296+------------------------+---------------------------------------------------+ 297| ID | 05 | 298+========================+===================================================+ 299| Threat | | **Information leak via UART logs** | 300| | | 301| | | During the development stages of software it is | 302| | common to print all sorts of information on the | 303| | console, including sensitive or confidential | 304| | information such as crash reports with detailed | 305| | information of the CPU state, current registers | 306| | values, privilege level or stack dumps. | 307| | | 308| | | This information is useful when debugging | 309| | problems before releasing the production | 310| | version but it could be used by an attacker | 311| | to develop a working exploit if left enabled in | 312| | the production version. | 313| | | 314| | | This happens when directly logging sensitive | 315| | information and more subtly when logging | 316| | side-channel information that can be used by an | 317| | attacker to learn about sensitive information. | 318+------------------------+---------------------------------------------------+ 319| Diagram Elements | DF2 | 320+------------------------+---------------------------------------------------+ 321| Affected TF-A | BL1, BL2, BL31 | 322| Components | | 323+------------------------+---------------------------------------------------+ 324| Assets | Sensitive Data | 325+------------------------+---------------------------------------------------+ 326| Threat Agent | AppDebug | 327+------------------------+---------------------------------------------------+ 328| Threat Type | Information Disclosure | 329+------------------------+------------------+----------------+---------------+ 330| Application | Server | IoT | Mobile | 331+------------------------+------------------+----------------+---------------+ 332| Impact | N/A | Low (2) | Low (2) | 333+------------------------+------------------+----------------+---------------+ 334| Likelihood | N/A | High (4) | High (4) | 335+------------------------+------------------+----------------+---------------+ 336| Total Risk Rating | N/A | Medium (8) | Medium (8) | 337+------------------------+------------------+----------------+---------------+ 338| Mitigations | | Remove sensitive information logging in | 339| | production releases. | 340| | | 341| | | Do not conditionally log information depending | 342| | on potentially sensitive data. | 343| | | 344| | | Do not log high precision timing information. | 345+------------------------+---------------------------------------------------+ 346| Mitigations | | Yes / Platform Specific. | 347| implemented? | Requires the right build options to be used. | 348| | | 349| | | Crash reporting is only enabled for debug | 350| | builds by default, see ``CRASH_REPORTING`` | 351| | build option. | 352| | | 353| | | The log level can be tuned at build time, from | 354| | very verbose to no output at all. See | 355| | ``LOG_LEVEL`` build option. By default, release | 356| | builds are a lot less verbose than debug ones | 357| | but still produce some output. | 358| | | 359| | | Messages produced by the platform code should | 360| | use the appropriate level of verbosity so as | 361| | not to leak sensitive information in production | 362| | builds. | 363+------------------------+---------------------------------------------------+ 364 365+------------------------+----------------------------------------------------+ 366| ID | 06 | 367+========================+====================================================+ 368| Threat | | **An attacker can read sensitive data and | 369| | execute arbitrary code through the external | 370| | debug and trace interface** | 371| | | 372| | | Arm processors include hardware-assisted debug | 373| | and trace features that can be controlled without| 374| | the need for software operating on the platform. | 375| | If left enabled without authentication, this | 376| | feature can be used by an attacker to inspect and| 377| | modify TF-A registers and memory allowing the | 378| | attacker to read sensitive data and execute | 379| | arbitrary code. | 380+------------------------+----------------------------------------------------+ 381| Diagram Elements | DF3 | 382+------------------------+----------------------------------------------------+ 383| Affected TF-A | BL1, BL2, BL31 | 384| Components | | 385+------------------------+----------------------------------------------------+ 386| Assets | Code Execution, Sensitive Data | 387+------------------------+----------------------------------------------------+ 388| Threat Agent | AppDebug | 389+------------------------+----------------------------------------------------+ 390| Threat Type | Tampering, Information Disclosure, | 391| | Elevation of privilege | 392+------------------------+------------------+---------------+-----------------+ 393| Application | Server | IoT | Mobile | 394+------------------------+------------------+---------------+-----------------+ 395| Impact | N/A | High (4) | High (4) | 396+------------------------+------------------+---------------+-----------------+ 397| Likelihood | N/A | Critical (5) | Critical (5) | 398+------------------------+------------------+---------------+-----------------+ 399| Total Risk Rating | N/A | Critical (20) | Critical (20) | 400+------------------------+------------------+---------------+-----------------+ 401| Mitigations | Disable the debug and trace capability for | 402| | production releases or enable proper debug | 403| | authentication as recommended by [`DEN0034`_]. | 404+------------------------+----------------------------------------------------+ 405| Mitigations | | Platform specific. | 406| implemented? | | 407| | | Configuration of debug and trace capabilities is | 408| | entirely platform specific. | 409+------------------------+----------------------------------------------------+ 410 411+------------------------+------------------------------------------------------+ 412| ID | 08 | 413+========================+======================================================+ 414| Threat | | **Memory corruption due to memory overflows and | 415| | lack of boundary checking when accessing resources | 416| | could allow an attacker to execute arbitrary code, | 417| | modify some state variable to change the normal | 418| | flow of the program, or leak sensitive | 419| | information** | 420| | | 421| | | Like in other software, TF-A has multiple points | 422| | where memory corruption security errors can arise. | 423| | | 424| | | Some of the errors include integer overflow, | 425| | buffer overflow, incorrect array boundary checks, | 426| | and incorrect error management. | 427| | Improper use of asserts instead of proper input | 428| | validations might also result in these kinds of | 429| | errors in release builds. | 430+------------------------+------------------------------------------------------+ 431| Diagram Elements | DF4, DF5 | 432+------------------------+------------------------------------------------------+ 433| Affected TF-A | BL1, BL2, BL31 | 434| Components | | 435+------------------------+------------------------------------------------------+ 436| Assets | Code Execution, Sensitive Data | 437+------------------------+------------------------------------------------------+ 438| Threat Agent | NSCode, SecCode | 439+------------------------+------------------------------------------------------+ 440| Threat Type | Tampering, Information Disclosure, | 441| | Elevation of Privilege | 442+------------------------+-------------------+-----------------+----------------+ 443| Application | Server | IoT | Mobile | 444+------------------------+-------------------+-----------------+----------------+ 445| Impact | Critical (5) | Critical (5) | Critical (5) | 446+------------------------+-------------------+-----------------+----------------+ 447| Likelihood | Medium (3 | Medium (3) | Medium (3) | 448+------------------------+-------------------+-----------------+----------------+ 449| Total Risk Rating | High (15) | High (15) | High (15) | 450+------------------------+-------------------+-----------------+----------------+ 451| Mitigations | | 1) Use proper input validation. | 452| | | 453| | | 2) Code reviews, testing. | 454+------------------------+------------------------------------------------------+ 455| Mitigations | | 1) Yes. | 456| implemented? | Data received from normal world, such as addresses | 457| | and sizes identifying memory regions, are | 458| | sanitized before being used. These security checks | 459| | make sure that the normal world software does not | 460| | access memory beyond its limit. | 461| | | 462| | | By default *asserts* are only used to check for | 463| | programming errors in debug builds. Other types of | 464| | errors are handled through condition checks that | 465| | remain enabled in release builds. See | 466| | `TF-A error handling policy`_. TF-A provides an | 467| | option to use *asserts* in release builds, however | 468| | we recommend using proper runtime checks instead | 469| | of relying on asserts in release builds. | 470| | | 471| | | 2) Yes. | 472| | TF-A uses a combination of manual code reviews | 473| | and automated program analysis and testing to | 474| | detect and fix memory corruption bugs. All TF-A | 475| | code including platform code go through manual | 476| | code reviews. Additionally, static code analysis | 477| | is performed using Coverity Scan on all TF-A code. | 478| | The code is also tested with | 479| | `Trusted Firmware-A Tests`_ on Juno and FVP | 480| | platforms. | 481+------------------------+------------------------------------------------------+ 482 483 484+------------------------+----------------------------------------------------+ 485| ID | 11 | 486+========================+====================================================+ 487| Threat | | **Misconfiguration of the Memory Management Unit | 488| | (MMU) may allow a normal world software to | 489| | access sensitive data, execute arbitrary | 490| | code or access otherwise restricted HW | 491| | interface** | 492| | | 493| | | A misconfiguration of the MMU could | 494| | lead to an open door for software running in the | 495| | normal world to access sensitive data or even | 496| | execute code if the proper security mechanisms | 497| | are not in place. | 498+------------------------+----------------------------------------------------+ 499| Diagram Elements | DF5, DF6 | 500+------------------------+----------------------------------------------------+ 501| Affected TF-A | BL1, BL2, BL31 | 502| Components | | 503+------------------------+----------------------------------------------------+ 504| Assets | Sensitive Data, Code execution | 505+------------------------+----------------------------------------------------+ 506| Threat Agent | NSCode | 507+------------------------+----------------------------------------------------+ 508| Threat Type | Information Disclosure, Elevation of Privilege | 509+------------------------+-----------------+-----------------+----------------+ 510| Application | Server | IoT | Mobile | 511+------------------------+-----------------+-----------------+----------------+ 512| Impact | Critical (5) | Critical (5) | Critical (5) | 513+------------------------+-----------------+-----------------+----------------+ 514| Likelihood | High (4) | High (4) | High (4) | 515+------------------------+-----------------+-----------------+----------------+ 516| Total Risk Rating | Critical (20) | Critical (20) | Critical (20) | 517+------------------------+-----------------+-----------------+----------------+ 518| Mitigations | When configuring access permissions, the | 519| | principle of least privilege ought to be | 520| | enforced. This means we should not grant more | 521| | privileges than strictly needed, e.g. code | 522| | should be read-only executable, read-only data | 523| | should be read-only execute-never, and so on. | 524+------------------------+----------------------------------------------------+ 525| Mitigations | | Platform specific. | 526| implemented? | | 527| | | MMU configuration is platform specific, | 528| | therefore platforms need to make sure that the | 529| | correct attributes are assigned to memory | 530| | regions. | 531| | | 532| | | TF-A provides a library which abstracts the | 533| | low-level details of MMU configuration. It | 534| | provides well-defined and tested APIs. | 535| | Platforms are encouraged to use it to limit the | 536| | risk of misconfiguration. | 537+------------------------+----------------------------------------------------+ 538 539 540+------------------------+-----------------------------------------------------+ 541| ID | 13 | 542+========================+=====================================================+ 543| Threat | | **Leaving sensitive information in the memory, | 544| | can allow an attacker to retrieve them.** | 545| | | 546| | | Accidentally leaving not-needed sensitive data in | 547| | internal buffers can leak them if an attacker | 548| | gains access to memory due to a vulnerability. | 549+------------------------+-----------------------------------------------------+ 550| Diagram Elements | DF4, DF5 | 551+------------------------+-----------------------------------------------------+ 552| Affected TF-A | BL1, BL2, BL31 | 553| Components | | 554+------------------------+-----------------------------------------------------+ 555| Assets | Sensitive Data | 556+------------------------+-----------------------------------------------------+ 557| Threat Agent | NSCode, SecCode | 558+------------------------+-----------------------------------------------------+ 559| Threat Type | Information Disclosure | 560+------------------------+-------------------+----------------+----------------+ 561| Application | Server | IoT | Mobile | 562+------------------------+-------------------+----------------+----------------+ 563| Impact | Critical (5) | Critical (5) | Critical (5) | 564+------------------------+-------------------+----------------+----------------+ 565| Likelihood | Medium (3) | Medium (3) | Medium (3) | 566+------------------------+-------------------+----------------+----------------+ 567| Total Risk Rating | High (15) | High (15) | High (15) | 568+------------------------+-------------------+----------------+----------------+ 569| Mitigations | Clear the sensitive data from internal buffers as | 570| | soon as they are not needed anymore. | 571+------------------------+-----------------------------------------------------+ 572| Mitigations | | Yes / Platform specific | 573| implemented? | | 574+------------------------+-----------------------------------------------------+ 575 576 577+------------------------+-----------------------------------------------------+ 578| ID | 15 | 579+========================+=====================================================+ 580| Threat | | **Improper handling of input data received over | 581| | a UART interface may allow an attacker to tamper | 582| | with TF-A execution environment.** | 583| | | 584| | | The consequences of the attack depend on the | 585| | the exact usage of input data received over UART. | 586| | Examples are injection of arbitrary data, | 587| | sensitive data tampering, influencing the | 588| | execution path, denial of service (if using | 589| | blocking I/O). This list may not be exhaustive. | 590+------------------------+-----------------------------------------------------+ 591| Diagram Elements | DF2, DF4, DF5 | 592+------------------------+-----------------------------------------------------+ 593| Affected TF-A | BL1, BL2, BL31 | 594| Components | | 595+------------------------+-----------------------------------------------------+ 596| Assets | Sensitive Data, Code Execution, Availability | 597+------------------------+-----------------------------------------------------+ 598| Threat Agent | NSCode, SecCode | 599+------------------------+-----------------------------------------------------+ 600| Threat Type | Tampering, Information Disclosure, Denial of | 601| | service, Elevation of privilege. | 602+------------------------+-------------------+----------------+----------------+ 603| Application | Server | IoT | Mobile | 604+------------------------+-------------------+----------------+----------------+ 605| Impact | Critical (5) | Critical (5) | Critical (5) | 606+------------------------+-------------------+----------------+----------------+ 607| Likelihood | Critical (5) | Critical (5) | Critical (5) | 608+------------------------+-------------------+----------------+----------------+ 609| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | 610+------------------------+-------------------+----------------+----------------+ 611| Mitigations | | By default, the code to read input data from UART | 612| | interfaces is disabled (see `ENABLE_CONSOLE_GETC` | 613| | build option). It should only be enabled on a | 614| | need basis. | 615| | | 616| | | Data received over UART interfaces should be | 617| | treated as untrusted data. As such, it should be | 618| | properly sanitized and handled with caution. | 619+------------------------+-----------------------------------------------------+ 620| Mitigations | | Platform specific. | 621| implemented? | | 622| | | Generic code does not read any input data from | 623| | UART interface(s). | 624+------------------------+-----------------------------------------------------+ 625 626+------------------------+-----------------------------------------------------+ 627| ID | 16 | 628+========================+=====================================================+ 629| Threat | | **An attacker could analyse the timing behaviour | 630| | of implemented methods in the system to infer | 631| | sensitive information.** | 632| | | 633| | | A timing side-channel attack is a type of attack | 634| | that exploits variations in the time it takes a | 635| | system to perform different operations. This | 636| | form of attack focuses on analyzing the time- | 637| | related information leakage that occurs during | 638| | the execution of cryptographic algorithms or | 639| | other security-sensitive processes. By observing | 640| | these timing differences, an attacker can gain | 641| | insights into the internal workings of a system | 642| | and potentially extract sensitive information. | 643| | Sensitive information that, when revealed even | 644| | partially, could heighten the susceptibility to | 645| | traditional attacks like brute-force attacks. | 646+------------------------+-----------------------------------------------------+ 647| Diagram Elements | DF2 | 648+------------------------+-----------------------------------------------------+ 649| Affected TF-A | BL1, BL2, BL31 | 650| Components | | 651+------------------------+-----------------------------------------------------+ 652| Assets | Sensitive Data | 653+------------------------+-----------------------------------------------------+ 654| Threat Agent | AppDebug | 655+------------------------+-----------------------------------------------------+ 656| Threat Type | Information Disclosure | 657+------------------------+------------------+----------------+-----------------+ 658| Application | Server | IoT | Mobile | 659+------------------------+------------------+----------------+-----------------+ 660| Impact | Critical (5) | Critical (5) | Critical (5) | 661+------------------------+------------------+----------------+-----------------+ 662| Likelihood | Critical (5) | Critical (5) | Critical (5) | 663+------------------------+------------------+----------------+-----------------+ 664| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | 665+------------------------+------------------+----------------+-----------------+ 666| Mitigations | | Ensure that the execution time of critical | 667| | operations is constant and independent of | 668| | secret data. This prevents attackers from | 669| | exploiting timing differences to infer | 670| | information about sensitive data. | 671| | | 672| | | Introduce random delays/timing jitter or dummy | 673| | operations to make the timing behavior of program| 674| | execution less predictable. This can disrupt the | 675| | correlation between the execution time and | 676| | sensitive data. | 677| | | 678+------------------------+-----------------------------------------------------+ 679| Mitigations | | Not implemented | 680| implemented? | | 681+------------------------+-----------------------------------------------------+ 682 683.. _Boot Firmware Threats: 684 685Threats to be Mitigated by the Boot Firmware 686-------------------------------------------- 687 688The boot firmware here refers to the boot ROM (BL1) and the trusted boot 689firmware (BL2). Typically it does not stay resident in memory and it is 690dismissed once execution has reached the runtime EL3 firmware (BL31). Thus, past 691that point in time, the threats below can no longer be exploited. 692 693Note, however, that this is not necessarily true on all platforms. Platform 694vendors should review these threats to make sure they cannot be exploited 695nonetheless once execution has reached the runtime EL3 firmware. 696 697+------------------------+----------------------------------------------------+ 698| ID | 01 | 699+========================+====================================================+ 700| Threat | | **An attacker can mangle firmware images to | 701| | execute arbitrary code** | 702| | | 703| | | Some TF-A images are loaded from external | 704| | storage. It is possible for an attacker to access| 705| | the external flash memory and change its contents| 706| | physically, through the Rich OS, or using the | 707| | updating mechanism to modify the non-volatile | 708| | images to execute arbitrary code. | 709+------------------------+----------------------------------------------------+ 710| Diagram Elements | DF1, DF4, DF5 | 711+------------------------+----------------------------------------------------+ 712| Affected TF-A | BL2, BL31 | 713| Components | | 714+------------------------+----------------------------------------------------+ 715| Assets | Code Execution | 716+------------------------+----------------------------------------------------+ 717| Threat Agent | PhysicalAccess, NSCode, SecCode | 718+------------------------+----------------------------------------------------+ 719| Threat Type | Tampering, Elevation of Privilege | 720+------------------------+------------------+-----------------+---------------+ 721| Application | Server | IoT | Mobile | 722+------------------------+------------------+-----------------+---------------+ 723| Impact | Critical (5) | Critical (5) | Critical (5) | 724+------------------------+------------------+-----------------+---------------+ 725| Likelihood | Critical (5) | Critical (5) | Critical (5) | 726+------------------------+------------------+-----------------+---------------+ 727| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | 728+------------------------+------------------+-----------------+---------------+ 729| Mitigations | | 1) Implement the `Trusted Board Boot (TBB)`_ | 730| | feature which prevents malicious firmware from | 731| | running on the platform by authenticating all | 732| | firmware images. | 733| | | 734| | | 2) Perform extra checks on unauthenticated data, | 735| | such as FIP metadata, prior to use. | 736+------------------------+----------------------------------------------------+ 737| Mitigations | | 1) Yes, provided that the ``TRUSTED_BOARD_BOOT`` | 738| implemented? | build option is set to 1. | 739| | | 740| | | 2) Yes. | 741+------------------------+----------------------------------------------------+ 742 743+------------------------+----------------------------------------------------+ 744| ID | 02 | 745+========================+====================================================+ 746| Threat | | **An attacker may attempt to boot outdated, | 747| | potentially vulnerable firmware image** | 748| | | 749| | | When updating firmware, an attacker may attempt | 750| | to rollback to an older version that has unfixed | 751| | vulnerabilities. | 752+------------------------+----------------------------------------------------+ 753| Diagram Elements | DF1, DF4, DF5 | 754+------------------------+----------------------------------------------------+ 755| Affected TF-A | BL2, BL31 | 756| Components | | 757+------------------------+----------------------------------------------------+ 758| Assets | Code Execution | 759+------------------------+----------------------------------------------------+ 760| Threat Agent | PhysicalAccess, NSCode, SecCode | 761+------------------------+----------------------------------------------------+ 762| Threat Type | Tampering | 763+------------------------+------------------+-----------------+---------------+ 764| Application | Server | IoT | Mobile | 765+------------------------+------------------+-----------------+---------------+ 766| Impact | Critical (5) | Critical (5) | Critical (5) | 767+------------------------+------------------+-----------------+---------------+ 768| Likelihood | Critical (5) | Critical (5) | Critical (5) | 769+------------------------+------------------+-----------------+---------------+ 770| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | 771+------------------------+------------------+-----------------+---------------+ 772| Mitigations | Implement anti-rollback protection using | 773| | non-volatile counters (NV counters) as required | 774| | by `TBBR-Client specification`_. | 775+------------------------+----------------------------------------------------+ 776| Mitigations | | Yes / Platform specific. | 777| implemented? | | 778| | | After a firmware image is validated, the image | 779| | revision number taken from a certificate | 780| | extension field is compared with the | 781| | corresponding NV counter stored in hardware to | 782| | make sure the new counter value is larger than | 783| | the current counter value. | 784| | | 785| | | **Platforms must implement this protection using | 786| | platform specific hardware NV counters.** | 787+------------------------+----------------------------------------------------+ 788 789 790+------------------------+-------------------------------------------------------+ 791| ID | 03 | 792+========================+=======================================================+ 793| Threat | | **An attacker can use Time-of-Check-Time-of-Use | 794| | (TOCTOU) attack to bypass image authentication | 795| | during the boot process** | 796| | | 797| | | Time-of-Check-Time-of-Use (TOCTOU) threats occur | 798| | when the security check is produced before the time | 799| | the resource is accessed. If an attacker is sitting | 800| | in the middle of the off-chip images, they could | 801| | change the binary containing executable code right | 802| | after the integrity and authentication check has | 803| | been performed. | 804+------------------------+-------------------------------------------------------+ 805| Diagram Elements | DF1 | 806+------------------------+-------------------------------------------------------+ 807| Affected TF-A | BL1, BL2 | 808| Components | | 809+------------------------+-------------------------------------------------------+ 810| Assets | Code Execution, Sensitive Data | 811+------------------------+-------------------------------------------------------+ 812| Threat Agent | PhysicalAccess | 813+------------------------+-------------------------------------------------------+ 814| Threat Type | Elevation of Privilege | 815+------------------------+---------------------+-----------------+---------------+ 816| Application | Server | IoT | Mobile | 817+------------------------+---------------------+-----------------+---------------+ 818| Impact | N/A | Critical (5) | Critical (5) | 819+------------------------+---------------------+-----------------+---------------+ 820| Likelihood | N/A | Medium (3) | Medium (3) | 821+------------------------+---------------------+-----------------+---------------+ 822| Total Risk Rating | N/A | High (15) | High (15) | 823+------------------------+---------------------+-----------------+---------------+ 824| Mitigations | Copy image to on-chip memory before authenticating | 825| | it. | 826+------------------------+-------------------------------------------------------+ 827| Mitigations | | Platform specific. | 828| implemented? | | 829| | | The list of images to load and their location is | 830| | platform specific. Platforms are responsible for | 831| | arranging images to be loaded in on-chip memory. | 832+------------------------+-------------------------------------------------------+ 833 834 835+------------------------+-------------------------------------------------------+ 836| ID | 04 | 837+========================+=======================================================+ 838| Threat | | **An attacker with physical access can execute | 839| | arbitrary image by bypassing the signature | 840| | verification stage using glitching techniques** | 841| | | 842| | | Glitching (Fault injection) attacks attempt to put | 843| | a hardware into a undefined state by manipulating an| 844| | environmental variable such as power supply. | 845| | | 846| | | TF-A relies on a chain of trust that starts with the| 847| | ROTPK, which is the key stored inside the chip and | 848| | the root of all validation processes. If an attacker| 849| | can break this chain of trust, they could execute | 850| | arbitrary code on the device. This could be | 851| | achieved with physical access to the device by | 852| | attacking the normal execution flow of the | 853| | process using glitching techniques that target | 854| | points where the image is validated against the | 855| | signature. | 856+------------------------+-------------------------------------------------------+ 857| Diagram Elements | DF1 | 858+------------------------+-------------------------------------------------------+ 859| Affected TF-A | BL1, BL2 | 860| Components | | 861+------------------------+-------------------------------------------------------+ 862| Assets | Code Execution | 863+------------------------+-------------------------------------------------------+ 864| Threat Agent | PhysicalAccess | 865+------------------------+-------------------------------------------------------+ 866| Threat Type | Tampering, Elevation of Privilege | 867+------------------------+---------------------+-----------------+---------------+ 868| Application | Server | IoT | Mobile | 869+------------------------+---------------------+-----------------+---------------+ 870| Impact | N/A | Critical (5) | Critical (5) | 871+------------------------+---------------------+-----------------+---------------+ 872| Likelihood | N/A | Medium (3) | Medium (3) | 873+------------------------+---------------------+-----------------+---------------+ 874| Total Risk Rating | N/A | High (15) | High (15) | 875+------------------------+---------------------+-----------------+---------------+ 876| Mitigations | Mechanisms to detect clock glitch and power | 877| | variations. | 878+------------------------+-------------------------------------------------------+ 879| Mitigations | | No. | 880| implemented? | | 881| | | The most effective mitigation is adding glitching | 882| | detection and mitigation circuit at the hardware | 883| | level. | 884| | | 885| | | However, software techniques, such as adding | 886| | redundant checks when performing conditional | 887| | branches that are security sensitive, can be used | 888| | to harden TF-A against such attacks. | 889| | **At the moment TF-A doesn't implement such | 890| | mitigations.** | 891+------------------------+-------------------------------------------------------+ 892 893.. topic:: Measured Boot Threats (or lack of) 894 895 In the current Measured Boot design, BL1, BL2, and BL31, as well as the 896 secure world components, form the |SRTM|. Measurement data is currently 897 considered an asset to be protected against attack, and this is achieved 898 by storing them in the Secure Memory. 899 Beyond the measurements stored inside the TCG-compliant Event Log buffer, 900 there are no other assets to protect or threats to defend against that 901 could compromise |TF-A| execution environment's security. 902 903 There are general security assets and threats associated with remote/delegated 904 attestation. However, these are outside the |TF-A| security boundary and 905 should be dealt with by the appropriate agent in the platform/system. 906 Since current Measured Boot design does not use local attestation, there would 907 be no further assets to protect(like unsealed keys). 908 909 A limitation of the current Measured Boot design is that it is dependent upon 910 Secure Boot as implementation of Measured Boot does not extend measurements 911 into a discrete |TPM|, where they would be securely stored and protected 912 against tampering. This implies that if Secure-Boot is compromised, Measured 913 Boot may also be compromised. 914 915 Platforms must carefully evaluate the security of the default implementation 916 since the |SRTM| includes all secure world components. 917 918 919.. _Runtime Firmware Threats: 920 921Threats to be Mitigated by the Runtime EL3 Firmware 922--------------------------------------------------- 923 924+------------------------+------------------------------------------------------+ 925| ID | 07 | 926+========================+======================================================+ 927| Threat | | **An attacker can perform a denial-of-service | 928| | attack by using a broken SMC call that causes the | 929| | system to reboot or enter into unknown state.** | 930| | | 931| | | Secure and non-secure clients access TF-A services | 932| | through SMC calls. Malicious code can attempt to | 933| | place the TF-A runtime into an inconsistent state | 934| | by calling unimplemented SMC call or by passing | 935| | invalid arguments. | 936+------------------------+------------------------------------------------------+ 937| Diagram Elements | DF4, DF5 | 938+------------------------+------------------------------------------------------+ 939| Affected TF-A | BL31 | 940| Components | | 941+------------------------+------------------------------------------------------+ 942| Assets | Availability | 943+------------------------+------------------------------------------------------+ 944| Threat Agent | NSCode, SecCode | 945+------------------------+------------------------------------------------------+ 946| Threat Type | Denial of Service | 947+------------------------+-------------------+----------------+-----------------+ 948| Application | Server | IoT | Mobile | 949+------------------------+-------------------+----------------+-----------------+ 950| Impact | Medium (3) | Medium (3) | Medium (3) | 951+------------------------+-------------------+----------------+-----------------+ 952| Likelihood | High (4) | High (4) | High (4) | 953+------------------------+-------------------+----------------+-----------------+ 954| Total Risk Rating | High (12) | High (12) | High (12) | 955+------------------------+-------------------+----------------+-----------------+ 956| Mitigations | Validate SMC function ids and arguments before using | 957| | them. | 958+------------------------+------------------------------------------------------+ 959| Mitigations | | Yes / Platform specific. | 960| implemented? | | 961| | | For standard services, all input is validated. | 962| | | 963| | | Platforms that implement SiP services must also | 964| | validate SMC call arguments. | 965+------------------------+------------------------------------------------------+ 966 967 968+------------------------+------------------------------------------------------+ 969| ID | 09 | 970+========================+======================================================+ 971| Threat | | **Improperly handled SMC calls can leak register | 972| | contents** | 973| | | 974| | | When switching between worlds, TF-A register state | 975| | can leak to software in different security | 976| | contexts. | 977+------------------------+------------------------------------------------------+ 978| Diagram Elements | DF4, DF5 | 979+------------------------+------------------------------------------------------+ 980| Affected TF-A | BL31 | 981| Components | | 982+------------------------+------------------------------------------------------+ 983| Assets | Sensitive Data | 984+------------------------+------------------------------------------------------+ 985| Threat Agent | NSCode, SecCode | 986+------------------------+------------------------------------------------------+ 987| Threat Type | Information Disclosure | 988+------------------------+-------------------+----------------+-----------------+ 989| Application | Server | IoT | Mobile | 990+------------------------+-------------------+----------------+-----------------+ 991| Impact | Medium (3) | Medium (3) | Medium (3) | 992+------------------------+-------------------+----------------+-----------------+ 993| Likelihood | High (4) | High (4) | High (4) | 994+------------------------+-------------------+----------------+-----------------+ 995| Total Risk Rating | High (12) | High (12) | High (12) | 996+------------------------+-------------------+----------------+-----------------+ 997| Mitigations | Save and restore registers when switching contexts. | 998+------------------------+------------------------------------------------------+ 999| Mitigations | | Yes. | 1000| implemented? | | 1001| | | This is the default behaviour in TF-A. | 1002| | Build options are also provided to save/restore | 1003| | additional registers such as floating-point | 1004| | registers. These should be enabled if required. | 1005+------------------------+------------------------------------------------------+ 1006 1007+------------------------+-----------------------------------------------------+ 1008| ID | 10 | 1009+========================+=====================================================+ 1010| Threat | | **SMC calls can leak sensitive information from | 1011| | TF-A memory via microarchitectural side channels**| 1012| | | 1013| | | Microarchitectural side-channel attacks such as | 1014| | `Spectre`_ can be used to leak data across | 1015| | security boundaries. An attacker might attempt to | 1016| | use this kind of attack to leak sensitive | 1017| | data from TF-A memory. | 1018+------------------------+-----------------------------------------------------+ 1019| Diagram Elements | DF4, DF5 | 1020+------------------------+-----------------------------------------------------+ 1021| Affected TF-A | BL31 | 1022| Components | | 1023+------------------------+-----------------------------------------------------+ 1024| Assets | Sensitive Data | 1025+------------------------+-----------------------------------------------------+ 1026| Threat Agent | SecCode, NSCode | 1027+------------------------+-----------------------------------------------------+ 1028| Threat Type | Information Disclosure | 1029+------------------------+-------------------+----------------+----------------+ 1030| Application | Server | IoT | Mobile | 1031+------------------------+-------------------+----------------+----------------+ 1032| Impact | Medium (3) | Medium (3) | Medium (3) | 1033+------------------------+-------------------+----------------+----------------+ 1034| Likelihood | Medium (3) | Medium (3) | Medium (3) | 1035+------------------------+-------------------+----------------+----------------+ 1036| Total Risk Rating | Medium (9) | Medium (9) | Medium (9) | 1037+------------------------+-------------------+----------------+----------------+ 1038| Mitigations | Enable appropriate side-channel protections. | 1039+------------------------+-----------------------------------------------------+ 1040| Mitigations | | Yes / Platform specific. | 1041| implemented? | | 1042| | | TF-A implements software mitigations for Spectre | 1043| | type attacks as recommended by `Cache Speculation | 1044| | Side-channels`_ for the generic code. | 1045| | | 1046| | | SiPs should implement similar mitigations for | 1047| | code that is deemed to be vulnerable to such | 1048| | attacks. | 1049+------------------------+-----------------------------------------------------+ 1050 1051 1052+------------------------+-----------------------------------------------------+ 1053| ID | 12 | 1054+========================+=====================================================+ 1055| Threat | | **Incorrect configuration of Performance Monitor | 1056| | Unit (PMU) counters can allow an attacker to | 1057| | mount side-channel attacks using information | 1058| | exposed by the counters** | 1059| | | 1060| | | Non-secure software can configure PMU registers | 1061| | to count events at any exception level and in | 1062| | both Secure and Non-secure states. This allows | 1063| | a Non-secure software (or a lower-level Secure | 1064| | software) to potentially carry out | 1065| | side-channel timing attacks against TF-A. | 1066+------------------------+-----------------------------------------------------+ 1067| Diagram Elements | DF5, DF6 | 1068+------------------------+-----------------------------------------------------+ 1069| Affected TF-A | BL31 | 1070| Components | | 1071+------------------------+-----------------------------------------------------+ 1072| Assets | Sensitive Data | 1073+------------------------+-----------------------------------------------------+ 1074| Threat Agent | NSCode | 1075+------------------------+-----------------------------------------------------+ 1076| Threat Type | Information Disclosure | 1077+------------------------+-------------------+----------------+----------------+ 1078| Application | Server | IoT | Mobile | 1079+------------------------+-------------------+----------------+----------------+ 1080| Impact | Medium (3) | Medium (3) | Medium (3) | 1081+------------------------+-------------------+----------------+----------------+ 1082| Likelihood | Low (2) | Low (2) | Low (2) | 1083+------------------------+-------------------+----------------+----------------+ 1084| Total Risk Rating | Medium (6) | Medium (6) | Medium (6) | 1085+------------------------+-------------------+----------------+----------------+ 1086| Mitigations | Follow mitigation strategies as described in | 1087| | `Secure Development Guidelines`_. | 1088+------------------------+-----------------------------------------------------+ 1089| Mitigations | | Yes / platform specific. | 1090| implemented? | | 1091| | | General events and cycle counting in the Secure | 1092| | world is prohibited by default when applicable. | 1093| | | 1094| | | However, on some implementations (e.g. PMUv3) | 1095| | Secure world event counting depends on external | 1096| | debug interface signals, i.e. Secure world event | 1097| | counting is enabled if external debug is enabled. | 1098| | | 1099| | | Configuration of debug signals is platform | 1100| | specific, therefore platforms need to make sure | 1101| | that external debug is disabled in production or | 1102| | proper debug authentication is in place. This | 1103| | should be the case if threat #06 is properly | 1104| | mitigated. | 1105+------------------------+-----------------------------------------------------+ 1106 1107 1108Threats to be Mitigated by an External Agent Outside of TF-A 1109------------------------------------------------------------ 1110 1111+------------------------+-----------------------------------------------------+ 1112| ID | 14 | 1113+========================+=====================================================+ 1114| Threat | | **Attacker wants to execute an arbitrary or | 1115| | untrusted binary as the secure OS.** | 1116| | | 1117| | | When the option OPTEE_ALLOW_SMC_LOAD is enabled, | 1118| | this trusts the non-secure world up until the | 1119| | point it issues the SMC call to load the Secure | 1120| | BL32 payload. If a compromise occurs before the | 1121| | SMC call is invoked, then arbitrary code execution| 1122| | in S-EL1 can occur or arbitrary memory in EL3 can | 1123| | be overwritten. | 1124+------------------------+-----------------------------------------------------+ 1125| Diagram Elements | DF5 | 1126+------------------------+-----------------------------------------------------+ 1127| Affected TF-A | BL31, BL32 | 1128| Components | | 1129+------------------------+-----------------------------------------------------+ 1130| Assets | Code Execution, Sensitive Data | 1131+------------------------+-----------------------------------------------------+ 1132| Threat Agent | NSCode | 1133+------------------------+-----------------------------------------------------+ 1134| Threat Type | Tampering, Information Disclosure, | 1135| | Elevation of privilege | 1136+------------------------+-----------------+-----------------+-----------------+ 1137| Application | Server | IoT | Mobile | 1138+------------------------+-----------------+-----------------+-----------------+ 1139| Impact | Critical (5) | Critical (5) | Critical (5) | 1140+------------------------+-----------------+-----------------+-----------------+ 1141| Likelihood | High (4) | High (4) | High (4) | 1142+------------------------+-----------------+-----------------+-----------------+ 1143| Total Risk Rating | Critical (20) | Critical (20) | Critical (20) | 1144+------------------------+-----------------+-----------------+-----------------+ 1145| Mitigations | When enabling the option OPTEE_ALLOW_SMC_LOAD, | 1146| | the non-secure OS must be considered a closed | 1147| | platform up until the point the SMC can be invoked | 1148| | to load OP-TEE. | 1149+------------------------+-----------------------------------------------------+ 1150| Mitigations | | None in TF-A itself. This option is only used by | 1151| implemented? | ChromeOS currently which has other mechanisms to | 1152| | to mitigate this threat which are described in | 1153| | `OP-TEE Dispatcher`_. | 1154+------------------------+-----------------------------------------------------+ 1155 1156-------------- 1157 1158*Copyright (c) 2021-2024, Arm Limited. All rights reserved.* 1159 1160 1161.. _STRIDE threat analysis technique: https://docs.microsoft.com/en-us/azure/security/develop/threat-modeling-tool-threats#stride-model 1162.. _DEN0034: https://developer.arm.com/documentation/den0034/latest 1163.. _Cache Speculation Side-channels: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability 1164.. _Spectre: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability 1165.. _TBBR-Client specification: https://developer.arm.com/documentation/den0006/d/ 1166.. _Trusted Board Boot (TBB): https://trustedfirmware-a.readthedocs.io/en/latest/design/trusted-board-boot.html 1167.. _TF-A error handling policy: https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#error-handling-and-robustness 1168.. _Secure Development Guidelines: https://trustedfirmware-a.readthedocs.io/en/latest/process/security-hardening.html#secure-development-guidelines 1169.. _Trusted Firmware-A Tests: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/about/ 1170.. _OP-TEE Dispatcher: https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/components/spd/optee-dispatcher.rst 1171.. _PSR Specification: https://developer.arm.com/documentation/den0106/0100 1172