1Porting Guide 2============= 3 4Introduction 5------------ 6 7Porting Trusted Firmware-A (TF-A) to a new platform involves making some 8mandatory and optional modifications for both the cold and warm boot paths. 9Modifications consist of: 10 11- Implementing a platform-specific function or variable, 12- Setting up the execution context in a certain way, or 13- Defining certain constants (for example #defines). 14 15The platform-specific functions and variables are declared in 16``include/plat/common/platform.h``. The firmware provides a default 17implementation of variables and functions to fulfill the optional requirements 18in order to ease the porting effort. Each platform port can use them as is or 19provide their own implementation if the default implementation is inadequate. 20 21 .. note:: 22 23 TF-A historically provided default implementations of platform interfaces 24 as *weak* functions. This practice is now discouraged and new platform 25 interfaces as they get introduced in the code base should be *strongly* 26 defined. We intend to convert existing weak functions over time. Until 27 then, you will find references to *weak* functions in this document. 28 29Please review the :ref:`Threat Model` documents as part of the porting 30effort. Some platform interfaces play a key role in mitigating against some of 31the threats. Failing to fulfill these expectations could undermine the security 32guarantees offered by TF-A. These platform responsibilities are highlighted in 33the threat assessment section, under the "`Mitigations implemented?`" box for 34each threat. 35 36Some modifications are common to all Boot Loader (BL) stages. Section 2 37discusses these in detail. The subsequent sections discuss the remaining 38modifications for each BL stage in detail. 39 40Please refer to the :ref:`Platform Ports Policy` for the policy regarding 41compatibility and deprecation of these porting interfaces. 42 43Only Arm development platforms (such as FVP and Juno) may use the 44functions/definitions in ``include/plat/arm/common/`` and the corresponding 45source files in ``plat/arm/common/``. This is done so that there are no 46dependencies between platforms maintained by different people/companies. If you 47want to use any of the functionality present in ``plat/arm`` files, please 48propose a patch that moves the code to ``plat/common`` so that it can be 49discussed. 50 51Common modifications 52-------------------- 53 54This section covers the modifications that should be made by the platform for 55each BL stage to correctly port the firmware stack. They are categorized as 56either mandatory or optional. 57 58Common mandatory modifications 59------------------------------ 60 61A platform port must enable the Memory Management Unit (MMU) as well as the 62instruction and data caches for each BL stage. Setting up the translation 63tables is the responsibility of the platform port because memory maps differ 64across platforms. A memory translation library (see ``lib/xlat_tables_v2/``) is 65provided to help in this setup. 66 67Note that although this library supports non-identity mappings, this is intended 68only for re-mapping peripheral physical addresses and allows platforms with high 69I/O addresses to reduce their virtual address space. All other addresses 70corresponding to code and data must currently use an identity mapping. 71 72Also, the only translation granule size supported in TF-A is 4KB, as various 73parts of the code assume that is the case. It is not possible to switch to 7416 KB or 64 KB granule sizes at the moment. 75 76In Arm standard platforms, each BL stage configures the MMU in the 77platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 78an identity mapping for all addresses. 79 80If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 81block of identity mapped secure memory with Device-nGnRE attributes aligned to 82page boundary (4K) for each BL stage. All sections which allocate coherent 83memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a 84section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its 85possible for the firmware to place variables in it using the following C code 86directive: 87 88:: 89 90 __section(".bakery_lock") 91 92Or alternatively the following assembler code directive: 93 94:: 95 96 .section .bakery_lock 97 98The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are 99used to allocate any data structures that are accessed both when a CPU is 100executing with its MMU and caches enabled, and when it's running with its MMU 101and caches disabled. Examples are given below. 102 103The following variables, functions and constants must be defined by the platform 104for the firmware to work correctly. 105 106.. _platform_def_mandatory: 107 108File : platform_def.h [mandatory] 109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 110 111Each platform must ensure that a header file of this name is in the system 112include path with the following constants defined. This will require updating 113the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 114 115Platform ports may optionally use the file ``include/plat/common/common_def.h``, 116which provides typical values for some of the constants below. These values are 117likely to be suitable for all platform ports. 118 119- **#define : PLATFORM_LINKER_FORMAT** 120 121 Defines the linker format used by the platform, for example 122 ``elf64-littleaarch64``. 123 124- **#define : PLATFORM_LINKER_ARCH** 125 126 Defines the processor architecture for the linker by the platform, for 127 example ``aarch64``. 128 129- **#define : PLATFORM_STACK_SIZE** 130 131 Defines the normal stack memory available to each CPU. This constant is used 132 by ``plat/common/aarch64/platform_mp_stack.S`` and 133 ``plat/common/aarch64/platform_up_stack.S``. 134 135- **#define : CACHE_WRITEBACK_GRANULE** 136 137 Defines the size in bytes of the largest cache line across all the cache 138 levels in the platform. 139 140- **#define : FIRMWARE_WELCOME_STR** 141 142 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 143 function. 144 145- **#define : PLATFORM_CORE_COUNT** 146 147 Defines the total number of CPUs implemented by the platform across all 148 clusters in the system. 149 150- **#define : PLAT_NUM_PWR_DOMAINS** 151 152 Defines the total number of nodes in the power domain topology 153 tree at all the power domain levels used by the platform. 154 This macro is used by the PSCI implementation to allocate 155 data structures to represent power domain topology. 156 157- **#define : PLAT_MAX_PWR_LVL** 158 159 Defines the maximum power domain level that the power management operations 160 should apply to. More often, but not always, the power domain level 161 corresponds to affinity level. This macro allows the PSCI implementation 162 to know the highest power domain level that it should consider for power 163 management operations in the system that the platform implements. For 164 example, the Base AEM FVP implements two clusters with a configurable 165 number of CPUs and it reports the maximum power domain level as 1. 166 167- **#define : PLAT_MAX_OFF_STATE** 168 169 Defines the local power state corresponding to the deepest power down 170 possible at every power domain level in the platform. The local power 171 states for each level may be sparsely allocated between 0 and this value 172 with 0 being reserved for the RUN state. The PSCI implementation uses this 173 value to initialize the local power states of the power domain nodes and 174 to specify the requested power state for a PSCI_CPU_OFF call. 175 176- **#define : PLAT_MAX_RET_STATE** 177 178 Defines the local power state corresponding to the deepest retention state 179 possible at every power domain level in the platform. This macro should be 180 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 181 PSCI implementation to distinguish between retention and power down local 182 power states within PSCI_CPU_SUSPEND call. 183 184- **#define : PLAT_MAX_PWR_LVL_STATES** 185 186 Defines the maximum number of local power states per power domain level 187 that the platform supports. The default value of this macro is 2 since 188 most platforms just support a maximum of two local power states at each 189 power domain level (power-down and retention). If the platform needs to 190 account for more local power states, then it must redefine this macro. 191 192 Currently, this macro is used by the Generic PSCI implementation to size 193 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 194 195- **#define : BL1_RO_BASE** 196 197 Defines the base address in secure ROM where BL1 originally lives. Must be 198 aligned on a page-size boundary. 199 200- **#define : BL1_RO_LIMIT** 201 202 Defines the maximum address in secure ROM that BL1's actual content (i.e. 203 excluding any data section allocated at runtime) can occupy. 204 205- **#define : BL1_RW_BASE** 206 207 Defines the base address in secure RAM where BL1's read-write data will live 208 at runtime. Must be aligned on a page-size boundary. 209 210- **#define : BL1_RW_LIMIT** 211 212 Defines the maximum address in secure RAM that BL1's read-write data can 213 occupy at runtime. 214 215- **#define : BL2_BASE** 216 217 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 218 Must be aligned on a page-size boundary. This constant is not applicable 219 when BL2_IN_XIP_MEM is set to '1'. 220 221- **#define : BL2_LIMIT** 222 223 Defines the maximum address in secure RAM that the BL2 image can occupy. 224 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2_RO_BASE** 227 228 Defines the base address in secure XIP memory where BL2 RO section originally 229 lives. Must be aligned on a page-size boundary. This constant is only needed 230 when BL2_IN_XIP_MEM is set to '1'. 231 232- **#define : BL2_RO_LIMIT** 233 234 Defines the maximum address in secure XIP memory that BL2's actual content 235 (i.e. excluding any data section allocated at runtime) can occupy. This 236 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 237 238- **#define : BL2_RW_BASE** 239 240 Defines the base address in secure RAM where BL2's read-write data will live 241 at runtime. Must be aligned on a page-size boundary. This constant is only 242 needed when BL2_IN_XIP_MEM is set to '1'. 243 244- **#define : BL2_RW_LIMIT** 245 246 Defines the maximum address in secure RAM that BL2's read-write data can 247 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 248 to '1'. 249 250- **#define : BL31_BASE** 251 252 Defines the base address in secure RAM where BL2 loads the BL31 binary 253 image. Must be aligned on a page-size boundary. 254 255- **#define : BL31_LIMIT** 256 257 Defines the maximum address in secure RAM that the BL31 image can occupy. 258 259- **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE** 260 261 Defines the maximum message size between AP and RSS. Need to define if 262 platform supports RSS. 263 264For every image, the platform must define individual identifiers that will be 265used by BL1 or BL2 to load the corresponding image into memory from non-volatile 266storage. For the sake of performance, integer numbers will be used as 267identifiers. The platform will use those identifiers to return the relevant 268information about the image to be loaded (file handler, load address, 269authentication information, etc.). The following image identifiers are 270mandatory: 271 272- **#define : BL2_IMAGE_ID** 273 274 BL2 image identifier, used by BL1 to load BL2. 275 276- **#define : BL31_IMAGE_ID** 277 278 BL31 image identifier, used by BL2 to load BL31. 279 280- **#define : BL33_IMAGE_ID** 281 282 BL33 image identifier, used by BL2 to load BL33. 283 284If Trusted Board Boot is enabled, the following certificate identifiers must 285also be defined: 286 287- **#define : TRUSTED_BOOT_FW_CERT_ID** 288 289 BL2 content certificate identifier, used by BL1 to load the BL2 content 290 certificate. 291 292- **#define : TRUSTED_KEY_CERT_ID** 293 294 Trusted key certificate identifier, used by BL2 to load the trusted key 295 certificate. 296 297- **#define : SOC_FW_KEY_CERT_ID** 298 299 BL31 key certificate identifier, used by BL2 to load the BL31 key 300 certificate. 301 302- **#define : SOC_FW_CONTENT_CERT_ID** 303 304 BL31 content certificate identifier, used by BL2 to load the BL31 content 305 certificate. 306 307- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 308 309 BL33 key certificate identifier, used by BL2 to load the BL33 key 310 certificate. 311 312- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 313 314 BL33 content certificate identifier, used by BL2 to load the BL33 content 315 certificate. 316 317- **#define : FWU_CERT_ID** 318 319 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 320 FWU content certificate. 321 322- **#define : PLAT_CRYPTOCELL_BASE** 323 324 This defines the base address of Arm® TrustZone® CryptoCell and must be 325 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 326 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 327 set. 328 329If the AP Firmware Updater Configuration image, BL2U is used, the following 330must also be defined: 331 332- **#define : BL2U_BASE** 333 334 Defines the base address in secure memory where BL1 copies the BL2U binary 335 image. Must be aligned on a page-size boundary. 336 337- **#define : BL2U_LIMIT** 338 339 Defines the maximum address in secure memory that the BL2U image can occupy. 340 341- **#define : BL2U_IMAGE_ID** 342 343 BL2U image identifier, used by BL1 to fetch an image descriptor 344 corresponding to BL2U. 345 346If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 347must also be defined: 348 349- **#define : SCP_BL2U_IMAGE_ID** 350 351 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 352 corresponding to SCP_BL2U. 353 354 .. note:: 355 TF-A does not provide source code for this image. 356 357If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 358also be defined: 359 360- **#define : NS_BL1U_BASE** 361 362 Defines the base address in non-secure ROM where NS_BL1U executes. 363 Must be aligned on a page-size boundary. 364 365 .. note:: 366 TF-A does not provide source code for this image. 367 368- **#define : NS_BL1U_IMAGE_ID** 369 370 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 371 corresponding to NS_BL1U. 372 373If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 374be defined: 375 376- **#define : NS_BL2U_BASE** 377 378 Defines the base address in non-secure memory where NS_BL2U executes. 379 Must be aligned on a page-size boundary. 380 381 .. note:: 382 TF-A does not provide source code for this image. 383 384- **#define : NS_BL2U_IMAGE_ID** 385 386 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 387 corresponding to NS_BL2U. 388 389For the the Firmware update capability of TRUSTED BOARD BOOT, the following 390macros may also be defined: 391 392- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 393 394 Total number of images that can be loaded simultaneously. If the platform 395 doesn't specify any value, it defaults to 10. 396 397If a SCP_BL2 image is supported by the platform, the following constants must 398also be defined: 399 400- **#define : SCP_BL2_IMAGE_ID** 401 402 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 403 from platform storage before being transferred to the SCP. 404 405- **#define : SCP_FW_KEY_CERT_ID** 406 407 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 408 certificate (mandatory when Trusted Board Boot is enabled). 409 410- **#define : SCP_FW_CONTENT_CERT_ID** 411 412 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 413 content certificate (mandatory when Trusted Board Boot is enabled). 414 415If a BL32 image is supported by the platform, the following constants must 416also be defined: 417 418- **#define : BL32_IMAGE_ID** 419 420 BL32 image identifier, used by BL2 to load BL32. 421 422- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 423 424 BL32 key certificate identifier, used by BL2 to load the BL32 key 425 certificate (mandatory when Trusted Board Boot is enabled). 426 427- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 428 429 BL32 content certificate identifier, used by BL2 to load the BL32 content 430 certificate (mandatory when Trusted Board Boot is enabled). 431 432- **#define : BL32_BASE** 433 434 Defines the base address in secure memory where BL2 loads the BL32 binary 435 image. Must be aligned on a page-size boundary. 436 437- **#define : BL32_LIMIT** 438 439 Defines the maximum address that the BL32 image can occupy. 440 441If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 442platform, the following constants must also be defined: 443 444- **#define : TSP_SEC_MEM_BASE** 445 446 Defines the base address of the secure memory used by the TSP image on the 447 platform. This must be at the same address or below ``BL32_BASE``. 448 449- **#define : TSP_SEC_MEM_SIZE** 450 451 Defines the size of the secure memory used by the BL32 image on the 452 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 453 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 454 and ``BL32_LIMIT``. 455 456- **#define : TSP_IRQ_SEC_PHY_TIMER** 457 458 Defines the ID of the secure physical generic timer interrupt used by the 459 TSP's interrupt handling code. 460 461If the platform port uses the translation table library code, the following 462constants must also be defined: 463 464- **#define : PLAT_XLAT_TABLES_DYNAMIC** 465 466 Optional flag that can be set per-image to enable the dynamic allocation of 467 regions even when the MMU is enabled. If not defined, only static 468 functionality will be available, if defined and set to 1 it will also 469 include the dynamic functionality. 470 471- **#define : MAX_XLAT_TABLES** 472 473 Defines the maximum number of translation tables that are allocated by the 474 translation table library code. To minimize the amount of runtime memory 475 used, choose the smallest value needed to map the required virtual addresses 476 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 477 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 478 as well. 479 480- **#define : MAX_MMAP_REGIONS** 481 482 Defines the maximum number of regions that are allocated by the translation 483 table library code. A region consists of physical base address, virtual base 484 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 485 defined in the ``mmap_region_t`` structure. The platform defines the regions 486 that should be mapped. Then, the translation table library will create the 487 corresponding tables and descriptors at runtime. To minimize the amount of 488 runtime memory used, choose the smallest value needed to register the 489 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 490 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 491 the dynamic regions as well. 492 493- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 494 495 Defines the total size of the virtual address space in bytes. For example, 496 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 497 498- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 499 500 Defines the total size of the physical address space in bytes. For example, 501 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 502 503If the platform port uses the IO storage framework, the following constants 504must also be defined: 505 506- **#define : MAX_IO_DEVICES** 507 508 Defines the maximum number of registered IO devices. Attempting to register 509 more devices than this value using ``io_register_device()`` will fail with 510 -ENOMEM. 511 512- **#define : MAX_IO_HANDLES** 513 514 Defines the maximum number of open IO handles. Attempting to open more IO 515 entities than this value using ``io_open()`` will fail with -ENOMEM. 516 517- **#define : MAX_IO_BLOCK_DEVICES** 518 519 Defines the maximum number of registered IO block devices. Attempting to 520 register more devices this value using ``io_dev_open()`` will fail 521 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 522 With this macro, multiple block devices could be supported at the same 523 time. 524 525If the platform needs to allocate data within the per-cpu data framework in 526BL31, it should define the following macro. Currently this is only required if 527the platform decides not to use the coherent memory section by undefining the 528``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 529required memory within the the per-cpu data to minimize wastage. 530 531- **#define : PLAT_PCPU_DATA_SIZE** 532 533 Defines the memory (in bytes) to be reserved within the per-cpu data 534 structure for use by the platform layer. 535 536The following constants are optional. They should be defined when the platform 537memory layout implies some image overlaying like in Arm standard platforms. 538 539- **#define : BL31_PROGBITS_LIMIT** 540 541 Defines the maximum address in secure RAM that the BL31's progbits sections 542 can occupy. 543 544- **#define : TSP_PROGBITS_LIMIT** 545 546 Defines the maximum address that the TSP's progbits sections can occupy. 547 548If the platform supports OS-initiated mode, i.e. the build option 549``PSCI_OS_INIT_MODE`` is enabled, and if the platform's maximum power domain 550level for PSCI_CPU_SUSPEND differs from ``PLAT_MAX_PWR_LVL``, the following 551constant must be defined. 552 553- **#define : PLAT_MAX_CPU_SUSPEND_PWR_LVL** 554 555 Defines the maximum power domain level that PSCI_CPU_SUSPEND should apply to. 556 557If the platform port uses the PL061 GPIO driver, the following constant may 558optionally be defined: 559 560- **PLAT_PL061_MAX_GPIOS** 561 Maximum number of GPIOs required by the platform. This allows control how 562 much memory is allocated for PL061 GPIO controllers. The default value is 563 564 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 565 566If the platform port uses the partition driver, the following constant may 567optionally be defined: 568 569- **PLAT_PARTITION_MAX_ENTRIES** 570 Maximum number of partition entries required by the platform. This allows 571 control how much memory is allocated for partition entries. The default 572 value is 128. 573 For example, define the build flag in ``platform.mk``: 574 PLAT_PARTITION_MAX_ENTRIES := 12 575 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 576 577- **PLAT_PARTITION_BLOCK_SIZE** 578 The size of partition block. It could be either 512 bytes or 4096 bytes. 579 The default value is 512. 580 For example, define the build flag in ``platform.mk``: 581 PLAT_PARTITION_BLOCK_SIZE := 4096 582 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) 583 584If the platform port uses the Arm® Ethos™-N NPU driver, the following 585configuration must be performed: 586 587- The NPU SiP service handler must be hooked up. This consists of both the 588 initial setup (``ethosn_smc_setup``) and the handler itself 589 (``ethosn_smc_handler``) 590 591If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support 592enabled, the following constants and configuration must also be defined: 593 594- **ETHOSN_NPU_PROT_FW_NSAID** 595 596 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to 597 access the protected memory that contains the NPU's firmware. 598 599- **ETHOSN_NPU_PROT_DATA_RW_NSAID** 600 601 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 602 read/write access to the protected memory that contains inference data. 603 604- **ETHOSN_NPU_PROT_DATA_RO_NSAID** 605 606 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 607 read-only access to the protected memory that contains inference data. 608 609- **ETHOSN_NPU_NS_RW_DATA_NSAID** 610 611 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 612 read/write access to the non-protected memory. 613 614- **ETHOSN_NPU_NS_RO_DATA_NSAID** 615 616 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 617 read-only access to the non-protected memory. 618 619- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT** 620 621 Defines the physical address range that the NPU's firmware will be loaded 622 into and executed from. 623 624- Configure the platforms TrustZone Controller (TZC) with appropriate regions 625 of protected memory. At minimum this must include a region for the NPU's 626 firmware code and a region for protected inference data, and these must be 627 accessible using the NSAIDs defined above. 628 629- Include the NPU firmware and certificates in the FIP. 630 631- Provide FCONF entries to configure the image source for the NPU firmware 632 and certificates. 633 634- Add MMU mappings such that: 635 636 - BL2 can write the NPU firmware into the region defined by 637 ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT`` 638 - BL31 (SiP service) can read the NPU firmware from the same region 639 640- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images 641 loaded by BL2. 642 643Please see the reference implementation code for the Juno platform as an example. 644 645 646The following constant is optional. It should be defined to override the default 647behaviour of the ``assert()`` function (for example, to save memory). 648 649- **PLAT_LOG_LEVEL_ASSERT** 650 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 651 ``assert()`` prints the name of the file, the line number and the asserted 652 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 653 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 654 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 655 defined, it defaults to ``LOG_LEVEL``. 656 657If the platform port uses the DRTM feature, the following constants must be 658defined: 659 660- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE** 661 662 Maximum Event Log size used by the platform. Platform can decide the maximum 663 size of the Event Log buffer, depending upon the highest hash algorithm 664 chosen and the number of components selected to measure during the DRTM 665 execution flow. 666 667- **#define : PLAT_DRTM_MMAP_ENTRIES** 668 669 Number of the MMAP entries used by the DRTM implementation to calculate the 670 size of address map region of the platform. 671 672File : plat_macros.S [mandatory] 673~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 674 675Each platform must ensure a file of this name is in the system include path with 676the following macro defined. In the Arm development platforms, this file is 677found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 678 679- **Macro : plat_crash_print_regs** 680 681 This macro allows the crash reporting routine to print relevant platform 682 registers in case of an unhandled exception in BL31. This aids in debugging 683 and this macro can be defined to be empty in case register reporting is not 684 desired. 685 686 For instance, GIC or interconnect registers may be helpful for 687 troubleshooting. 688 689Handling Reset 690-------------- 691 692BL1 by default implements the reset vector where execution starts from a cold 693or warm boot. BL31 can be optionally set as a reset vector using the 694``RESET_TO_BL31`` make variable. 695 696For each CPU, the reset vector code is responsible for the following tasks: 697 698#. Distinguishing between a cold boot and a warm boot. 699 700#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 701 the CPU is placed in a platform-specific state until the primary CPU 702 performs the necessary steps to remove it from this state. 703 704#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 705 specific address in the BL31 image in the same processor mode as it was 706 when released from reset. 707 708The following functions need to be implemented by the platform port to enable 709reset vector code to perform the above tasks. 710 711Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 712~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 713 714:: 715 716 Argument : void 717 Return : uintptr_t 718 719This function is called with the MMU and caches disabled 720(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 721distinguishing between a warm and cold reset for the current CPU using 722platform-specific means. If it's a warm reset, then it returns the warm 723reset entrypoint point provided to ``plat_setup_psci_ops()`` during 724BL31 initialization. If it's a cold reset then this function must return zero. 725 726This function does not follow the Procedure Call Standard used by the 727Application Binary Interface for the Arm 64-bit architecture. The caller should 728not assume that callee saved registers are preserved across a call to this 729function. 730 731This function fulfills requirement 1 and 3 listed above. 732 733Note that for platforms that support programming the reset address, it is 734expected that a CPU will start executing code directly at the right address, 735both on a cold and warm reset. In this case, there is no need to identify the 736type of reset nor to query the warm reset entrypoint. Therefore, implementing 737this function is not required on such platforms. 738 739Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 740~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 741 742:: 743 744 Argument : void 745 746This function is called with the MMU and data caches disabled. It is responsible 747for placing the executing secondary CPU in a platform-specific state until the 748primary CPU performs the necessary actions to bring it out of that state and 749allow entry into the OS. This function must not return. 750 751In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 752itself off. The primary CPU is responsible for powering up the secondary CPUs 753when normal world software requires them. When booting an EL3 payload instead, 754they stay powered on and are put in a holding pen until their mailbox gets 755populated. 756 757This function fulfills requirement 2 above. 758 759Note that for platforms that can't release secondary CPUs out of reset, only the 760primary CPU will execute the cold boot code. Therefore, implementing this 761function is not required on such platforms. 762 763Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 764~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 765 766:: 767 768 Argument : void 769 Return : unsigned int 770 771This function identifies whether the current CPU is the primary CPU or a 772secondary CPU. A return value of zero indicates that the CPU is not the 773primary CPU, while a non-zero return value indicates that the CPU is the 774primary CPU. 775 776Note that for platforms that can't release secondary CPUs out of reset, only the 777primary CPU will execute the cold boot code. Therefore, there is no need to 778distinguish between primary and secondary CPUs and implementing this function is 779not required. 780 781Function : platform_mem_init() [mandatory] 782~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 783 784:: 785 786 Argument : void 787 Return : void 788 789This function is called before any access to data is made by the firmware, in 790order to carry out any essential memory initialization. 791 792Function: plat_get_rotpk_info() 793~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 794 795:: 796 797 Argument : void *, void **, unsigned int *, unsigned int * 798 Return : int 799 800This function is mandatory when Trusted Board Boot is enabled. It returns a 801pointer to the ROTPK stored in the platform (or a hash of it) and its length. 802The ROTPK must be encoded in DER format according to the following ASN.1 803structure: 804 805:: 806 807 AlgorithmIdentifier ::= SEQUENCE { 808 algorithm OBJECT IDENTIFIER, 809 parameters ANY DEFINED BY algorithm OPTIONAL 810 } 811 812 SubjectPublicKeyInfo ::= SEQUENCE { 813 algorithm AlgorithmIdentifier, 814 subjectPublicKey BIT STRING 815 } 816 817In case the function returns a hash of the key: 818 819:: 820 821 DigestInfo ::= SEQUENCE { 822 digestAlgorithm AlgorithmIdentifier, 823 digest OCTET STRING 824 } 825 826The function returns 0 on success. Any other value is treated as error by the 827Trusted Board Boot. The function also reports extra information related 828to the ROTPK in the flags parameter: 829 830:: 831 832 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 833 hash. 834 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 835 verification while the platform ROTPK is not deployed. 836 When this flag is set, the function does not need to 837 return a platform ROTPK, and the authentication 838 framework uses the ROTPK in the certificate without 839 verifying it against the platform value. This flag 840 must not be used in a deployed production environment. 841 842Function: plat_get_nv_ctr() 843~~~~~~~~~~~~~~~~~~~~~~~~~~~ 844 845:: 846 847 Argument : void *, unsigned int * 848 Return : int 849 850This function is mandatory when Trusted Board Boot is enabled. It returns the 851non-volatile counter value stored in the platform in the second argument. The 852cookie in the first argument may be used to select the counter in case the 853platform provides more than one (for example, on platforms that use the default 854TBBR CoT, the cookie will correspond to the OID values defined in 855TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 856 857The function returns 0 on success. Any other value means the counter value could 858not be retrieved from the platform. 859 860Function: plat_set_nv_ctr() 861~~~~~~~~~~~~~~~~~~~~~~~~~~~ 862 863:: 864 865 Argument : void *, unsigned int 866 Return : int 867 868This function is mandatory when Trusted Board Boot is enabled. It sets a new 869counter value in the platform. The cookie in the first argument may be used to 870select the counter (as explained in plat_get_nv_ctr()). The second argument is 871the updated counter value to be written to the NV counter. 872 873The function returns 0 on success. Any other value means the counter value could 874not be updated. 875 876Function: plat_set_nv_ctr2() 877~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 878 879:: 880 881 Argument : void *, const auth_img_desc_t *, unsigned int 882 Return : int 883 884This function is optional when Trusted Board Boot is enabled. If this 885interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 886first argument passed is a cookie and is typically used to 887differentiate between a Non Trusted NV Counter and a Trusted NV 888Counter. The second argument is a pointer to an authentication image 889descriptor and may be used to decide if the counter is allowed to be 890updated or not. The third argument is the updated counter value to 891be written to the NV counter. 892 893The function returns 0 on success. Any other value means the counter value 894either could not be updated or the authentication image descriptor indicates 895that it is not allowed to be updated. 896 897Dynamic Root of Trust for Measurement support (in BL31) 898------------------------------------------------------- 899 900The functions mentioned in this section are mandatory, when platform enables 901DRTM_SUPPORT build flag. 902 903Function : plat_get_addr_mmap() 904~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 905 906:: 907 908 Argument : void 909 Return : const mmap_region_t * 910 911This function is used to return the address of the platform *address-map* table, 912which describes the regions of normal memory, memory mapped I/O 913and non-volatile memory. 914 915Function : plat_has_non_host_platforms() 916~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 917 918:: 919 920 Argument : void 921 Return : bool 922 923This function returns *true* if the platform has any trusted devices capable of 924DMA, otherwise returns *false*. 925 926Function : plat_has_unmanaged_dma_peripherals() 927~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 928 929:: 930 931 Argument : void 932 Return : bool 933 934This function returns *true* if platform uses peripherals whose DMA is not 935managed by an SMMU, otherwise returns *false*. 936 937Note - 938If the platform has peripherals that are not managed by the SMMU, then the 939platform should investigate such peripherals to determine whether they can 940be trusted, and such peripherals should be moved under "Non-host platforms" 941if they can be trusted. 942 943Function : plat_get_total_num_smmus() 944~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 945 946:: 947 948 Argument : void 949 Return : unsigned int 950 951This function returns the total number of SMMUs in the platform. 952 953Function : plat_enumerate_smmus() 954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 955:: 956 957 958 Argument : void 959 Return : const uintptr_t *, size_t 960 961This function returns an array of SMMU addresses and the actual number of SMMUs 962reported by the platform. 963 964Function : plat_drtm_get_dma_prot_features() 965~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 966 967:: 968 969 Argument : void 970 Return : const plat_drtm_dma_prot_features_t* 971 972This function returns the address of plat_drtm_dma_prot_features_t structure 973containing the maximum number of protected regions and bitmap with the types 974of DMA protection supported by the platform. 975For more details see section 3.3 Table 6 of `DRTM`_ specification. 976 977Function : plat_drtm_dma_prot_get_max_table_bytes() 978~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 979 980:: 981 982 Argument : void 983 Return : uint64_t 984 985This function returns the maximum size of DMA protected regions table in 986bytes. 987 988Function : plat_drtm_get_tpm_features() 989~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 990 991:: 992 993 Argument : void 994 Return : const plat_drtm_tpm_features_t* 995 996This function returns the address of *plat_drtm_tpm_features_t* structure 997containing PCR usage schema, TPM-based hash, and firmware hash algorithm 998supported by the platform. 999 1000Function : plat_drtm_get_min_size_normal_world_dce() 1001~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1002 1003:: 1004 1005 Argument : void 1006 Return : uint64_t 1007 1008This function returns the size normal-world DCE of the platform. 1009 1010Function : plat_drtm_get_imp_def_dlme_region_size() 1011~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1012 1013:: 1014 1015 Argument : void 1016 Return : uint64_t 1017 1018This function returns the size of implementation defined DLME region 1019of the platform. 1020 1021Function : plat_drtm_get_tcb_hash_table_size() 1022~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1023 1024:: 1025 1026 Argument : void 1027 Return : uint64_t 1028 1029This function returns the size of TCB hash table of the platform. 1030 1031Function : plat_drtm_get_tcb_hash_features() 1032~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1033 1034:: 1035 1036 Argument : void 1037 Return : uint64_t 1038 1039This function returns the Maximum number of TCB hashes recorded by the 1040platform. 1041For more details see section 3.3 Table 6 of `DRTM`_ specification. 1042 1043Function : plat_drtm_validate_ns_region() 1044~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1045 1046:: 1047 1048 Argument : uintptr_t, uintptr_t 1049 Return : int 1050 1051This function validates that given region is within the Non-Secure region 1052of DRAM. This function takes a region start address and size an input 1053arguments, and returns 0 on success and -1 on failure. 1054 1055Function : plat_set_drtm_error() 1056~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1057 1058:: 1059 1060 Argument : uint64_t 1061 Return : int 1062 1063This function writes a 64 bit error code received as input into 1064non-volatile storage and returns 0 on success and -1 on failure. 1065 1066Function : plat_get_drtm_error() 1067~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1068 1069:: 1070 1071 Argument : uint64_t* 1072 Return : int 1073 1074This function reads a 64 bit error code from the non-volatile storage 1075into the received address, and returns 0 on success and -1 on failure. 1076 1077Common mandatory function modifications 1078--------------------------------------- 1079 1080The following functions are mandatory functions which need to be implemented 1081by the platform port. 1082 1083Function : plat_my_core_pos() 1084~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1085 1086:: 1087 1088 Argument : void 1089 Return : unsigned int 1090 1091This function returns the index of the calling CPU which is used as a 1092CPU-specific linear index into blocks of memory (for example while allocating 1093per-CPU stacks). This function will be invoked very early in the 1094initialization sequence which mandates that this function should be 1095implemented in assembly and should not rely on the availability of a C 1096runtime environment. This function can clobber x0 - x8 and must preserve 1097x9 - x29. 1098 1099This function plays a crucial role in the power domain topology framework in 1100PSCI and details of this can be found in 1101:ref:`PSCI Power Domain Tree Structure`. 1102 1103Function : plat_core_pos_by_mpidr() 1104~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1105 1106:: 1107 1108 Argument : u_register_t 1109 Return : int 1110 1111This function validates the ``MPIDR`` of a CPU and converts it to an index, 1112which can be used as a CPU-specific linear index into blocks of memory. In 1113case the ``MPIDR`` is invalid, this function returns -1. This function will only 1114be invoked by BL31 after the power domain topology is initialized and can 1115utilize the C runtime environment. For further details about how TF-A 1116represents the power domain topology and how this relates to the linear CPU 1117index, please refer :ref:`PSCI Power Domain Tree Structure`. 1118 1119Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 1120~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1121 1122:: 1123 1124 Arguments : void **heap_addr, size_t *heap_size 1125 Return : int 1126 1127This function is invoked during Mbed TLS library initialisation to get a heap, 1128by means of a starting address and a size. This heap will then be used 1129internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 1130must be able to provide a heap to it. 1131 1132A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 1133which a heap is statically reserved during compile time inside every image 1134(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 1135the function simply returns the address and size of this "pre-allocated" heap. 1136For a platform to use this default implementation, only a call to the helper 1137from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 1138 1139However, by writting their own implementation, platforms have the potential to 1140optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 1141shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 1142twice. 1143 1144On success the function should return 0 and a negative error code otherwise. 1145 1146Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] 1147~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1148 1149:: 1150 1151 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, 1152 size_t *key_len, unsigned int *flags, const uint8_t *img_id, 1153 size_t img_id_len 1154 Return : int 1155 1156This function provides a symmetric key (either SSK or BSSK depending on 1157fw_enc_status) which is invoked during runtime decryption of encrypted 1158firmware images. `plat/common/plat_bl_common.c` provides a dummy weak 1159implementation for testing purposes which must be overridden by the platform 1160trying to implement a real world firmware encryption use-case. 1161 1162It also allows the platform to pass symmetric key identifier rather than 1163actual symmetric key which is useful in cases where the crypto backend provides 1164secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` 1165flag must be set in ``flags``. 1166 1167In addition to above a platform may also choose to provide an image specific 1168symmetric key/identifier using img_id. 1169 1170On success the function should return 0 and a negative error code otherwise. 1171 1172Note that this API depends on ``DECRYPTION_SUPPORT`` build flag. 1173 1174Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1] 1175~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1176 1177:: 1178 1179 Argument : const struct fwu_metadata *metadata 1180 Return : void 1181 1182This function is mandatory when PSA_FWU_SUPPORT is enabled. 1183It provides a means to retrieve image specification (offset in 1184non-volatile storage and length) of active/updated images using the passed 1185FWU metadata, and update I/O policies of active/updated images using retrieved 1186image specification information. 1187Further I/O layer operations such as I/O open, I/O read, etc. on these 1188images rely on this function call. 1189 1190In Arm platforms, this function is used to set an I/O policy of the FIP image, 1191container of all active/updated secure and non-secure images. 1192 1193Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1] 1194~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1195 1196:: 1197 1198 Argument : unsigned int image_id, uintptr_t *dev_handle, 1199 uintptr_t *image_spec 1200 Return : int 1201 1202This function is mandatory when PSA_FWU_SUPPORT is enabled. It is 1203responsible for setting up the platform I/O policy of the requested metadata 1204image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will 1205be used to load this image from the platform's non-volatile storage. 1206 1207FWU metadata can not be always stored as a raw image in non-volatile storage 1208to define its image specification (offset in non-volatile storage and length) 1209statically in I/O policy. 1210For example, the FWU metadata image is stored as a partition inside the GUID 1211partition table image. Its specification is defined in the partition table 1212that needs to be parsed dynamically. 1213This function provides a means to retrieve such dynamic information to set 1214the I/O policy of the FWU metadata image. 1215Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata 1216image relies on this function call. 1217 1218It returns '0' on success, otherwise a negative error value on error. 1219Alongside, returns device handle and image specification from the I/O policy 1220of the requested FWU metadata image. 1221 1222Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1] 1223~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1224 1225:: 1226 1227 Argument : void 1228 Return : uint32_t 1229 1230This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the 1231means to retrieve the boot index value from the platform. The boot index is the 1232bank from which the platform has booted the firmware images. 1233 1234By default, the platform will read the metadata structure and try to boot from 1235the active bank. If the platform fails to boot from the active bank due to 1236reasons like an Authentication failure, or on crossing a set number of watchdog 1237resets while booting from the active bank, the platform can then switch to boot 1238from a different bank. This function then returns the bank that the platform 1239should boot its images from. 1240 1241Common optional modifications 1242----------------------------- 1243 1244The following are helper functions implemented by the firmware that perform 1245common platform-specific tasks. A platform may choose to override these 1246definitions. 1247 1248Function : plat_set_my_stack() 1249~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1250 1251:: 1252 1253 Argument : void 1254 Return : void 1255 1256This function sets the current stack pointer to the normal memory stack that 1257has been allocated for the current CPU. For BL images that only require a 1258stack for the primary CPU, the UP version of the function is used. The size 1259of the stack allocated to each CPU is specified by the platform defined 1260constant ``PLATFORM_STACK_SIZE``. 1261 1262Common implementations of this function for the UP and MP BL images are 1263provided in ``plat/common/aarch64/platform_up_stack.S`` and 1264``plat/common/aarch64/platform_mp_stack.S`` 1265 1266Function : plat_get_my_stack() 1267~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1268 1269:: 1270 1271 Argument : void 1272 Return : uintptr_t 1273 1274This function returns the base address of the normal memory stack that 1275has been allocated for the current CPU. For BL images that only require a 1276stack for the primary CPU, the UP version of the function is used. The size 1277of the stack allocated to each CPU is specified by the platform defined 1278constant ``PLATFORM_STACK_SIZE``. 1279 1280Common implementations of this function for the UP and MP BL images are 1281provided in ``plat/common/aarch64/platform_up_stack.S`` and 1282``plat/common/aarch64/platform_mp_stack.S`` 1283 1284Function : plat_report_exception() 1285~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1286 1287:: 1288 1289 Argument : unsigned int 1290 Return : void 1291 1292A platform may need to report various information about its status when an 1293exception is taken, for example the current exception level, the CPU security 1294state (secure/non-secure), the exception type, and so on. This function is 1295called in the following circumstances: 1296 1297- In BL1, whenever an exception is taken. 1298- In BL2, whenever an exception is taken. 1299 1300The default implementation doesn't do anything, to avoid making assumptions 1301about the way the platform displays its status information. 1302 1303For AArch64, this function receives the exception type as its argument. 1304Possible values for exceptions types are listed in the 1305``include/common/bl_common.h`` header file. Note that these constants are not 1306related to any architectural exception code; they are just a TF-A convention. 1307 1308For AArch32, this function receives the exception mode as its argument. 1309Possible values for exception modes are listed in the 1310``include/lib/aarch32/arch.h`` header file. 1311 1312Function : plat_reset_handler() 1313~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1314 1315:: 1316 1317 Argument : void 1318 Return : void 1319 1320A platform may need to do additional initialization after reset. This function 1321allows the platform to do the platform specific initializations. Platform 1322specific errata workarounds could also be implemented here. The API should 1323preserve the values of callee saved registers x19 to x29. 1324 1325The default implementation doesn't do anything. If a platform needs to override 1326the default implementation, refer to the :ref:`Firmware Design` for general 1327guidelines. 1328 1329Function : plat_disable_acp() 1330~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1331 1332:: 1333 1334 Argument : void 1335 Return : void 1336 1337This API allows a platform to disable the Accelerator Coherency Port (if 1338present) during a cluster power down sequence. The default weak implementation 1339doesn't do anything. Since this API is called during the power down sequence, 1340it has restrictions for stack usage and it can use the registers x0 - x17 as 1341scratch registers. It should preserve the value in x18 register as it is used 1342by the caller to store the return address. 1343 1344Function : plat_error_handler() 1345~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1346 1347:: 1348 1349 Argument : int 1350 Return : void 1351 1352This API is called when the generic code encounters an error situation from 1353which it cannot continue. It allows the platform to perform error reporting or 1354recovery actions (for example, reset the system). This function must not return. 1355 1356The parameter indicates the type of error using standard codes from ``errno.h``. 1357Possible errors reported by the generic code are: 1358 1359- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 1360 Board Boot is enabled) 1361- ``-ENOENT``: the requested image or certificate could not be found or an IO 1362 error was detected 1363- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 1364 error is usually an indication of an incorrect array size 1365 1366The default implementation simply spins. 1367 1368Function : plat_panic_handler() 1369~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1370 1371:: 1372 1373 Argument : void 1374 Return : void 1375 1376This API is called when the generic code encounters an unexpected error 1377situation from which it cannot recover. This function must not return, 1378and must be implemented in assembly because it may be called before the C 1379environment is initialized. 1380 1381.. note:: 1382 The address from where it was called is stored in x30 (Link Register). 1383 The default implementation simply spins. 1384 1385Function : plat_system_reset() 1386~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1387 1388:: 1389 1390 Argument : void 1391 Return : void 1392 1393This function is used by the platform to resets the system. It can be used 1394in any specific use-case where system needs to be resetted. For example, 1395in case of DRTM implementation this function reset the system after 1396writing the DRTM error code in the non-volatile storage. This function 1397never returns. Failure in reset results in panic. 1398 1399Function : plat_get_bl_image_load_info() 1400~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1401 1402:: 1403 1404 Argument : void 1405 Return : bl_load_info_t * 1406 1407This function returns pointer to the list of images that the platform has 1408populated to load. This function is invoked in BL2 to load the 1409BL3xx images. 1410 1411Function : plat_get_next_bl_params() 1412~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1413 1414:: 1415 1416 Argument : void 1417 Return : bl_params_t * 1418 1419This function returns a pointer to the shared memory that the platform has 1420kept aside to pass TF-A related information that next BL image needs. This 1421function is invoked in BL2 to pass this information to the next BL 1422image. 1423 1424Function : plat_get_stack_protector_canary() 1425~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1426 1427:: 1428 1429 Argument : void 1430 Return : u_register_t 1431 1432This function returns a random value that is used to initialize the canary used 1433when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1434value will weaken the protection as the attacker could easily write the right 1435value as part of the attack most of the time. Therefore, it should return a 1436true random number. 1437 1438.. warning:: 1439 For the protection to be effective, the global data need to be placed at 1440 a lower address than the stack bases. Failure to do so would allow an 1441 attacker to overwrite the canary as part of the stack buffer overflow attack. 1442 1443Function : plat_flush_next_bl_params() 1444~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1445 1446:: 1447 1448 Argument : void 1449 Return : void 1450 1451This function flushes to main memory all the image params that are passed to 1452next image. This function is invoked in BL2 to flush this information 1453to the next BL image. 1454 1455Function : plat_log_get_prefix() 1456~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1457 1458:: 1459 1460 Argument : unsigned int 1461 Return : const char * 1462 1463This function defines the prefix string corresponding to the `log_level` to be 1464prepended to all the log output from TF-A. The `log_level` (argument) will 1465correspond to one of the standard log levels defined in debug.h. The platform 1466can override the common implementation to define a different prefix string for 1467the log output. The implementation should be robust to future changes that 1468increase the number of log levels. 1469 1470Function : plat_get_soc_version() 1471~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1472 1473:: 1474 1475 Argument : void 1476 Return : int32_t 1477 1478This function returns soc version which mainly consist of below fields 1479 1480:: 1481 1482 soc_version[30:24] = JEP-106 continuation code for the SiP 1483 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 1484 soc_version[15:0] = Implementation defined SoC ID 1485 1486Function : plat_get_soc_revision() 1487~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1488 1489:: 1490 1491 Argument : void 1492 Return : int32_t 1493 1494This function returns soc revision in below format 1495 1496:: 1497 1498 soc_revision[0:30] = SOC revision of specific SOC 1499 1500Function : plat_is_smccc_feature_available() 1501~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1502 1503:: 1504 1505 Argument : u_register_t 1506 Return : int32_t 1507 1508This function returns SMC_ARCH_CALL_SUCCESS if the platform supports 1509the SMCCC function specified in the argument; otherwise returns 1510SMC_ARCH_CALL_NOT_SUPPORTED. 1511 1512Function : plat_can_cmo() 1513~~~~~~~~~~~~~~~~~~~~~~~~~ 1514 1515:: 1516 1517 Argument : void 1518 Return : uint64_t 1519 1520When CONDITIONAL_CMO flag is enabled: 1521 1522- This function indicates whether cache management operations should be 1523 performed. It returns 0 if CMOs should be skipped and non-zero 1524 otherwise. 1525- The function must not clobber x1, x2 and x3. It's also not safe to rely on 1526 stack. Otherwise obey AAPCS. 1527 1528Modifications specific to a Boot Loader stage 1529--------------------------------------------- 1530 1531Boot Loader Stage 1 (BL1) 1532------------------------- 1533 1534BL1 implements the reset vector where execution starts from after a cold or 1535warm boot. For each CPU, BL1 is responsible for the following tasks: 1536 1537#. Handling the reset as described in section 2.2 1538 1539#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1540 only this CPU executes the remaining BL1 code, including loading and passing 1541 control to the BL2 stage. 1542 1543#. Identifying and starting the Firmware Update process (if required). 1544 1545#. Loading the BL2 image from non-volatile storage into secure memory at the 1546 address specified by the platform defined constant ``BL2_BASE``. 1547 1548#. Populating a ``meminfo`` structure with the following information in memory, 1549 accessible by BL2 immediately upon entry. 1550 1551 :: 1552 1553 meminfo.total_base = Base address of secure RAM visible to BL2 1554 meminfo.total_size = Size of secure RAM visible to BL2 1555 1556 By default, BL1 places this ``meminfo`` structure at the end of secure 1557 memory visible to BL2. 1558 1559 It is possible for the platform to decide where it wants to place the 1560 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1561 BL2 by overriding the weak default implementation of 1562 ``bl1_plat_handle_post_image_load`` API. 1563 1564The following functions need to be implemented by the platform port to enable 1565BL1 to perform the above tasks. 1566 1567Function : bl1_early_platform_setup() [mandatory] 1568~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1569 1570:: 1571 1572 Argument : void 1573 Return : void 1574 1575This function executes with the MMU and data caches disabled. It is only called 1576by the primary CPU. 1577 1578On Arm standard platforms, this function: 1579 1580- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1581 1582- Initializes a UART (PL011 console), which enables access to the ``printf`` 1583 family of functions in BL1. 1584 1585- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1586 the CCI slave interface corresponding to the cluster that includes the 1587 primary CPU. 1588 1589Function : bl1_plat_arch_setup() [mandatory] 1590~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1591 1592:: 1593 1594 Argument : void 1595 Return : void 1596 1597This function performs any platform-specific and architectural setup that the 1598platform requires. Platform-specific setup might include configuration of 1599memory controllers and the interconnect. 1600 1601In Arm standard platforms, this function enables the MMU. 1602 1603This function helps fulfill requirement 2 above. 1604 1605Function : bl1_platform_setup() [mandatory] 1606~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1607 1608:: 1609 1610 Argument : void 1611 Return : void 1612 1613This function executes with the MMU and data caches enabled. It is responsible 1614for performing any remaining platform-specific setup that can occur after the 1615MMU and data cache have been enabled. 1616 1617if support for multiple boot sources is required, it initializes the boot 1618sequence used by plat_try_next_boot_source(). 1619 1620In Arm standard platforms, this function initializes the storage abstraction 1621layer used to load the next bootloader image. 1622 1623This function helps fulfill requirement 4 above. 1624 1625Function : bl1_plat_sec_mem_layout() [mandatory] 1626~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1627 1628:: 1629 1630 Argument : void 1631 Return : meminfo * 1632 1633This function should only be called on the cold boot path. It executes with the 1634MMU and data caches enabled. The pointer returned by this function must point to 1635a ``meminfo`` structure containing the extents and availability of secure RAM for 1636the BL1 stage. 1637 1638:: 1639 1640 meminfo.total_base = Base address of secure RAM visible to BL1 1641 meminfo.total_size = Size of secure RAM visible to BL1 1642 1643This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1644populates a similar structure to tell BL2 the extents of memory available for 1645its own use. 1646 1647This function helps fulfill requirements 4 and 5 above. 1648 1649Function : bl1_plat_prepare_exit() [optional] 1650~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1651 1652:: 1653 1654 Argument : entry_point_info_t * 1655 Return : void 1656 1657This function is called prior to exiting BL1 in response to the 1658``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1659platform specific clean up or bookkeeping operations before transferring 1660control to the next image. It receives the address of the ``entry_point_info_t`` 1661structure passed from BL2. This function runs with MMU disabled. 1662 1663Function : bl1_plat_set_ep_info() [optional] 1664~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1665 1666:: 1667 1668 Argument : unsigned int image_id, entry_point_info_t *ep_info 1669 Return : void 1670 1671This function allows platforms to override ``ep_info`` for the given ``image_id``. 1672 1673The default implementation just returns. 1674 1675Function : bl1_plat_get_next_image_id() [optional] 1676~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1677 1678:: 1679 1680 Argument : void 1681 Return : unsigned int 1682 1683This and the following function must be overridden to enable the FWU feature. 1684 1685BL1 calls this function after platform setup to identify the next image to be 1686loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1687with the normal boot sequence, which loads and executes BL2. If the platform 1688returns a different image id, BL1 assumes that Firmware Update is required. 1689 1690The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1691platforms override this function to detect if firmware update is required, and 1692if so, return the first image in the firmware update process. 1693 1694Function : bl1_plat_get_image_desc() [optional] 1695~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1696 1697:: 1698 1699 Argument : unsigned int image_id 1700 Return : image_desc_t * 1701 1702BL1 calls this function to get the image descriptor information ``image_desc_t`` 1703for the provided ``image_id`` from the platform. 1704 1705The default implementation always returns a common BL2 image descriptor. Arm 1706standard platforms return an image descriptor corresponding to BL2 or one of 1707the firmware update images defined in the Trusted Board Boot Requirements 1708specification. 1709 1710Function : bl1_plat_handle_pre_image_load() [optional] 1711~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1712 1713:: 1714 1715 Argument : unsigned int image_id 1716 Return : int 1717 1718This function can be used by the platforms to update/use image information 1719corresponding to ``image_id``. This function is invoked in BL1, both in cold 1720boot and FWU code path, before loading the image. 1721 1722Function : bl1_plat_handle_post_image_load() [optional] 1723~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1724 1725:: 1726 1727 Argument : unsigned int image_id 1728 Return : int 1729 1730This function can be used by the platforms to update/use image information 1731corresponding to ``image_id``. This function is invoked in BL1, both in cold 1732boot and FWU code path, after loading and authenticating the image. 1733 1734The default weak implementation of this function calculates the amount of 1735Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1736structure at the beginning of this free memory and populates it. The address 1737of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1738information to BL2. 1739 1740Function : bl1_plat_fwu_done() [optional] 1741~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1742 1743:: 1744 1745 Argument : unsigned int image_id, uintptr_t image_src, 1746 unsigned int image_size 1747 Return : void 1748 1749BL1 calls this function when the FWU process is complete. It must not return. 1750The platform may override this function to take platform specific action, for 1751example to initiate the normal boot flow. 1752 1753The default implementation spins forever. 1754 1755Function : bl1_plat_mem_check() [mandatory] 1756~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1757 1758:: 1759 1760 Argument : uintptr_t mem_base, unsigned int mem_size, 1761 unsigned int flags 1762 Return : int 1763 1764BL1 calls this function while handling FWU related SMCs, more specifically when 1765copying or authenticating an image. Its responsibility is to ensure that the 1766region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1767that this memory corresponds to either a secure or non-secure memory region as 1768indicated by the security state of the ``flags`` argument. 1769 1770This function can safely assume that the value resulting from the addition of 1771``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1772overflow. 1773 1774This function must return 0 on success, a non-null error code otherwise. 1775 1776The default implementation of this function asserts therefore platforms must 1777override it when using the FWU feature. 1778 1779Boot Loader Stage 2 (BL2) 1780------------------------- 1781 1782The BL2 stage is executed only by the primary CPU, which is determined in BL1 1783using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1784``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1785``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1786non-volatile storage to secure/non-secure RAM. After all the images are loaded 1787then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1788images to be passed to the next BL image. 1789 1790The following functions must be implemented by the platform port to enable BL2 1791to perform the above tasks. 1792 1793Function : bl2_early_platform_setup2() [mandatory] 1794~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1795 1796:: 1797 1798 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1799 Return : void 1800 1801This function executes with the MMU and data caches disabled. It is only called 1802by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1803are platform specific. 1804 1805On Arm standard platforms, the arguments received are : 1806 1807 arg0 - Points to load address of FW_CONFIG 1808 1809 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1810 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1811 1812On Arm standard platforms, this function also: 1813 1814- Initializes a UART (PL011 console), which enables access to the ``printf`` 1815 family of functions in BL2. 1816 1817- Initializes the storage abstraction layer used to load further bootloader 1818 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1819 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1820 1821Function : bl2_plat_arch_setup() [mandatory] 1822~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1823 1824:: 1825 1826 Argument : void 1827 Return : void 1828 1829This function executes with the MMU and data caches disabled. It is only called 1830by the primary CPU. 1831 1832The purpose of this function is to perform any architectural initialization 1833that varies across platforms. 1834 1835On Arm standard platforms, this function enables the MMU. 1836 1837Function : bl2_platform_setup() [mandatory] 1838~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1839 1840:: 1841 1842 Argument : void 1843 Return : void 1844 1845This function may execute with the MMU and data caches enabled if the platform 1846port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1847called by the primary CPU. 1848 1849The purpose of this function is to perform any platform initialization 1850specific to BL2. 1851 1852In Arm standard platforms, this function performs security setup, including 1853configuration of the TrustZone controller to allow non-secure masters access 1854to most of DRAM. Part of DRAM is reserved for secure world use. 1855 1856Function : bl2_plat_handle_pre_image_load() [optional] 1857~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1858 1859:: 1860 1861 Argument : unsigned int 1862 Return : int 1863 1864This function can be used by the platforms to update/use image information 1865for given ``image_id``. This function is currently invoked in BL2 before 1866loading each image. 1867 1868Function : bl2_plat_handle_post_image_load() [optional] 1869~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1870 1871:: 1872 1873 Argument : unsigned int 1874 Return : int 1875 1876This function can be used by the platforms to update/use image information 1877for given ``image_id``. This function is currently invoked in BL2 after 1878loading each image. 1879 1880Function : bl2_plat_preload_setup [optional] 1881~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1882 1883:: 1884 1885 Argument : void 1886 Return : void 1887 1888This optional function performs any BL2 platform initialization 1889required before image loading, that is not done later in 1890bl2_platform_setup(). Specifically, if support for multiple 1891boot sources is required, it initializes the boot sequence used by 1892plat_try_next_boot_source(). 1893 1894Function : plat_try_next_boot_source() [optional] 1895~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1896 1897:: 1898 1899 Argument : void 1900 Return : int 1901 1902This optional function passes to the next boot source in the redundancy 1903sequence. 1904 1905This function moves the current boot redundancy source to the next 1906element in the boot sequence. If there are no more boot sources then it 1907must return 0, otherwise it must return 1. The default implementation 1908of this always returns 0. 1909 1910Boot Loader Stage 2 (BL2) at EL3 1911-------------------------------- 1912 1913When the platform has a non-TF-A Boot ROM it is desirable to jump 1914directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1915execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` 1916document for more information. 1917 1918All mandatory functions of BL2 must be implemented, except the functions 1919bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 1920their work is done now by bl2_el3_early_platform_setup and 1921bl2_el3_plat_arch_setup. These functions should generally implement 1922the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 1923 1924 1925Function : bl2_el3_early_platform_setup() [mandatory] 1926~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1927 1928:: 1929 1930 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1931 Return : void 1932 1933This function executes with the MMU and data caches disabled. It is only called 1934by the primary CPU. This function receives four parameters which can be used 1935by the platform to pass any needed information from the Boot ROM to BL2. 1936 1937On Arm standard platforms, this function does the following: 1938 1939- Initializes a UART (PL011 console), which enables access to the ``printf`` 1940 family of functions in BL2. 1941 1942- Initializes the storage abstraction layer used to load further bootloader 1943 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1944 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1945 1946- Initializes the private variables that define the memory layout used. 1947 1948Function : bl2_el3_plat_arch_setup() [mandatory] 1949~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1950 1951:: 1952 1953 Argument : void 1954 Return : void 1955 1956This function executes with the MMU and data caches disabled. It is only called 1957by the primary CPU. 1958 1959The purpose of this function is to perform any architectural initialization 1960that varies across platforms. 1961 1962On Arm standard platforms, this function enables the MMU. 1963 1964Function : bl2_el3_plat_prepare_exit() [optional] 1965~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1966 1967:: 1968 1969 Argument : void 1970 Return : void 1971 1972This function is called prior to exiting BL2 and run the next image. 1973It should be used to perform platform specific clean up or bookkeeping 1974operations before transferring control to the next image. This function 1975runs with MMU disabled. 1976 1977FWU Boot Loader Stage 2 (BL2U) 1978------------------------------ 1979 1980The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1981process and is executed only by the primary CPU. BL1 passes control to BL2U at 1982``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1983 1984#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 1985 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 1986 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 1987 should be copied from. Subsequent handling of the SCP_BL2U image is 1988 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1989 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1990 1991#. Any platform specific setup required to perform the FWU process. For 1992 example, Arm standard platforms initialize the TZC controller so that the 1993 normal world can access DDR memory. 1994 1995The following functions must be implemented by the platform port to enable 1996BL2U to perform the tasks mentioned above. 1997 1998Function : bl2u_early_platform_setup() [mandatory] 1999~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2000 2001:: 2002 2003 Argument : meminfo *mem_info, void *plat_info 2004 Return : void 2005 2006This function executes with the MMU and data caches disabled. It is only 2007called by the primary CPU. The arguments to this function is the address 2008of the ``meminfo`` structure and platform specific info provided by BL1. 2009 2010The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 2011private storage as the original memory may be subsequently overwritten by BL2U. 2012 2013On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 2014to extract SCP_BL2U image information, which is then copied into a private 2015variable. 2016 2017Function : bl2u_plat_arch_setup() [mandatory] 2018~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2019 2020:: 2021 2022 Argument : void 2023 Return : void 2024 2025This function executes with the MMU and data caches disabled. It is only 2026called by the primary CPU. 2027 2028The purpose of this function is to perform any architectural initialization 2029that varies across platforms, for example enabling the MMU (since the memory 2030map differs across platforms). 2031 2032Function : bl2u_platform_setup() [mandatory] 2033~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2034 2035:: 2036 2037 Argument : void 2038 Return : void 2039 2040This function may execute with the MMU and data caches enabled if the platform 2041port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 2042called by the primary CPU. 2043 2044The purpose of this function is to perform any platform initialization 2045specific to BL2U. 2046 2047In Arm standard platforms, this function performs security setup, including 2048configuration of the TrustZone controller to allow non-secure masters access 2049to most of DRAM. Part of DRAM is reserved for secure world use. 2050 2051Function : bl2u_plat_handle_scp_bl2u() [optional] 2052~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2053 2054:: 2055 2056 Argument : void 2057 Return : int 2058 2059This function is used to perform any platform-specific actions required to 2060handle the SCP firmware. Typically it transfers the image into SCP memory using 2061a platform-specific protocol and waits until SCP executes it and signals to the 2062Application Processor (AP) for BL2U execution to continue. 2063 2064This function returns 0 on success, a negative error code otherwise. 2065This function is included if SCP_BL2U_BASE is defined. 2066 2067Boot Loader Stage 3-1 (BL31) 2068---------------------------- 2069 2070During cold boot, the BL31 stage is executed only by the primary CPU. This is 2071determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 2072control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 2073CPUs. BL31 executes at EL3 and is responsible for: 2074 2075#. Re-initializing all architectural and platform state. Although BL1 performs 2076 some of this initialization, BL31 remains resident in EL3 and must ensure 2077 that EL3 architectural and platform state is completely initialized. It 2078 should make no assumptions about the system state when it receives control. 2079 2080#. Passing control to a normal world BL image, pre-loaded at a platform- 2081 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 2082 populated by BL2 in memory to do this. 2083 2084#. Providing runtime firmware services. Currently, BL31 only implements a 2085 subset of the Power State Coordination Interface (PSCI) API as a runtime 2086 service. See :ref:`psci_in_bl31` below for details of porting the PSCI 2087 implementation. 2088 2089#. Optionally passing control to the BL32 image, pre-loaded at a platform- 2090 specific address by BL2. BL31 exports a set of APIs that allow runtime 2091 services to specify the security state in which the next image should be 2092 executed and run the corresponding image. On ARM platforms, BL31 uses the 2093 ``bl_params`` list populated by BL2 in memory to do this. 2094 2095If BL31 is a reset vector, It also needs to handle the reset as specified in 2096section 2.2 before the tasks described above. 2097 2098The following functions must be implemented by the platform port to enable BL31 2099to perform the above tasks. 2100 2101Function : bl31_early_platform_setup2() [mandatory] 2102~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2103 2104:: 2105 2106 Argument : u_register_t, u_register_t, u_register_t, u_register_t 2107 Return : void 2108 2109This function executes with the MMU and data caches disabled. It is only called 2110by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 2111platform specific. 2112 2113In Arm standard platforms, the arguments received are : 2114 2115 arg0 - The pointer to the head of `bl_params_t` list 2116 which is list of executable images following BL31, 2117 2118 arg1 - Points to load address of SOC_FW_CONFIG if present 2119 except in case of Arm FVP and Juno platform. 2120 2121 In case of Arm FVP and Juno platform, points to load address 2122 of FW_CONFIG. 2123 2124 arg2 - Points to load address of HW_CONFIG if present 2125 2126 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 2127 used in release builds. 2128 2129The function runs through the `bl_param_t` list and extracts the entry point 2130information for BL32 and BL33. It also performs the following: 2131 2132- Initialize a UART (PL011 console), which enables access to the ``printf`` 2133 family of functions in BL31. 2134 2135- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 2136 CCI slave interface corresponding to the cluster that includes the primary 2137 CPU. 2138 2139Function : bl31_plat_arch_setup() [mandatory] 2140~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2141 2142:: 2143 2144 Argument : void 2145 Return : void 2146 2147This function executes with the MMU and data caches disabled. It is only called 2148by the primary CPU. 2149 2150The purpose of this function is to perform any architectural initialization 2151that varies across platforms. 2152 2153On Arm standard platforms, this function enables the MMU. 2154 2155Function : bl31_platform_setup() [mandatory] 2156~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2157 2158:: 2159 2160 Argument : void 2161 Return : void 2162 2163This function may execute with the MMU and data caches enabled if the platform 2164port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 2165called by the primary CPU. 2166 2167The purpose of this function is to complete platform initialization so that both 2168BL31 runtime services and normal world software can function correctly. 2169 2170On Arm standard platforms, this function does the following: 2171 2172- Initialize the generic interrupt controller. 2173 2174 Depending on the GIC driver selected by the platform, the appropriate GICv2 2175 or GICv3 initialization will be done, which mainly consists of: 2176 2177 - Enable secure interrupts in the GIC CPU interface. 2178 - Disable the legacy interrupt bypass mechanism. 2179 - Configure the priority mask register to allow interrupts of all priorities 2180 to be signaled to the CPU interface. 2181 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 2182 - Target all secure SPIs to CPU0. 2183 - Enable these secure interrupts in the GIC distributor. 2184 - Configure all other interrupts as non-secure. 2185 - Enable signaling of secure interrupts in the GIC distributor. 2186 2187- Enable system-level implementation of the generic timer counter through the 2188 memory mapped interface. 2189 2190- Grant access to the system counter timer module 2191 2192- Initialize the power controller device. 2193 2194 In particular, initialise the locks that prevent concurrent accesses to the 2195 power controller device. 2196 2197Function : bl31_plat_runtime_setup() [optional] 2198~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2199 2200:: 2201 2202 Argument : void 2203 Return : void 2204 2205The purpose of this function is allow the platform to perform any BL31 runtime 2206setup just prior to BL31 exit during cold boot. The default weak 2207implementation of this function will invoke ``console_switch_state()`` to switch 2208console output to consoles marked for use in the ``runtime`` state. 2209 2210Function : bl31_plat_get_next_image_ep_info() [mandatory] 2211~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2212 2213:: 2214 2215 Argument : uint32_t 2216 Return : entry_point_info * 2217 2218This function may execute with the MMU and data caches enabled if the platform 2219port does the necessary initializations in ``bl31_plat_arch_setup()``. 2220 2221This function is called by ``bl31_main()`` to retrieve information provided by 2222BL2 for the next image in the security state specified by the argument. BL31 2223uses this information to pass control to that image in the specified security 2224state. This function must return a pointer to the ``entry_point_info`` structure 2225(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2226should return NULL otherwise. 2227 2228Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1] 2229~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2230 2231:: 2232 2233 Argument : uintptr_t, size_t *, uintptr_t, size_t 2234 Return : int 2235 2236This function returns the Platform attestation token. 2237 2238The parameters of the function are: 2239 2240 arg0 - A pointer to the buffer where the Platform token should be copied by 2241 this function. The buffer must be big enough to hold the Platform 2242 token. 2243 2244 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2245 function returns the platform token length in this parameter. 2246 2247 arg2 - A pointer to the buffer where the challenge object is stored. 2248 2249 arg3 - The length of the challenge object in bytes. Possible values are 32, 2250 48 and 64. 2251 2252The function returns 0 on success, -EINVAL on failure. 2253 2254Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] 2255~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2256 2257:: 2258 2259 Argument : uintptr_t, size_t *, unsigned int 2260 Return : int 2261 2262This function returns the delegated realm attestation key which will be used to 2263sign Realm attestation token. The API currently only supports P-384 ECC curve 2264key. 2265 2266The parameters of the function are: 2267 2268 arg0 - A pointer to the buffer where the attestation key should be copied 2269 by this function. The buffer must be big enough to hold the 2270 attestation key. 2271 2272 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2273 function returns the attestation key length in this parameter. 2274 2275 arg2 - The type of the elliptic curve to which the requested attestation key 2276 belongs. 2277 2278The function returns 0 on success, -EINVAL on failure. 2279 2280Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1] 2281~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2282 2283:: 2284 2285 Argument : uintptr_t * 2286 Return : size_t 2287 2288This function returns the size of the shared area between EL3 and RMM (or 0 on 2289failure). A pointer to the shared area (or a NULL pointer on failure) is stored 2290in the pointer passed as argument. 2291 2292Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1] 2293~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2294 2295:: 2296 2297 Arguments : rmm_manifest_t *manifest 2298 Return : int 2299 2300When ENABLE_RME is enabled, this function populates a boot manifest for the 2301RMM image and stores it in the area specified by manifest. 2302 2303When ENABLE_RME is disabled, this function is not used. 2304 2305Function : bl31_plat_enable_mmu [optional] 2306~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2307 2308:: 2309 2310 Argument : uint32_t 2311 Return : void 2312 2313This function enables the MMU. The boot code calls this function with MMU and 2314caches disabled. This function should program necessary registers to enable 2315translation, and upon return, the MMU on the calling PE must be enabled. 2316 2317The function must honor flags passed in the first argument. These flags are 2318defined by the translation library, and can be found in the file 2319``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2320 2321On DynamIQ systems, this function must not use stack while enabling MMU, which 2322is how the function in xlat table library version 2 is implemented. 2323 2324Function : plat_init_apkey [optional] 2325~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2326 2327:: 2328 2329 Argument : void 2330 Return : uint128_t 2331 2332This function returns the 128-bit value which can be used to program ARMv8.3 2333pointer authentication keys. 2334 2335The value should be obtained from a reliable source of randomness. 2336 2337This function is only needed if ARMv8.3 pointer authentication is used in the 2338Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero. 2339 2340Function : plat_get_syscnt_freq2() [mandatory] 2341~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2342 2343:: 2344 2345 Argument : void 2346 Return : unsigned int 2347 2348This function is used by the architecture setup code to retrieve the counter 2349frequency for the CPU's generic timer. This value will be programmed into the 2350``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2351of the system counter, which is retrieved from the first entry in the frequency 2352modes table. 2353 2354#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 2355~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2356 2357When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2358bytes) aligned to the cache line boundary that should be allocated per-cpu to 2359accommodate all the bakery locks. 2360 2361If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2362calculates the size of the ``.bakery_lock`` input section, aligns it to the 2363nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2364and stores the result in a linker symbol. This constant prevents a platform 2365from relying on the linker and provide a more efficient mechanism for 2366accessing per-cpu bakery lock information. 2367 2368If this constant is defined and its value is not equal to the value 2369calculated by the linker then a link time assertion is raised. A compile time 2370assertion is raised if the value of the constant is not aligned to the cache 2371line boundary. 2372 2373.. _porting_guide_sdei_requirements: 2374 2375SDEI porting requirements 2376~~~~~~~~~~~~~~~~~~~~~~~~~ 2377 2378The |SDEI| dispatcher requires the platform to provide the following macros 2379and functions, of which some are optional, and some others mandatory. 2380 2381Macros 2382...... 2383 2384Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2385^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2386 2387This macro must be defined to the EL3 exception priority level associated with 2388Normal |SDEI| events on the platform. This must have a higher value 2389(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2390 2391Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2392^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2393 2394This macro must be defined to the EL3 exception priority level associated with 2395Critical |SDEI| events on the platform. This must have a lower value 2396(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2397 2398**Note**: |SDEI| exception priorities must be the lowest among Secure 2399priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must 2400be higher than Normal |SDEI| priority. 2401 2402Functions 2403......... 2404 2405Function: int plat_sdei_validate_entry_point() [optional] 2406^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2407 2408:: 2409 2410 Argument: uintptr_t ep, unsigned int client_mode 2411 Return: int 2412 2413This function validates the entry point address of the event handler provided by 2414the client for both event registration and *Complete and Resume* |SDEI| calls. 2415The function ensures that the address is valid in the client translation regime. 2416 2417The second argument is the exception level that the client is executing in. It 2418can be Non-Secure EL1 or Non-Secure EL2. 2419 2420The function must return ``0`` for successful validation, or ``-1`` upon failure. 2421 2422The default implementation always returns ``0``. On Arm platforms, this function 2423translates the entry point address within the client translation regime and 2424further ensures that the resulting physical address is located in Non-secure 2425DRAM. 2426 2427Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2428^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2429 2430:: 2431 2432 Argument: uint64_t 2433 Argument: unsigned int 2434 Return: void 2435 2436|SDEI| specification requires that a PE comes out of reset with the events 2437masked. The client therefore is expected to call ``PE_UNMASK`` to unmask 2438|SDEI| events on the PE. No |SDEI| events can be dispatched until such 2439time. 2440 2441Should a PE receive an interrupt that was bound to an |SDEI| event while the 2442events are masked on the PE, the dispatcher implementation invokes the function 2443``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2444interrupt and the interrupt ID are passed as parameters. 2445 2446The default implementation only prints out a warning message. 2447 2448.. _porting_guide_trng_requirements: 2449 2450TRNG porting requirements 2451~~~~~~~~~~~~~~~~~~~~~~~~~ 2452 2453The |TRNG| backend requires the platform to provide the following values 2454and mandatory functions. 2455 2456Values 2457...... 2458 2459value: uuid_t plat_trng_uuid [mandatory] 2460^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2461 2462This value must be defined to the UUID of the TRNG backend that is specific to 2463the hardware after ``plat_entropy_setup`` function is called. This value must 2464conform to the SMCCC calling convention; The most significant 32 bits of the 2465UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in 2466w0 indicates failure to get a TRNG source. 2467 2468Functions 2469......... 2470 2471Function: void plat_entropy_setup(void) [mandatory] 2472^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2473 2474:: 2475 2476 Argument: none 2477 Return: none 2478 2479This function is expected to do platform-specific initialization of any TRNG 2480hardware. This may include generating a UUID from a hardware-specific seed. 2481 2482Function: bool plat_get_entropy(uint64_t \*out) [mandatory] 2483^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2484 2485:: 2486 2487 Argument: uint64_t * 2488 Return: bool 2489 Out : when the return value is true, the entropy has been written into the 2490 storage pointed to 2491 2492This function writes entropy into storage provided by the caller. If no entropy 2493is available, it must return false and the storage must not be written. 2494 2495.. _psci_in_bl31: 2496 2497Power State Coordination Interface (in BL31) 2498-------------------------------------------- 2499 2500The TF-A implementation of the PSCI API is based around the concept of a 2501*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2502share some state on which power management operations can be performed as 2503specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2504a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2505*power domains* are arranged in a hierarchical tree structure and each 2506*power domain* can be identified in a system by the cpu index of any CPU that 2507is part of that domain and a *power domain level*. A processing element (for 2508example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2509logical grouping of CPUs that share some state, then level 1 is that group of 2510CPUs (for example, a cluster), and level 2 is a group of clusters (for 2511example, the system). More details on the power domain topology and its 2512organization can be found in :ref:`PSCI Power Domain Tree Structure`. 2513 2514BL31's platform initialization code exports a pointer to the platform-specific 2515power management operations required for the PSCI implementation to function 2516correctly. This information is populated in the ``plat_psci_ops`` structure. The 2517PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2518power management operations on the power domains. For example, the target 2519CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2520handler (if present) is called for the CPU power domain. 2521 2522The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2523describe composite power states specific to a platform. The PSCI implementation 2524defines a generic representation of the power-state parameter, which is an 2525array of local power states where each index corresponds to a power domain 2526level. Each entry contains the local power state the power domain at that power 2527level could enter. It depends on the ``validate_power_state()`` handler to 2528convert the power-state parameter (possibly encoding a composite power state) 2529passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2530 2531The following functions form part of platform port of PSCI functionality. 2532 2533Function : plat_psci_stat_accounting_start() [optional] 2534~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2535 2536:: 2537 2538 Argument : const psci_power_state_t * 2539 Return : void 2540 2541This is an optional hook that platforms can implement for residency statistics 2542accounting before entering a low power state. The ``pwr_domain_state`` field of 2543``state_info`` (first argument) can be inspected if stat accounting is done 2544differently at CPU level versus higher levels. As an example, if the element at 2545index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2546state, special hardware logic may be programmed in order to keep track of the 2547residency statistics. For higher levels (array indices > 0), the residency 2548statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2549default implementation will use PMF to capture timestamps. 2550 2551Function : plat_psci_stat_accounting_stop() [optional] 2552~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2553 2554:: 2555 2556 Argument : const psci_power_state_t * 2557 Return : void 2558 2559This is an optional hook that platforms can implement for residency statistics 2560accounting after exiting from a low power state. The ``pwr_domain_state`` field 2561of ``state_info`` (first argument) can be inspected if stat accounting is done 2562differently at CPU level versus higher levels. As an example, if the element at 2563index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2564state, special hardware logic may be programmed in order to keep track of the 2565residency statistics. For higher levels (array indices > 0), the residency 2566statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2567default implementation will use PMF to capture timestamps. 2568 2569Function : plat_psci_stat_get_residency() [optional] 2570~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2571 2572:: 2573 2574 Argument : unsigned int, const psci_power_state_t *, unsigned int 2575 Return : u_register_t 2576 2577This is an optional interface that is is invoked after resuming from a low power 2578state and provides the time spent resident in that low power state by the power 2579domain at a particular power domain level. When a CPU wakes up from suspend, 2580all its parent power domain levels are also woken up. The generic PSCI code 2581invokes this function for each parent power domain that is resumed and it 2582identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2583argument) describes the low power state that the power domain has resumed from. 2584The current CPU is the first CPU in the power domain to resume from the low 2585power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2586CPU in the power domain to suspend and may be needed to calculate the residency 2587for that power domain. 2588 2589Function : plat_get_target_pwr_state() [optional] 2590~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2591 2592:: 2593 2594 Argument : unsigned int, const plat_local_state_t *, unsigned int 2595 Return : plat_local_state_t 2596 2597The PSCI generic code uses this function to let the platform participate in 2598state coordination during a power management operation. The function is passed 2599a pointer to an array of platform specific local power state ``states`` (second 2600argument) which contains the requested power state for each CPU at a particular 2601power domain level ``lvl`` (first argument) within the power domain. The function 2602is expected to traverse this array of upto ``ncpus`` (third argument) and return 2603a coordinated target power state by the comparing all the requested power 2604states. The target power state should not be deeper than any of the requested 2605power states. 2606 2607A weak definition of this API is provided by default wherein it assumes 2608that the platform assigns a local state value in order of increasing depth 2609of the power state i.e. for two power states X & Y, if X < Y 2610then X represents a shallower power state than Y. As a result, the 2611coordinated target local power state for a power domain will be the minimum 2612of the requested local power state values. 2613 2614Function : plat_get_power_domain_tree_desc() [mandatory] 2615~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2616 2617:: 2618 2619 Argument : void 2620 Return : const unsigned char * 2621 2622This function returns a pointer to the byte array containing the power domain 2623topology tree description. The format and method to construct this array are 2624described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI 2625initialization code requires this array to be described by the platform, either 2626statically or dynamically, to initialize the power domain topology tree. In case 2627the array is populated dynamically, then plat_core_pos_by_mpidr() and 2628plat_my_core_pos() should also be implemented suitably so that the topology tree 2629description matches the CPU indices returned by these APIs. These APIs together 2630form the platform interface for the PSCI topology framework. 2631 2632Function : plat_setup_psci_ops() [mandatory] 2633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2634 2635:: 2636 2637 Argument : uintptr_t, const plat_psci_ops ** 2638 Return : int 2639 2640This function may execute with the MMU and data caches enabled if the platform 2641port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2642called by the primary CPU. 2643 2644This function is called by PSCI initialization code. Its purpose is to let 2645the platform layer know about the warm boot entrypoint through the 2646``sec_entrypoint`` (first argument) and to export handler routines for 2647platform-specific psci power management actions by populating the passed 2648pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2649 2650A description of each member of this structure is given below. Please refer to 2651the Arm FVP specific implementation of these handlers in 2652``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the 2653platform wants to support, the associated operation or operations in this 2654structure must be provided and implemented (Refer section 4 of 2655:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI 2656function in a platform port, the operation should be removed from this 2657structure instead of providing an empty implementation. 2658 2659plat_psci_ops.cpu_standby() 2660........................... 2661 2662Perform the platform-specific actions to enter the standby state for a cpu 2663indicated by the passed argument. This provides a fast path for CPU standby 2664wherein overheads of PSCI state management and lock acquisition is avoided. 2665For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2666the suspend state type specified in the ``power-state`` parameter should be 2667STANDBY and the target power domain level specified should be the CPU. The 2668handler should put the CPU into a low power retention state (usually by 2669issuing a wfi instruction) and ensure that it can be woken up from that 2670state by a normal interrupt. The generic code expects the handler to succeed. 2671 2672plat_psci_ops.pwr_domain_on() 2673............................. 2674 2675Perform the platform specific actions to power on a CPU, specified 2676by the ``MPIDR`` (first argument). The generic code expects the platform to 2677return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 2678 2679plat_psci_ops.pwr_domain_off_early() [optional] 2680............................................... 2681 2682This optional function performs the platform specific actions to check if 2683powering off the calling CPU and its higher parent power domain levels as 2684indicated by the ``target_state`` (first argument) is possible or allowed. 2685 2686The ``target_state`` encodes the platform coordinated target local power states 2687for the CPU power domain and its parent power domain levels. 2688 2689For this handler, the local power state for the CPU power domain will be a 2690power down state where as it could be either power down, retention or run state 2691for the higher power domain levels depending on the result of state 2692coordination. The generic code expects PSCI_E_DENIED return code if the 2693platform thinks that CPU_OFF should not proceed on the calling CPU. 2694 2695plat_psci_ops.pwr_domain_off() 2696.............................. 2697 2698Perform the platform specific actions to prepare to power off the calling CPU 2699and its higher parent power domain levels as indicated by the ``target_state`` 2700(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2701 2702The ``target_state`` encodes the platform coordinated target local power states 2703for the CPU power domain and its parent power domain levels. The handler 2704needs to perform power management operation corresponding to the local state 2705at each power level. 2706 2707For this handler, the local power state for the CPU power domain will be a 2708power down state where as it could be either power down, retention or run state 2709for the higher power domain levels depending on the result of state 2710coordination. The generic code expects the handler to succeed. 2711 2712plat_psci_ops.pwr_domain_validate_suspend() [optional] 2713...................................................... 2714 2715This is an optional function that is only compiled into the build if the build 2716option ``PSCI_OS_INIT_MODE`` is enabled. 2717 2718If implemented, this function allows the platform to perform platform specific 2719validations based on hardware states. The generic code expects this function to 2720return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or 2721PSCI_E_INVALID_PARAMS as appropriate for any invalid requests. 2722 2723plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 2724........................................................... 2725 2726This optional function may be used as a performance optimization to replace 2727or complement pwr_domain_suspend() on some platforms. Its calling semantics 2728are identical to pwr_domain_suspend(), except the PSCI implementation only 2729calls this function when suspending to a power down state, and it guarantees 2730that data caches are enabled. 2731 2732When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2733before calling pwr_domain_suspend(). If the target_state corresponds to a 2734power down state and it is safe to perform some or all of the platform 2735specific actions in that function with data caches enabled, it may be more 2736efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2737= 1, data caches remain enabled throughout, and so there is no advantage to 2738moving platform specific actions to this function. 2739 2740plat_psci_ops.pwr_domain_suspend() 2741.................................. 2742 2743Perform the platform specific actions to prepare to suspend the calling 2744CPU and its higher parent power domain levels as indicated by the 2745``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2746API implementation. 2747 2748The ``target_state`` has a similar meaning as described in 2749the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2750target local power states for the CPU power domain and its parent 2751power domain levels. The handler needs to perform power management operation 2752corresponding to the local state at each power level. The generic code 2753expects the handler to succeed. 2754 2755The difference between turning a power domain off versus suspending it is that 2756in the former case, the power domain is expected to re-initialize its state 2757when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2758case, the power domain is expected to save enough state so that it can resume 2759execution by restoring this state when its powered on (see 2760``pwr_domain_suspend_finish()``). 2761 2762When suspending a core, the platform can also choose to power off the GICv3 2763Redistributor and ITS through an implementation-defined sequence. To achieve 2764this safely, the ITS context must be saved first. The architectural part is 2765implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2766sequence is implementation defined and it is therefore the responsibility of 2767the platform code to implement the necessary sequence. Then the GIC 2768Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2769Powering off the Redistributor requires the implementation to support it and it 2770is the responsibility of the platform code to execute the right implementation 2771defined sequence. 2772 2773When a system suspend is requested, the platform can also make use of the 2774``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2775it has saved the context of the Redistributors and ITS of all the cores in the 2776system. The context of the Distributor can be large and may require it to be 2777allocated in a special area if it cannot fit in the platform's global static 2778data, for example in DRAM. The Distributor can then be powered down using an 2779implementation-defined sequence. 2780 2781plat_psci_ops.pwr_domain_pwr_down_wfi() 2782....................................... 2783 2784This is an optional function and, if implemented, is expected to perform 2785platform specific actions including the ``wfi`` invocation which allows the 2786CPU to powerdown. Since this function is invoked outside the PSCI locks, 2787the actions performed in this hook must be local to the CPU or the platform 2788must ensure that races between multiple CPUs cannot occur. 2789 2790The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2791operation and it encodes the platform coordinated target local power states for 2792the CPU power domain and its parent power domain levels. This function must 2793not return back to the caller (by calling wfi in an infinite loop to ensure 2794some CPUs power down mitigations work properly). 2795 2796If this function is not implemented by the platform, PSCI generic 2797implementation invokes ``psci_power_down_wfi()`` for power down. 2798 2799plat_psci_ops.pwr_domain_on_finish() 2800.................................... 2801 2802This function is called by the PSCI implementation after the calling CPU is 2803powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2804It performs the platform-specific setup required to initialize enough state for 2805this CPU to enter the normal world and also provide secure runtime firmware 2806services. 2807 2808The ``target_state`` (first argument) is the prior state of the power domains 2809immediately before the CPU was turned on. It indicates which power domains 2810above the CPU might require initialization due to having previously been in 2811low power states. The generic code expects the handler to succeed. 2812 2813plat_psci_ops.pwr_domain_on_finish_late() [optional] 2814........................................................... 2815 2816This optional function is called by the PSCI implementation after the calling 2817CPU is fully powered on with respective data caches enabled. The calling CPU and 2818the associated cluster are guaranteed to be participating in coherency. This 2819function gives the flexibility to perform any platform-specific actions safely, 2820such as initialization or modification of shared data structures, without the 2821overhead of explicit cache maintainace operations. 2822 2823The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` 2824operation. The generic code expects the handler to succeed. 2825 2826plat_psci_ops.pwr_domain_suspend_finish() 2827......................................... 2828 2829This function is called by the PSCI implementation after the calling CPU is 2830powered on and released from reset in response to an asynchronous wakeup 2831event, for example a timer interrupt that was programmed by the CPU during the 2832``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2833setup required to restore the saved state for this CPU to resume execution 2834in the normal world and also provide secure runtime firmware services. 2835 2836The ``target_state`` (first argument) has a similar meaning as described in 2837the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2838to succeed. 2839 2840If the Distributor, Redistributors or ITS have been powered off as part of a 2841suspend, their context must be restored in this function in the reverse order 2842to how they were saved during suspend sequence. 2843 2844plat_psci_ops.system_off() 2845.......................... 2846 2847This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2848call. It performs the platform-specific system poweroff sequence after 2849notifying the Secure Payload Dispatcher. 2850 2851plat_psci_ops.system_reset() 2852............................ 2853 2854This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2855call. It performs the platform-specific system reset sequence after 2856notifying the Secure Payload Dispatcher. 2857 2858plat_psci_ops.validate_power_state() 2859.................................... 2860 2861This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2862call to validate the ``power_state`` parameter of the PSCI API and if valid, 2863populate it in ``req_state`` (second argument) array as power domain level 2864specific local states. If the ``power_state`` is invalid, the platform must 2865return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 2866normal world PSCI client. 2867 2868plat_psci_ops.validate_ns_entrypoint() 2869...................................... 2870 2871This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2872``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2873parameter passed by the normal world. If the ``entry_point`` is invalid, 2874the platform must return PSCI_E_INVALID_ADDRESS as error, which is 2875propagated back to the normal world PSCI client. 2876 2877plat_psci_ops.get_sys_suspend_power_state() 2878........................................... 2879 2880This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2881call to get the ``req_state`` parameter from platform which encodes the power 2882domain level specific local states to suspend to system affinity level. The 2883``req_state`` will be utilized to do the PSCI state coordination and 2884``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2885enter system suspend. 2886 2887plat_psci_ops.get_pwr_lvl_state_idx() 2888..................................... 2889 2890This is an optional function and, if implemented, is invoked by the PSCI 2891implementation to convert the ``local_state`` (first argument) at a specified 2892``pwr_lvl`` (second argument) to an index between 0 and 2893``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2894supports more than two local power states at each power domain level, that is 2895``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2896local power states. 2897 2898plat_psci_ops.translate_power_state_by_mpidr() 2899.............................................. 2900 2901This is an optional function and, if implemented, verifies the ``power_state`` 2902(second argument) parameter of the PSCI API corresponding to a target power 2903domain. The target power domain is identified by using both ``MPIDR`` (first 2904argument) and the power domain level encoded in ``power_state``. The power domain 2905level specific local states are to be extracted from ``power_state`` and be 2906populated in the ``output_state`` (third argument) array. The functionality 2907is similar to the ``validate_power_state`` function described above and is 2908envisaged to be used in case the validity of ``power_state`` depend on the 2909targeted power domain. If the ``power_state`` is invalid for the targeted power 2910domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 2911function is not implemented, then the generic implementation relies on 2912``validate_power_state`` function to translate the ``power_state``. 2913 2914This function can also be used in case the platform wants to support local 2915power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 2916APIs as described in Section 5.18 of `PSCI`_. 2917 2918plat_psci_ops.get_node_hw_state() 2919................................. 2920 2921This is an optional function. If implemented this function is intended to return 2922the power state of a node (identified by the first parameter, the ``MPIDR``) in 2923the power domain topology (identified by the second parameter, ``power_level``), 2924as retrieved from a power controller or equivalent component on the platform. 2925Upon successful completion, the implementation must map and return the final 2926status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2927must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2928appropriate. 2929 2930Implementations are not expected to handle ``power_levels`` greater than 2931``PLAT_MAX_PWR_LVL``. 2932 2933plat_psci_ops.system_reset2() 2934............................. 2935 2936This is an optional function. If implemented this function is 2937called during the ``SYSTEM_RESET2`` call to perform a reset 2938based on the first parameter ``reset_type`` as specified in 2939`PSCI`_. The parameter ``cookie`` can be used to pass additional 2940reset information. If the ``reset_type`` is not supported, the 2941function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2942resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2943and vendor reset can return other PSCI error codes as defined 2944in `PSCI`_. On success this function will not return. 2945 2946plat_psci_ops.write_mem_protect() 2947................................. 2948 2949This is an optional function. If implemented it enables or disables the 2950``MEM_PROTECT`` functionality based on the value of ``val``. 2951A non-zero value enables ``MEM_PROTECT`` and a value of zero 2952disables it. Upon encountering failures it must return a negative value 2953and on success it must return 0. 2954 2955plat_psci_ops.read_mem_protect() 2956................................ 2957 2958This is an optional function. If implemented it returns the current 2959state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2960failures it must return a negative value and on success it must 2961return 0. 2962 2963plat_psci_ops.mem_protect_chk() 2964............................... 2965 2966This is an optional function. If implemented it checks if a memory 2967region defined by a base address ``base`` and with a size of ``length`` 2968bytes is protected by ``MEM_PROTECT``. If the region is protected 2969then it must return 0, otherwise it must return a negative number. 2970 2971.. _porting_guide_imf_in_bl31: 2972 2973Interrupt Management framework (in BL31) 2974---------------------------------------- 2975 2976BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2977generated in either security state and targeted to EL1 or EL2 in the non-secure 2978state or EL3/S-EL1 in the secure state. The design of this framework is 2979described in the :ref:`Interrupt Management Framework` 2980 2981A platform should export the following APIs to support the IMF. The following 2982text briefly describes each API and its implementation in Arm standard 2983platforms. The API implementation depends upon the type of interrupt controller 2984present in the platform. Arm standard platform layer supports both 2985`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2986and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2987FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2988``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more 2989details). 2990 2991See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. 2992 2993Function : plat_interrupt_type_to_line() [mandatory] 2994~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2995 2996:: 2997 2998 Argument : uint32_t, uint32_t 2999 Return : uint32_t 3000 3001The Arm processor signals an interrupt exception either through the IRQ or FIQ 3002interrupt line. The specific line that is signaled depends on how the interrupt 3003controller (IC) reports different interrupt types from an execution context in 3004either security state. The IMF uses this API to determine which interrupt line 3005the platform IC uses to signal each type of interrupt supported by the framework 3006from a given security state. This API must be invoked at EL3. 3007 3008The first parameter will be one of the ``INTR_TYPE_*`` values (see 3009:ref:`Interrupt Management Framework`) indicating the target type of the 3010interrupt, the second parameter is the security state of the originating 3011execution context. The return result is the bit position in the ``SCR_EL3`` 3012register of the respective interrupt trap: IRQ=1, FIQ=2. 3013 3014In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 3015configured as FIQs and Non-secure interrupts as IRQs from either security 3016state. 3017 3018In the case of Arm standard platforms using GICv3, the interrupt line to be 3019configured depends on the security state of the execution context when the 3020interrupt is signalled and are as follows: 3021 3022- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 3023 NS-EL0/1/2 context. 3024- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 3025 in the NS-EL0/1/2 context. 3026- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 3027 context. 3028 3029Function : plat_ic_get_pending_interrupt_type() [mandatory] 3030~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3031 3032:: 3033 3034 Argument : void 3035 Return : uint32_t 3036 3037This API returns the type of the highest priority pending interrupt at the 3038platform IC. The IMF uses the interrupt type to retrieve the corresponding 3039handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 3040pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 3041``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 3042 3043In the case of Arm standard platforms using GICv2, the *Highest Priority 3044Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 3045the pending interrupt. The type of interrupt depends upon the id value as 3046follows. 3047 3048#. id < 1022 is reported as a S-EL1 interrupt 3049#. id = 1022 is reported as a Non-secure interrupt. 3050#. id = 1023 is reported as an invalid interrupt type. 3051 3052In the case of Arm standard platforms using GICv3, the system register 3053``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 3054is read to determine the id of the pending interrupt. The type of interrupt 3055depends upon the id value as follows. 3056 3057#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 3058#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 3059#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 3060#. All other interrupt id's are reported as EL3 interrupt. 3061 3062Function : plat_ic_get_pending_interrupt_id() [mandatory] 3063~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3064 3065:: 3066 3067 Argument : void 3068 Return : uint32_t 3069 3070This API returns the id of the highest priority pending interrupt at the 3071platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 3072pending. 3073 3074In the case of Arm standard platforms using GICv2, the *Highest Priority 3075Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 3076pending interrupt. The id that is returned by API depends upon the value of 3077the id read from the interrupt controller as follows. 3078 3079#. id < 1022. id is returned as is. 3080#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 3081 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 3082 This id is returned by the API. 3083#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 3084 3085In the case of Arm standard platforms using GICv3, if the API is invoked from 3086EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 3087group 0 Register*, is read to determine the id of the pending interrupt. The id 3088that is returned by API depends upon the value of the id read from the 3089interrupt controller as follows. 3090 3091#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 3092#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 3093 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 3094 Register* is read to determine the id of the group 1 interrupt. This id 3095 is returned by the API as long as it is a valid interrupt id 3096#. If the id is any of the special interrupt identifiers, 3097 ``INTR_ID_UNAVAILABLE`` is returned. 3098 3099When the API invoked from S-EL1 for GICv3 systems, the id read from system 3100register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 3101Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 3102``INTR_ID_UNAVAILABLE`` is returned. 3103 3104Function : plat_ic_acknowledge_interrupt() [mandatory] 3105~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3106 3107:: 3108 3109 Argument : void 3110 Return : uint32_t 3111 3112This API is used by the CPU to indicate to the platform IC that processing of 3113the highest pending interrupt has begun. It should return the raw, unmodified 3114value obtained from the interrupt controller when acknowledging an interrupt. 3115The actual interrupt number shall be extracted from this raw value using the API 3116`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. 3117 3118This function in Arm standard platforms using GICv2, reads the *Interrupt 3119Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 3120priority pending interrupt from pending to active in the interrupt controller. 3121It returns the value read from the ``GICC_IAR``, unmodified. 3122 3123In the case of Arm standard platforms using GICv3, if the API is invoked 3124from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 3125Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 3126reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 3127group 1*. The read changes the state of the highest pending interrupt from 3128pending to active in the interrupt controller. The value read is returned 3129unmodified. 3130 3131The TSP uses this API to start processing of the secure physical timer 3132interrupt. 3133 3134Function : plat_ic_end_of_interrupt() [mandatory] 3135~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3136 3137:: 3138 3139 Argument : uint32_t 3140 Return : void 3141 3142This API is used by the CPU to indicate to the platform IC that processing of 3143the interrupt corresponding to the id (passed as the parameter) has 3144finished. The id should be the same as the id returned by the 3145``plat_ic_acknowledge_interrupt()`` API. 3146 3147Arm standard platforms write the id to the *End of Interrupt Register* 3148(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 3149system register in case of GICv3 depending on where the API is invoked from, 3150EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 3151controller. 3152 3153The TSP uses this API to finish processing of the secure physical timer 3154interrupt. 3155 3156Function : plat_ic_get_interrupt_type() [mandatory] 3157~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3158 3159:: 3160 3161 Argument : uint32_t 3162 Return : uint32_t 3163 3164This API returns the type of the interrupt id passed as the parameter. 3165``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 3166interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 3167returned depending upon how the interrupt has been configured by the platform 3168IC. This API must be invoked at EL3. 3169 3170Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 3171and Non-secure interrupts as Group1 interrupts. It reads the group value 3172corresponding to the interrupt id from the relevant *Interrupt Group Register* 3173(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 3174 3175In the case of Arm standard platforms using GICv3, both the *Interrupt Group 3176Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 3177(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 3178as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 3179 3180Common helper functions 3181----------------------- 3182Function : elx_panic() 3183~~~~~~~~~~~~~~~~~~~~~~ 3184 3185:: 3186 3187 Argument : void 3188 Return : void 3189 3190This API is called from assembly files when reporting a critical failure 3191that has occured in lower EL and is been trapped in EL3. This call 3192**must not** return. 3193 3194Function : el3_panic() 3195~~~~~~~~~~~~~~~~~~~~~~ 3196 3197:: 3198 3199 Argument : void 3200 Return : void 3201 3202This API is called from assembly files when encountering a critical failure that 3203cannot be recovered from. This function assumes that it is invoked from a C 3204runtime environment i.e. valid stack exists. This call **must not** return. 3205 3206Function : panic() 3207~~~~~~~~~~~~~~~~~~ 3208 3209:: 3210 3211 Argument : void 3212 Return : void 3213 3214This API called from C files when encountering a critical failure that cannot 3215be recovered from. This function in turn prints backtrace (if enabled) and calls 3216el3_panic(). This call **must not** return. 3217 3218Crash Reporting mechanism (in BL31) 3219----------------------------------- 3220 3221BL31 implements a crash reporting mechanism which prints the various registers 3222of the CPU to enable quick crash analysis and debugging. This mechanism relies 3223on the platform implementing ``plat_crash_console_init``, 3224``plat_crash_console_putc`` and ``plat_crash_console_flush``. 3225 3226The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 3227implementation of all of them. Platforms may include this file to their 3228makefiles in order to benefit from them. By default, they will cause the crash 3229output to be routed over the normal console infrastructure and get printed on 3230consoles configured to output in crash state. ``console_set_scope()`` can be 3231used to control whether a console is used for crash output. 3232 3233.. note:: 3234 Platforms are responsible for making sure that they only mark consoles for 3235 use in the crash scope that are able to support this, i.e. that are written 3236 in assembly and conform with the register clobber rules for putc() 3237 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. 3238 3239In some cases (such as debugging very early crashes that happen before the 3240normal boot console can be set up), platforms may want to control crash output 3241more explicitly. These platforms may instead provide custom implementations for 3242these. They are executed outside of a C environment and without a stack. Many 3243console drivers provide functions named ``console_xxx_core_init/putc/flush`` 3244that are designed to be used by these functions. See Arm platforms (like juno) 3245for an example of this. 3246 3247Function : plat_crash_console_init [mandatory] 3248~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3249 3250:: 3251 3252 Argument : void 3253 Return : int 3254 3255This API is used by the crash reporting mechanism to initialize the crash 3256console. It must only use the general purpose registers x0 through x7 to do the 3257initialization and returns 1 on success. 3258 3259Function : plat_crash_console_putc [mandatory] 3260~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3261 3262:: 3263 3264 Argument : int 3265 Return : int 3266 3267This API is used by the crash reporting mechanism to print a character on the 3268designated crash console. It must only use general purpose registers x1 and 3269x2 to do its work. The parameter and the return value are in general purpose 3270register x0. 3271 3272Function : plat_crash_console_flush [mandatory] 3273~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3274 3275:: 3276 3277 Argument : void 3278 Return : void 3279 3280This API is used by the crash reporting mechanism to force write of all buffered 3281data on the designated crash console. It should only use general purpose 3282registers x0 through x5 to do its work. 3283 3284.. _External Abort handling and RAS Support: 3285 3286External Abort handling and RAS Support 3287--------------------------------------- 3288 3289Function : plat_ea_handler 3290~~~~~~~~~~~~~~~~~~~~~~~~~~ 3291 3292:: 3293 3294 Argument : int 3295 Argument : uint64_t 3296 Argument : void * 3297 Argument : void * 3298 Argument : uint64_t 3299 Return : void 3300 3301This function is invoked by the RAS framework for the platform to handle an 3302External Abort received at EL3. The intention of the function is to attempt to 3303resolve the cause of External Abort and return; if that's not possible, to 3304initiate orderly shutdown of the system. 3305 3306The first parameter (``int ea_reason``) indicates the reason for External Abort. 3307Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 3308 3309The second parameter (``uint64_t syndrome``) is the respective syndrome 3310presented to EL3 after having received the External Abort. Depending on the 3311nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 3312can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 3313 3314The third parameter (``void *cookie``) is unused for now. The fourth parameter 3315(``void *handle``) is a pointer to the preempted context. The fifth parameter 3316(``uint64_t flags``) indicates the preempted security state. These parameters 3317are received from the top-level exception handler. 3318 3319If ``RAS_FFH_SUPPORT`` is set to ``1``, the default implementation of this 3320function iterates through RAS handlers registered by the platform. If any of the 3321RAS handlers resolve the External Abort, no further action is taken. 3322 3323If ``RAS_FFH_SUPPORT`` is set to ``0``, or if none of the platform RAS handlers 3324could resolve the External Abort, the default implementation prints an error 3325message, and panics. 3326 3327Function : plat_handle_uncontainable_ea 3328~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3329 3330:: 3331 3332 Argument : int 3333 Argument : uint64_t 3334 Return : void 3335 3336This function is invoked by the RAS framework when an External Abort of 3337Uncontainable type is received at EL3. Due to the critical nature of 3338Uncontainable errors, the intention of this function is to initiate orderly 3339shutdown of the system, and is not expected to return. 3340 3341This function must be implemented in assembly. 3342 3343The first and second parameters are the same as that of ``plat_ea_handler``. 3344 3345The default implementation of this function calls 3346``report_unhandled_exception``. 3347 3348Function : plat_handle_double_fault 3349~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3350 3351:: 3352 3353 Argument : int 3354 Argument : uint64_t 3355 Return : void 3356 3357This function is invoked by the RAS framework when another External Abort is 3358received at EL3 while one is already being handled. I.e., a call to 3359``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 3360this function is to initiate orderly shutdown of the system, and is not expected 3361recover or return. 3362 3363This function must be implemented in assembly. 3364 3365The first and second parameters are the same as that of ``plat_ea_handler``. 3366 3367The default implementation of this function calls 3368``report_unhandled_exception``. 3369 3370Function : plat_handle_el3_ea 3371~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3372 3373:: 3374 3375 Return : void 3376 3377This function is invoked when an External Abort is received while executing in 3378EL3. Due to its critical nature, the intention of this function is to initiate 3379orderly shutdown of the system, and is not expected recover or return. 3380 3381This function must be implemented in assembly. 3382 3383The default implementation of this function calls 3384``report_unhandled_exception``. 3385 3386Function : plat_handle_rng_trap 3387~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3388 3389:: 3390 3391 Argument : uint64_t 3392 Argument : cpu_context_t * 3393 Return : int 3394 3395This function is invoked by BL31's exception handler when there is a synchronous 3396system register trap caused by access to the RNDR or RNDRRS registers. It allows 3397platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to 3398emulate those system registers by returing back some entropy to the lower EL. 3399 3400The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3401syndrome register, which encodes the instruction that was trapped. The interesting 3402information in there is the target register (``get_sysreg_iss_rt()``). 3403 3404The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3405lower exception level, at the time when the execution of the ``mrs`` instruction 3406was trapped. Its content can be changed, to put the entropy into the target 3407register. 3408 3409The return value indicates how to proceed: 3410 3411- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3412- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3413 to the same instruction, so its execution will be repeated. 3414- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3415 to the next instruction. 3416 3417This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP. 3418 3419Function : plat_handle_impdef_trap 3420~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3421 3422:: 3423 3424 Argument : uint64_t 3425 Argument : cpu_context_t * 3426 Return : int 3427 3428This function is invoked by BL31's exception handler when there is a synchronous 3429system register trap caused by access to the implementation defined registers. 3430It allows platforms enabling ``IMPDEF_SYSREG_TRAP`` to emulate those system 3431registers choosing to program bits of their choice. 3432 3433The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3434syndrome register, which encodes the instruction that was trapped. 3435 3436The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3437lower exception level, at the time when the execution of the ``mrs`` instruction 3438was trapped. 3439 3440The return value indicates how to proceed: 3441 3442- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3443- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3444 to the same instruction, so its execution will be repeated. 3445- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3446 to the next instruction. 3447 3448This function needs to be implemented by a platform if it enables 3449IMPDEF_SYSREG_TRAP. 3450 3451Build flags 3452----------- 3453 3454There are some build flags which can be defined by the platform to control 3455inclusion or exclusion of certain BL stages from the FIP image. These flags 3456need to be defined in the platform makefile which will get included by the 3457build system. 3458 3459- **NEED_BL33** 3460 By default, this flag is defined ``yes`` by the build system and ``BL33`` 3461 build option should be supplied as a build option. The platform has the 3462 option of excluding the BL33 image in the ``fip`` image by defining this flag 3463 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 3464 are used, this flag will be set to ``no`` automatically. 3465 3466Platform include paths 3467---------------------- 3468 3469Platforms are allowed to add more include paths to be passed to the compiler. 3470The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in 3471particular for the file ``platform_def.h``. 3472 3473Example: 3474 3475.. code:: c 3476 3477 PLAT_INCLUDES += -Iinclude/plat/myplat/include 3478 3479C Library 3480--------- 3481 3482To avoid subtle toolchain behavioral dependencies, the header files provided 3483by the compiler are not used. The software is built with the ``-nostdinc`` flag 3484to ensure no headers are included from the toolchain inadvertently. Instead the 3485required headers are included in the TF-A source tree. The library only 3486contains those C library definitions required by the local implementation. If 3487more functionality is required, the needed library functions will need to be 3488added to the local implementation. 3489 3490Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3491been written specifically for TF-A. Some implementation files have been obtained 3492from `FreeBSD`_, others have been written specifically for TF-A as well. The 3493files can be found in ``include/lib/libc`` and ``lib/libc``. 3494 3495SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 3496can be obtained from http://github.com/freebsd/freebsd. 3497 3498Storage abstraction layer 3499------------------------- 3500 3501In order to improve platform independence and portability a storage abstraction 3502layer is used to load data from non-volatile platform storage. Currently 3503storage access is only required by BL1 and BL2 phases and performed inside the 3504``load_image()`` function in ``bl_common.c``. 3505 3506.. uml:: resources/diagrams/plantuml/io_framework_usage_overview.puml 3507 3508It is mandatory to implement at least one storage driver. For the Arm 3509development platforms the Firmware Image Package (FIP) driver is provided as 3510the default means to load data from storage (see :ref:`firmware_design_fip`). 3511The storage layer is described in the header file 3512``include/drivers/io/io_storage.h``. The implementation of the common library is 3513in ``drivers/io/io_storage.c`` and the driver files are located in 3514``drivers/io/``. 3515 3516.. uml:: resources/diagrams/plantuml/io_arm_class_diagram.puml 3517 3518Each IO driver must provide ``io_dev_*`` structures, as described in 3519``drivers/io/io_driver.h``. These are returned via a mandatory registration 3520function that is called on platform initialization. The semi-hosting driver 3521implementation in ``io_semihosting.c`` can be used as an example. 3522 3523Each platform should register devices and their drivers via the storage 3524abstraction layer. These drivers then need to be initialized by bootloader 3525phases as required in their respective ``blx_platform_setup()`` functions. 3526 3527.. uml:: resources/diagrams/plantuml/io_dev_registration.puml 3528 3529The storage abstraction layer provides mechanisms (``io_dev_init()``) to 3530initialize storage devices before IO operations are called. 3531 3532.. uml:: resources/diagrams/plantuml/io_dev_init_and_check.puml 3533 3534The basic operations supported by the layer 3535include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3536Drivers do not have to implement all operations, but each platform must 3537provide at least one driver for a device capable of supporting generic 3538operations such as loading a bootloader image. 3539 3540The current implementation only allows for known images to be loaded by the 3541firmware. These images are specified by using their identifiers, as defined in 3542``include/plat/common/common_def.h`` (or a separate header file included from 3543there). The platform layer (``plat_get_image_source()``) then returns a reference 3544to a device and a driver-specific ``spec`` which will be understood by the driver 3545to allow access to the image data. 3546 3547The layer is designed in such a way that is it possible to chain drivers with 3548other drivers. For example, file-system drivers may be implemented on top of 3549physical block devices, both represented by IO devices with corresponding 3550drivers. In such a case, the file-system "binding" with the block device may 3551be deferred until the file-system device is initialised. 3552 3553The abstraction currently depends on structures being statically allocated 3554by the drivers and callers, as the system does not yet provide a means of 3555dynamically allocating memory. This may also have the affect of limiting the 3556amount of open resources per driver. 3557 3558Measured Boot Platform Interface 3559-------------------------------- 3560 3561Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer 3562to :ref:`Measured Boot Design` for more details. 3563 3564-------------- 3565 3566*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* 3567 3568.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 3569.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 3570.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 3571.. _FreeBSD: https://www.freebsd.org 3572.. _SCC: http://www.simple-cc.org/ 3573.. _DRTM: https://developer.arm.com/documentation/den0113/a 3574