1Porting Guide 2============= 3 4Introduction 5------------ 6 7Porting Trusted Firmware-A (TF-A) to a new platform involves making some 8mandatory and optional modifications for both the cold and warm boot paths. 9Modifications consist of: 10 11- Implementing a platform-specific function or variable, 12- Setting up the execution context in a certain way, or 13- Defining certain constants (for example #defines). 14 15The platform-specific functions and variables are declared in 16``include/plat/common/platform.h``. The firmware provides a default 17implementation of variables and functions to fulfill the optional requirements 18in order to ease the porting effort. Each platform port can use them as is or 19provide their own implementation if the default implementation is inadequate. 20 21 .. note:: 22 23 TF-A historically provided default implementations of platform interfaces 24 as *weak* functions. This practice is now discouraged and new platform 25 interfaces as they get introduced in the code base should be *strongly* 26 defined. We intend to convert existing weak functions over time. Until 27 then, you will find references to *weak* functions in this document. 28 29Please review the :ref:`Threat Model` documents as part of the porting 30effort. Some platform interfaces play a key role in mitigating against some of 31the threats. Failing to fulfill these expectations could undermine the security 32guarantees offered by TF-A. These platform responsibilities are highlighted in 33the threat assessment section, under the "`Mitigations implemented?`" box for 34each threat. 35 36Some modifications are common to all Boot Loader (BL) stages. Section 2 37discusses these in detail. The subsequent sections discuss the remaining 38modifications for each BL stage in detail. 39 40Please refer to the :ref:`Platform Ports Policy` for the policy regarding 41compatibility and deprecation of these porting interfaces. 42 43Only Arm development platforms (such as FVP and Juno) may use the 44functions/definitions in ``include/plat/arm/common/`` and the corresponding 45source files in ``plat/arm/common/``. This is done so that there are no 46dependencies between platforms maintained by different people/companies. If you 47want to use any of the functionality present in ``plat/arm`` files, please 48propose a patch that moves the code to ``plat/common`` so that it can be 49discussed. 50 51Common modifications 52-------------------- 53 54This section covers the modifications that should be made by the platform for 55each BL stage to correctly port the firmware stack. They are categorized as 56either mandatory or optional. 57 58Common mandatory modifications 59------------------------------ 60 61A platform port must enable the Memory Management Unit (MMU) as well as the 62instruction and data caches for each BL stage. Setting up the translation 63tables is the responsibility of the platform port because memory maps differ 64across platforms. A memory translation library (see ``lib/xlat_tables_v2/``) is 65provided to help in this setup. 66 67Note that although this library supports non-identity mappings, this is intended 68only for re-mapping peripheral physical addresses and allows platforms with high 69I/O addresses to reduce their virtual address space. All other addresses 70corresponding to code and data must currently use an identity mapping. 71 72Also, the only translation granule size supported in TF-A is 4KB, as various 73parts of the code assume that is the case. It is not possible to switch to 7416 KB or 64 KB granule sizes at the moment. 75 76In Arm standard platforms, each BL stage configures the MMU in the 77platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 78an identity mapping for all addresses. 79 80If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 81block of identity mapped secure memory with Device-nGnRE attributes aligned to 82page boundary (4K) for each BL stage. All sections which allocate coherent 83memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a 84section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its 85possible for the firmware to place variables in it using the following C code 86directive: 87 88:: 89 90 __section(".bakery_lock") 91 92Or alternatively the following assembler code directive: 93 94:: 95 96 .section .bakery_lock 97 98The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are 99used to allocate any data structures that are accessed both when a CPU is 100executing with its MMU and caches enabled, and when it's running with its MMU 101and caches disabled. Examples are given below. 102 103The following variables, functions and constants must be defined by the platform 104for the firmware to work correctly. 105 106.. _platform_def_mandatory: 107 108File : platform_def.h [mandatory] 109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 110 111Each platform must ensure that a header file of this name is in the system 112include path with the following constants defined. This will require updating 113the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 114 115Platform ports may optionally use the file ``include/plat/common/common_def.h``, 116which provides typical values for some of the constants below. These values are 117likely to be suitable for all platform ports. 118 119- **#define : PLATFORM_LINKER_FORMAT** 120 121 Defines the linker format used by the platform, for example 122 ``elf64-littleaarch64``. 123 124- **#define : PLATFORM_LINKER_ARCH** 125 126 Defines the processor architecture for the linker by the platform, for 127 example ``aarch64``. 128 129- **#define : PLATFORM_STACK_SIZE** 130 131 Defines the normal stack memory available to each CPU. This constant is used 132 by ``plat/common/aarch64/platform_mp_stack.S`` and 133 ``plat/common/aarch64/platform_up_stack.S``. 134 135- **#define : CACHE_WRITEBACK_GRANULE** 136 137 Defines the size in bytes of the largest cache line across all the cache 138 levels in the platform. 139 140- **#define : FIRMWARE_WELCOME_STR** 141 142 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 143 function. 144 145- **#define : PLATFORM_CORE_COUNT** 146 147 Defines the total number of CPUs implemented by the platform across all 148 clusters in the system. 149 150- **#define : PLAT_NUM_PWR_DOMAINS** 151 152 Defines the total number of nodes in the power domain topology 153 tree at all the power domain levels used by the platform. 154 This macro is used by the PSCI implementation to allocate 155 data structures to represent power domain topology. 156 157- **#define : PLAT_MAX_PWR_LVL** 158 159 Defines the maximum power domain level that the power management operations 160 should apply to. More often, but not always, the power domain level 161 corresponds to affinity level. This macro allows the PSCI implementation 162 to know the highest power domain level that it should consider for power 163 management operations in the system that the platform implements. For 164 example, the Base AEM FVP implements two clusters with a configurable 165 number of CPUs and it reports the maximum power domain level as 1. 166 167- **#define : PLAT_MAX_OFF_STATE** 168 169 Defines the local power state corresponding to the deepest power down 170 possible at every power domain level in the platform. The local power 171 states for each level may be sparsely allocated between 0 and this value 172 with 0 being reserved for the RUN state. The PSCI implementation uses this 173 value to initialize the local power states of the power domain nodes and 174 to specify the requested power state for a PSCI_CPU_OFF call. 175 176- **#define : PLAT_MAX_RET_STATE** 177 178 Defines the local power state corresponding to the deepest retention state 179 possible at every power domain level in the platform. This macro should be 180 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 181 PSCI implementation to distinguish between retention and power down local 182 power states within PSCI_CPU_SUSPEND call. 183 184- **#define : PLAT_MAX_PWR_LVL_STATES** 185 186 Defines the maximum number of local power states per power domain level 187 that the platform supports. The default value of this macro is 2 since 188 most platforms just support a maximum of two local power states at each 189 power domain level (power-down and retention). If the platform needs to 190 account for more local power states, then it must redefine this macro. 191 192 Currently, this macro is used by the Generic PSCI implementation to size 193 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 194 195- **#define : BL1_RO_BASE** 196 197 Defines the base address in secure ROM where BL1 originally lives. Must be 198 aligned on a page-size boundary. 199 200- **#define : BL1_RO_LIMIT** 201 202 Defines the maximum address in secure ROM that BL1's actual content (i.e. 203 excluding any data section allocated at runtime) can occupy. 204 205- **#define : BL1_RW_BASE** 206 207 Defines the base address in secure RAM where BL1's read-write data will live 208 at runtime. Must be aligned on a page-size boundary. 209 210- **#define : BL1_RW_LIMIT** 211 212 Defines the maximum address in secure RAM that BL1's read-write data can 213 occupy at runtime. 214 215- **#define : BL2_BASE** 216 217 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 218 Must be aligned on a page-size boundary. This constant is not applicable 219 when BL2_IN_XIP_MEM is set to '1'. 220 221- **#define : BL2_LIMIT** 222 223 Defines the maximum address in secure RAM that the BL2 image can occupy. 224 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2_RO_BASE** 227 228 Defines the base address in secure XIP memory where BL2 RO section originally 229 lives. Must be aligned on a page-size boundary. This constant is only needed 230 when BL2_IN_XIP_MEM is set to '1'. 231 232- **#define : BL2_RO_LIMIT** 233 234 Defines the maximum address in secure XIP memory that BL2's actual content 235 (i.e. excluding any data section allocated at runtime) can occupy. This 236 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 237 238- **#define : BL2_RW_BASE** 239 240 Defines the base address in secure RAM where BL2's read-write data will live 241 at runtime. Must be aligned on a page-size boundary. This constant is only 242 needed when BL2_IN_XIP_MEM is set to '1'. 243 244- **#define : BL2_RW_LIMIT** 245 246 Defines the maximum address in secure RAM that BL2's read-write data can 247 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 248 to '1'. 249 250- **#define : BL31_BASE** 251 252 Defines the base address in secure RAM where BL2 loads the BL31 binary 253 image. Must be aligned on a page-size boundary. 254 255- **#define : BL31_LIMIT** 256 257 Defines the maximum address in secure RAM that the BL31 image can occupy. 258 259- **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE** 260 261 Defines the maximum message size between AP and RSS. Need to define if 262 platform supports RSS. 263 264For every image, the platform must define individual identifiers that will be 265used by BL1 or BL2 to load the corresponding image into memory from non-volatile 266storage. For the sake of performance, integer numbers will be used as 267identifiers. The platform will use those identifiers to return the relevant 268information about the image to be loaded (file handler, load address, 269authentication information, etc.). The following image identifiers are 270mandatory: 271 272- **#define : BL2_IMAGE_ID** 273 274 BL2 image identifier, used by BL1 to load BL2. 275 276- **#define : BL31_IMAGE_ID** 277 278 BL31 image identifier, used by BL2 to load BL31. 279 280- **#define : BL33_IMAGE_ID** 281 282 BL33 image identifier, used by BL2 to load BL33. 283 284If Trusted Board Boot is enabled, the following certificate identifiers must 285also be defined: 286 287- **#define : TRUSTED_BOOT_FW_CERT_ID** 288 289 BL2 content certificate identifier, used by BL1 to load the BL2 content 290 certificate. 291 292- **#define : TRUSTED_KEY_CERT_ID** 293 294 Trusted key certificate identifier, used by BL2 to load the trusted key 295 certificate. 296 297- **#define : SOC_FW_KEY_CERT_ID** 298 299 BL31 key certificate identifier, used by BL2 to load the BL31 key 300 certificate. 301 302- **#define : SOC_FW_CONTENT_CERT_ID** 303 304 BL31 content certificate identifier, used by BL2 to load the BL31 content 305 certificate. 306 307- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 308 309 BL33 key certificate identifier, used by BL2 to load the BL33 key 310 certificate. 311 312- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 313 314 BL33 content certificate identifier, used by BL2 to load the BL33 content 315 certificate. 316 317- **#define : FWU_CERT_ID** 318 319 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 320 FWU content certificate. 321 322- **#define : PLAT_CRYPTOCELL_BASE** 323 324 This defines the base address of Arm® TrustZone® CryptoCell and must be 325 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 326 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 327 set. 328 329If the AP Firmware Updater Configuration image, BL2U is used, the following 330must also be defined: 331 332- **#define : BL2U_BASE** 333 334 Defines the base address in secure memory where BL1 copies the BL2U binary 335 image. Must be aligned on a page-size boundary. 336 337- **#define : BL2U_LIMIT** 338 339 Defines the maximum address in secure memory that the BL2U image can occupy. 340 341- **#define : BL2U_IMAGE_ID** 342 343 BL2U image identifier, used by BL1 to fetch an image descriptor 344 corresponding to BL2U. 345 346If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 347must also be defined: 348 349- **#define : SCP_BL2U_IMAGE_ID** 350 351 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 352 corresponding to SCP_BL2U. 353 354 .. note:: 355 TF-A does not provide source code for this image. 356 357If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 358also be defined: 359 360- **#define : NS_BL1U_BASE** 361 362 Defines the base address in non-secure ROM where NS_BL1U executes. 363 Must be aligned on a page-size boundary. 364 365 .. note:: 366 TF-A does not provide source code for this image. 367 368- **#define : NS_BL1U_IMAGE_ID** 369 370 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 371 corresponding to NS_BL1U. 372 373If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 374be defined: 375 376- **#define : NS_BL2U_BASE** 377 378 Defines the base address in non-secure memory where NS_BL2U executes. 379 Must be aligned on a page-size boundary. 380 381 .. note:: 382 TF-A does not provide source code for this image. 383 384- **#define : NS_BL2U_IMAGE_ID** 385 386 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 387 corresponding to NS_BL2U. 388 389For the the Firmware update capability of TRUSTED BOARD BOOT, the following 390macros may also be defined: 391 392- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 393 394 Total number of images that can be loaded simultaneously. If the platform 395 doesn't specify any value, it defaults to 10. 396 397If a SCP_BL2 image is supported by the platform, the following constants must 398also be defined: 399 400- **#define : SCP_BL2_IMAGE_ID** 401 402 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 403 from platform storage before being transferred to the SCP. 404 405- **#define : SCP_FW_KEY_CERT_ID** 406 407 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 408 certificate (mandatory when Trusted Board Boot is enabled). 409 410- **#define : SCP_FW_CONTENT_CERT_ID** 411 412 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 413 content certificate (mandatory when Trusted Board Boot is enabled). 414 415If a BL32 image is supported by the platform, the following constants must 416also be defined: 417 418- **#define : BL32_IMAGE_ID** 419 420 BL32 image identifier, used by BL2 to load BL32. 421 422- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 423 424 BL32 key certificate identifier, used by BL2 to load the BL32 key 425 certificate (mandatory when Trusted Board Boot is enabled). 426 427- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 428 429 BL32 content certificate identifier, used by BL2 to load the BL32 content 430 certificate (mandatory when Trusted Board Boot is enabled). 431 432- **#define : BL32_BASE** 433 434 Defines the base address in secure memory where BL2 loads the BL32 binary 435 image. Must be aligned on a page-size boundary. 436 437- **#define : BL32_LIMIT** 438 439 Defines the maximum address that the BL32 image can occupy. 440 441If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 442platform, the following constants must also be defined: 443 444- **#define : TSP_SEC_MEM_BASE** 445 446 Defines the base address of the secure memory used by the TSP image on the 447 platform. This must be at the same address or below ``BL32_BASE``. 448 449- **#define : TSP_SEC_MEM_SIZE** 450 451 Defines the size of the secure memory used by the BL32 image on the 452 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 453 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 454 and ``BL32_LIMIT``. 455 456- **#define : TSP_IRQ_SEC_PHY_TIMER** 457 458 Defines the ID of the secure physical generic timer interrupt used by the 459 TSP's interrupt handling code. 460 461If the platform port uses the translation table library code, the following 462constants must also be defined: 463 464- **#define : PLAT_XLAT_TABLES_DYNAMIC** 465 466 Optional flag that can be set per-image to enable the dynamic allocation of 467 regions even when the MMU is enabled. If not defined, only static 468 functionality will be available, if defined and set to 1 it will also 469 include the dynamic functionality. 470 471- **#define : MAX_XLAT_TABLES** 472 473 Defines the maximum number of translation tables that are allocated by the 474 translation table library code. To minimize the amount of runtime memory 475 used, choose the smallest value needed to map the required virtual addresses 476 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 477 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 478 as well. 479 480- **#define : MAX_MMAP_REGIONS** 481 482 Defines the maximum number of regions that are allocated by the translation 483 table library code. A region consists of physical base address, virtual base 484 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 485 defined in the ``mmap_region_t`` structure. The platform defines the regions 486 that should be mapped. Then, the translation table library will create the 487 corresponding tables and descriptors at runtime. To minimize the amount of 488 runtime memory used, choose the smallest value needed to register the 489 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 490 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 491 the dynamic regions as well. 492 493- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 494 495 Defines the total size of the virtual address space in bytes. For example, 496 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 497 498- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 499 500 Defines the total size of the physical address space in bytes. For example, 501 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 502 503If the platform port uses the IO storage framework, the following constants 504must also be defined: 505 506- **#define : MAX_IO_DEVICES** 507 508 Defines the maximum number of registered IO devices. Attempting to register 509 more devices than this value using ``io_register_device()`` will fail with 510 -ENOMEM. 511 512- **#define : MAX_IO_HANDLES** 513 514 Defines the maximum number of open IO handles. Attempting to open more IO 515 entities than this value using ``io_open()`` will fail with -ENOMEM. 516 517- **#define : MAX_IO_BLOCK_DEVICES** 518 519 Defines the maximum number of registered IO block devices. Attempting to 520 register more devices this value using ``io_dev_open()`` will fail 521 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 522 With this macro, multiple block devices could be supported at the same 523 time. 524 525If the platform needs to allocate data within the per-cpu data framework in 526BL31, it should define the following macro. Currently this is only required if 527the platform decides not to use the coherent memory section by undefining the 528``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 529required memory within the the per-cpu data to minimize wastage. 530 531- **#define : PLAT_PCPU_DATA_SIZE** 532 533 Defines the memory (in bytes) to be reserved within the per-cpu data 534 structure for use by the platform layer. 535 536The following constants are optional. They should be defined when the platform 537memory layout implies some image overlaying like in Arm standard platforms. 538 539- **#define : BL31_PROGBITS_LIMIT** 540 541 Defines the maximum address in secure RAM that the BL31's progbits sections 542 can occupy. 543 544- **#define : TSP_PROGBITS_LIMIT** 545 546 Defines the maximum address that the TSP's progbits sections can occupy. 547 548If the platform supports OS-initiated mode, i.e. the build option 549``PSCI_OS_INIT_MODE`` is enabled, and if the platform's maximum power domain 550level for PSCI_CPU_SUSPEND differs from ``PLAT_MAX_PWR_LVL``, the following 551constant must be defined. 552 553- **#define : PLAT_MAX_CPU_SUSPEND_PWR_LVL** 554 555 Defines the maximum power domain level that PSCI_CPU_SUSPEND should apply to. 556 557If the platform port uses the PL061 GPIO driver, the following constant may 558optionally be defined: 559 560- **PLAT_PL061_MAX_GPIOS** 561 Maximum number of GPIOs required by the platform. This allows control how 562 much memory is allocated for PL061 GPIO controllers. The default value is 563 564 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 565 566If the platform port uses the partition driver, the following constant may 567optionally be defined: 568 569- **PLAT_PARTITION_MAX_ENTRIES** 570 Maximum number of partition entries required by the platform. This allows 571 control how much memory is allocated for partition entries. The default 572 value is 128. 573 For example, define the build flag in ``platform.mk``: 574 PLAT_PARTITION_MAX_ENTRIES := 12 575 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 576 577- **PLAT_PARTITION_BLOCK_SIZE** 578 The size of partition block. It could be either 512 bytes or 4096 bytes. 579 The default value is 512. 580 For example, define the build flag in ``platform.mk``: 581 PLAT_PARTITION_BLOCK_SIZE := 4096 582 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) 583 584If the platform port uses the Arm® Ethos™-N NPU driver, the following 585configuration must be performed: 586 587- The NPU SiP service handler must be hooked up. This consists of both the 588 initial setup (``ethosn_smc_setup``) and the handler itself 589 (``ethosn_smc_handler``) 590 591If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support 592enabled, the following constants and configuration must also be defined: 593 594- **ARM_ETHOSN_NPU_PROT_FW_NSAID** 595 596 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to 597 access the protected memory that contains the NPU's firmware. 598 599- **ARM_ETHOSN_NPU_PROT_DATA_RW_NSAID** 600 601 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 602 read/write access to the protected memory that contains inference data. 603 604- **ARM_ETHOSN_NPU_PROT_DATA_RO_NSAID** 605 606 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 607 read-only access to the protected memory that contains inference data. 608 609- **ARM_ETHOSN_NPU_NS_RW_DATA_NSAID** 610 611 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 612 read/write access to the non-protected memory. 613 614- **ARM_ETHOSN_NPU_NS_RO_DATA_NSAID** 615 616 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 617 read-only access to the non-protected memory. 618 619- **ARM_ETHOSN_NPU_FW_IMAGE_BASE** and **ARM_ETHOSN_NPU_FW_IMAGE_LIMIT** 620 621 Defines the physical address range that the NPU's firmware will be loaded 622 into and executed from. 623 624- Configure the platforms TrustZone Controller (TZC) with appropriate regions 625 of protected memory. At minimum this must include a region for the NPU's 626 firmware code and a region for protected inference data, and these must be 627 accessible using the NSAIDs defined above. 628 629- Include the NPU firmware and certificates in the FIP. 630 631- Provide FCONF entries to configure the image source for the NPU firmware 632 and certificates. 633 634- Add MMU mappings such that: 635 636 - BL2 can write the NPU firmware into the region defined by 637 ``ARM_ETHOSN_NPU_FW_IMAGE_BASE`` and ``ARM_ETHOSN_NPU_FW_IMAGE_LIMIT`` 638 - BL31 (SiP service) can read the NPU firmware from the same region 639 640- Add the firmware image ID ``ARM_ETHOSN_NPU_FW_IMAGE_ID`` to the list of images 641 loaded by BL2. 642 643Please see the reference implementation code for the Juno platform as an example. 644 645 646The following constant is optional. It should be defined to override the default 647behaviour of the ``assert()`` function (for example, to save memory). 648 649- **PLAT_LOG_LEVEL_ASSERT** 650 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 651 ``assert()`` prints the name of the file, the line number and the asserted 652 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 653 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 654 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 655 defined, it defaults to ``LOG_LEVEL``. 656 657If the platform port uses the DRTM feature, the following constants must be 658defined: 659 660- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE** 661 662 Maximum Event Log size used by the platform. Platform can decide the maximum 663 size of the Event Log buffer, depending upon the highest hash algorithm 664 chosen and the number of components selected to measure during the DRTM 665 execution flow. 666 667- **#define : PLAT_DRTM_MMAP_ENTRIES** 668 669 Number of the MMAP entries used by the DRTM implementation to calculate the 670 size of address map region of the platform. 671 672File : plat_macros.S [mandatory] 673~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 674 675Each platform must ensure a file of this name is in the system include path with 676the following macro defined. In the Arm development platforms, this file is 677found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 678 679- **Macro : plat_crash_print_regs** 680 681 This macro allows the crash reporting routine to print relevant platform 682 registers in case of an unhandled exception in BL31. This aids in debugging 683 and this macro can be defined to be empty in case register reporting is not 684 desired. 685 686 For instance, GIC or interconnect registers may be helpful for 687 troubleshooting. 688 689Handling Reset 690-------------- 691 692BL1 by default implements the reset vector where execution starts from a cold 693or warm boot. BL31 can be optionally set as a reset vector using the 694``RESET_TO_BL31`` make variable. 695 696For each CPU, the reset vector code is responsible for the following tasks: 697 698#. Distinguishing between a cold boot and a warm boot. 699 700#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 701 the CPU is placed in a platform-specific state until the primary CPU 702 performs the necessary steps to remove it from this state. 703 704#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 705 specific address in the BL31 image in the same processor mode as it was 706 when released from reset. 707 708The following functions need to be implemented by the platform port to enable 709reset vector code to perform the above tasks. 710 711Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 712~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 713 714:: 715 716 Argument : void 717 Return : uintptr_t 718 719This function is called with the MMU and caches disabled 720(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 721distinguishing between a warm and cold reset for the current CPU using 722platform-specific means. If it's a warm reset, then it returns the warm 723reset entrypoint point provided to ``plat_setup_psci_ops()`` during 724BL31 initialization. If it's a cold reset then this function must return zero. 725 726This function does not follow the Procedure Call Standard used by the 727Application Binary Interface for the Arm 64-bit architecture. The caller should 728not assume that callee saved registers are preserved across a call to this 729function. 730 731This function fulfills requirement 1 and 3 listed above. 732 733Note that for platforms that support programming the reset address, it is 734expected that a CPU will start executing code directly at the right address, 735both on a cold and warm reset. In this case, there is no need to identify the 736type of reset nor to query the warm reset entrypoint. Therefore, implementing 737this function is not required on such platforms. 738 739Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 740~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 741 742:: 743 744 Argument : void 745 746This function is called with the MMU and data caches disabled. It is responsible 747for placing the executing secondary CPU in a platform-specific state until the 748primary CPU performs the necessary actions to bring it out of that state and 749allow entry into the OS. This function must not return. 750 751In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 752itself off. The primary CPU is responsible for powering up the secondary CPUs 753when normal world software requires them. When booting an EL3 payload instead, 754they stay powered on and are put in a holding pen until their mailbox gets 755populated. 756 757This function fulfills requirement 2 above. 758 759Note that for platforms that can't release secondary CPUs out of reset, only the 760primary CPU will execute the cold boot code. Therefore, implementing this 761function is not required on such platforms. 762 763Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 764~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 765 766:: 767 768 Argument : void 769 Return : unsigned int 770 771This function identifies whether the current CPU is the primary CPU or a 772secondary CPU. A return value of zero indicates that the CPU is not the 773primary CPU, while a non-zero return value indicates that the CPU is the 774primary CPU. 775 776Note that for platforms that can't release secondary CPUs out of reset, only the 777primary CPU will execute the cold boot code. Therefore, there is no need to 778distinguish between primary and secondary CPUs and implementing this function is 779not required. 780 781Function : platform_mem_init() [mandatory] 782~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 783 784:: 785 786 Argument : void 787 Return : void 788 789This function is called before any access to data is made by the firmware, in 790order to carry out any essential memory initialization. 791 792Function: plat_get_rotpk_info() 793~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 794 795:: 796 797 Argument : void *, void **, unsigned int *, unsigned int * 798 Return : int 799 800This function is mandatory when Trusted Board Boot is enabled. It returns a 801pointer to the ROTPK stored in the platform (or a hash of it) and its length. 802The ROTPK must be encoded in DER format according to the following ASN.1 803structure: 804 805:: 806 807 AlgorithmIdentifier ::= SEQUENCE { 808 algorithm OBJECT IDENTIFIER, 809 parameters ANY DEFINED BY algorithm OPTIONAL 810 } 811 812 SubjectPublicKeyInfo ::= SEQUENCE { 813 algorithm AlgorithmIdentifier, 814 subjectPublicKey BIT STRING 815 } 816 817In case the function returns a hash of the key: 818 819:: 820 821 DigestInfo ::= SEQUENCE { 822 digestAlgorithm AlgorithmIdentifier, 823 digest OCTET STRING 824 } 825 826The function returns 0 on success. Any other value is treated as error by the 827Trusted Board Boot. The function also reports extra information related 828to the ROTPK in the flags parameter: 829 830:: 831 832 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 833 hash. 834 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 835 verification while the platform ROTPK is not deployed. 836 When this flag is set, the function does not need to 837 return a platform ROTPK, and the authentication 838 framework uses the ROTPK in the certificate without 839 verifying it against the platform value. This flag 840 must not be used in a deployed production environment. 841 842Function: plat_get_nv_ctr() 843~~~~~~~~~~~~~~~~~~~~~~~~~~~ 844 845:: 846 847 Argument : void *, unsigned int * 848 Return : int 849 850This function is mandatory when Trusted Board Boot is enabled. It returns the 851non-volatile counter value stored in the platform in the second argument. The 852cookie in the first argument may be used to select the counter in case the 853platform provides more than one (for example, on platforms that use the default 854TBBR CoT, the cookie will correspond to the OID values defined in 855TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 856 857The function returns 0 on success. Any other value means the counter value could 858not be retrieved from the platform. 859 860Function: plat_set_nv_ctr() 861~~~~~~~~~~~~~~~~~~~~~~~~~~~ 862 863:: 864 865 Argument : void *, unsigned int 866 Return : int 867 868This function is mandatory when Trusted Board Boot is enabled. It sets a new 869counter value in the platform. The cookie in the first argument may be used to 870select the counter (as explained in plat_get_nv_ctr()). The second argument is 871the updated counter value to be written to the NV counter. 872 873The function returns 0 on success. Any other value means the counter value could 874not be updated. 875 876Function: plat_set_nv_ctr2() 877~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 878 879:: 880 881 Argument : void *, const auth_img_desc_t *, unsigned int 882 Return : int 883 884This function is optional when Trusted Board Boot is enabled. If this 885interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 886first argument passed is a cookie and is typically used to 887differentiate between a Non Trusted NV Counter and a Trusted NV 888Counter. The second argument is a pointer to an authentication image 889descriptor and may be used to decide if the counter is allowed to be 890updated or not. The third argument is the updated counter value to 891be written to the NV counter. 892 893The function returns 0 on success. Any other value means the counter value 894either could not be updated or the authentication image descriptor indicates 895that it is not allowed to be updated. 896 897Function: plat_convert_pk() 898~~~~~~~~~~~~~~~~~~~~~~~~~~~ 899 900:: 901 902 Argument : void *, unsigned int, void **, unsigned int * 903 Return : int 904 905This function is optional when Trusted Board Boot is enabled, and only 906used if the platform saves a hash of the ROTPK. 907First argument is the Distinguished Encoding Rules (DER) ROTPK. 908Second argument is its size. 909Third argument is used to return a pointer to a buffer, which hash should 910be the one saved in OTP. 911Fourth argument is a pointer to return its size. 912 913Most platforms save the hash of the ROTPK, but some may save slightly different 914information - e.g the hash of the ROTPK plus some related information. 915Defining this function allows to transform the ROTPK used to verify 916the signature to the buffer (a platform specific public key) which 917hash is saved in OTP. 918 919The default implementation copies the input key and length to the output without 920modification. 921 922The function returns 0 on success. Any other value means the expected 923public key buffer cannot be extracted. 924 925Dynamic Root of Trust for Measurement support (in BL31) 926------------------------------------------------------- 927 928The functions mentioned in this section are mandatory, when platform enables 929DRTM_SUPPORT build flag. 930 931Function : plat_get_addr_mmap() 932~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 933 934:: 935 936 Argument : void 937 Return : const mmap_region_t * 938 939This function is used to return the address of the platform *address-map* table, 940which describes the regions of normal memory, memory mapped I/O 941and non-volatile memory. 942 943Function : plat_has_non_host_platforms() 944~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 945 946:: 947 948 Argument : void 949 Return : bool 950 951This function returns *true* if the platform has any trusted devices capable of 952DMA, otherwise returns *false*. 953 954Function : plat_has_unmanaged_dma_peripherals() 955~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 956 957:: 958 959 Argument : void 960 Return : bool 961 962This function returns *true* if platform uses peripherals whose DMA is not 963managed by an SMMU, otherwise returns *false*. 964 965Note - 966If the platform has peripherals that are not managed by the SMMU, then the 967platform should investigate such peripherals to determine whether they can 968be trusted, and such peripherals should be moved under "Non-host platforms" 969if they can be trusted. 970 971Function : plat_get_total_num_smmus() 972~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 973 974:: 975 976 Argument : void 977 Return : unsigned int 978 979This function returns the total number of SMMUs in the platform. 980 981Function : plat_enumerate_smmus() 982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 983:: 984 985 986 Argument : void 987 Return : const uintptr_t *, size_t 988 989This function returns an array of SMMU addresses and the actual number of SMMUs 990reported by the platform. 991 992Function : plat_drtm_get_dma_prot_features() 993~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 994 995:: 996 997 Argument : void 998 Return : const plat_drtm_dma_prot_features_t* 999 1000This function returns the address of plat_drtm_dma_prot_features_t structure 1001containing the maximum number of protected regions and bitmap with the types 1002of DMA protection supported by the platform. 1003For more details see section 3.3 Table 6 of `DRTM`_ specification. 1004 1005Function : plat_drtm_dma_prot_get_max_table_bytes() 1006~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1007 1008:: 1009 1010 Argument : void 1011 Return : uint64_t 1012 1013This function returns the maximum size of DMA protected regions table in 1014bytes. 1015 1016Function : plat_drtm_get_tpm_features() 1017~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1018 1019:: 1020 1021 Argument : void 1022 Return : const plat_drtm_tpm_features_t* 1023 1024This function returns the address of *plat_drtm_tpm_features_t* structure 1025containing PCR usage schema, TPM-based hash, and firmware hash algorithm 1026supported by the platform. 1027 1028Function : plat_drtm_get_min_size_normal_world_dce() 1029~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1030 1031:: 1032 1033 Argument : void 1034 Return : uint64_t 1035 1036This function returns the size normal-world DCE of the platform. 1037 1038Function : plat_drtm_get_imp_def_dlme_region_size() 1039~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1040 1041:: 1042 1043 Argument : void 1044 Return : uint64_t 1045 1046This function returns the size of implementation defined DLME region 1047of the platform. 1048 1049Function : plat_drtm_get_tcb_hash_table_size() 1050~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1051 1052:: 1053 1054 Argument : void 1055 Return : uint64_t 1056 1057This function returns the size of TCB hash table of the platform. 1058 1059Function : plat_drtm_get_tcb_hash_features() 1060~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1061 1062:: 1063 1064 Argument : void 1065 Return : uint64_t 1066 1067This function returns the Maximum number of TCB hashes recorded by the 1068platform. 1069For more details see section 3.3 Table 6 of `DRTM`_ specification. 1070 1071Function : plat_drtm_validate_ns_region() 1072~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1073 1074:: 1075 1076 Argument : uintptr_t, uintptr_t 1077 Return : int 1078 1079This function validates that given region is within the Non-Secure region 1080of DRAM. This function takes a region start address and size an input 1081arguments, and returns 0 on success and -1 on failure. 1082 1083Function : plat_set_drtm_error() 1084~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1085 1086:: 1087 1088 Argument : uint64_t 1089 Return : int 1090 1091This function writes a 64 bit error code received as input into 1092non-volatile storage and returns 0 on success and -1 on failure. 1093 1094Function : plat_get_drtm_error() 1095~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1096 1097:: 1098 1099 Argument : uint64_t* 1100 Return : int 1101 1102This function reads a 64 bit error code from the non-volatile storage 1103into the received address, and returns 0 on success and -1 on failure. 1104 1105Common mandatory function modifications 1106--------------------------------------- 1107 1108The following functions are mandatory functions which need to be implemented 1109by the platform port. 1110 1111Function : plat_my_core_pos() 1112~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1113 1114:: 1115 1116 Argument : void 1117 Return : unsigned int 1118 1119This function returns the index of the calling CPU which is used as a 1120CPU-specific linear index into blocks of memory (for example while allocating 1121per-CPU stacks). This function will be invoked very early in the 1122initialization sequence which mandates that this function should be 1123implemented in assembly and should not rely on the availability of a C 1124runtime environment. This function can clobber x0 - x8 and must preserve 1125x9 - x29. 1126 1127This function plays a crucial role in the power domain topology framework in 1128PSCI and details of this can be found in 1129:ref:`PSCI Power Domain Tree Structure`. 1130 1131Function : plat_core_pos_by_mpidr() 1132~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1133 1134:: 1135 1136 Argument : u_register_t 1137 Return : int 1138 1139This function validates the ``MPIDR`` of a CPU and converts it to an index, 1140which can be used as a CPU-specific linear index into blocks of memory. In 1141case the ``MPIDR`` is invalid, this function returns -1. This function will only 1142be invoked by BL31 after the power domain topology is initialized and can 1143utilize the C runtime environment. For further details about how TF-A 1144represents the power domain topology and how this relates to the linear CPU 1145index, please refer :ref:`PSCI Power Domain Tree Structure`. 1146 1147Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 1148~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1149 1150:: 1151 1152 Arguments : void **heap_addr, size_t *heap_size 1153 Return : int 1154 1155This function is invoked during Mbed TLS library initialisation to get a heap, 1156by means of a starting address and a size. This heap will then be used 1157internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 1158must be able to provide a heap to it. 1159 1160A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 1161which a heap is statically reserved during compile time inside every image 1162(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 1163the function simply returns the address and size of this "pre-allocated" heap. 1164For a platform to use this default implementation, only a call to the helper 1165from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 1166 1167However, by writting their own implementation, platforms have the potential to 1168optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 1169shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 1170twice. 1171 1172On success the function should return 0 and a negative error code otherwise. 1173 1174Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] 1175~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1176 1177:: 1178 1179 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, 1180 size_t *key_len, unsigned int *flags, const uint8_t *img_id, 1181 size_t img_id_len 1182 Return : int 1183 1184This function provides a symmetric key (either SSK or BSSK depending on 1185fw_enc_status) which is invoked during runtime decryption of encrypted 1186firmware images. `plat/common/plat_bl_common.c` provides a dummy weak 1187implementation for testing purposes which must be overridden by the platform 1188trying to implement a real world firmware encryption use-case. 1189 1190It also allows the platform to pass symmetric key identifier rather than 1191actual symmetric key which is useful in cases where the crypto backend provides 1192secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` 1193flag must be set in ``flags``. 1194 1195In addition to above a platform may also choose to provide an image specific 1196symmetric key/identifier using img_id. 1197 1198On success the function should return 0 and a negative error code otherwise. 1199 1200Note that this API depends on ``DECRYPTION_SUPPORT`` build flag. 1201 1202Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1] 1203~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1204 1205:: 1206 1207 Argument : const struct fwu_metadata *metadata 1208 Return : void 1209 1210This function is mandatory when PSA_FWU_SUPPORT is enabled. 1211It provides a means to retrieve image specification (offset in 1212non-volatile storage and length) of active/updated images using the passed 1213FWU metadata, and update I/O policies of active/updated images using retrieved 1214image specification information. 1215Further I/O layer operations such as I/O open, I/O read, etc. on these 1216images rely on this function call. 1217 1218In Arm platforms, this function is used to set an I/O policy of the FIP image, 1219container of all active/updated secure and non-secure images. 1220 1221Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1] 1222~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1223 1224:: 1225 1226 Argument : unsigned int image_id, uintptr_t *dev_handle, 1227 uintptr_t *image_spec 1228 Return : int 1229 1230This function is mandatory when PSA_FWU_SUPPORT is enabled. It is 1231responsible for setting up the platform I/O policy of the requested metadata 1232image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will 1233be used to load this image from the platform's non-volatile storage. 1234 1235FWU metadata can not be always stored as a raw image in non-volatile storage 1236to define its image specification (offset in non-volatile storage and length) 1237statically in I/O policy. 1238For example, the FWU metadata image is stored as a partition inside the GUID 1239partition table image. Its specification is defined in the partition table 1240that needs to be parsed dynamically. 1241This function provides a means to retrieve such dynamic information to set 1242the I/O policy of the FWU metadata image. 1243Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata 1244image relies on this function call. 1245 1246It returns '0' on success, otherwise a negative error value on error. 1247Alongside, returns device handle and image specification from the I/O policy 1248of the requested FWU metadata image. 1249 1250Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1] 1251~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1252 1253:: 1254 1255 Argument : void 1256 Return : uint32_t 1257 1258This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the 1259means to retrieve the boot index value from the platform. The boot index is the 1260bank from which the platform has booted the firmware images. 1261 1262By default, the platform will read the metadata structure and try to boot from 1263the active bank. If the platform fails to boot from the active bank due to 1264reasons like an Authentication failure, or on crossing a set number of watchdog 1265resets while booting from the active bank, the platform can then switch to boot 1266from a different bank. This function then returns the bank that the platform 1267should boot its images from. 1268 1269Common optional modifications 1270----------------------------- 1271 1272The following are helper functions implemented by the firmware that perform 1273common platform-specific tasks. A platform may choose to override these 1274definitions. 1275 1276Function : plat_set_my_stack() 1277~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1278 1279:: 1280 1281 Argument : void 1282 Return : void 1283 1284This function sets the current stack pointer to the normal memory stack that 1285has been allocated for the current CPU. For BL images that only require a 1286stack for the primary CPU, the UP version of the function is used. The size 1287of the stack allocated to each CPU is specified by the platform defined 1288constant ``PLATFORM_STACK_SIZE``. 1289 1290Common implementations of this function for the UP and MP BL images are 1291provided in ``plat/common/aarch64/platform_up_stack.S`` and 1292``plat/common/aarch64/platform_mp_stack.S`` 1293 1294Function : plat_get_my_stack() 1295~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1296 1297:: 1298 1299 Argument : void 1300 Return : uintptr_t 1301 1302This function returns the base address of the normal memory stack that 1303has been allocated for the current CPU. For BL images that only require a 1304stack for the primary CPU, the UP version of the function is used. The size 1305of the stack allocated to each CPU is specified by the platform defined 1306constant ``PLATFORM_STACK_SIZE``. 1307 1308Common implementations of this function for the UP and MP BL images are 1309provided in ``plat/common/aarch64/platform_up_stack.S`` and 1310``plat/common/aarch64/platform_mp_stack.S`` 1311 1312Function : plat_report_exception() 1313~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1314 1315:: 1316 1317 Argument : unsigned int 1318 Return : void 1319 1320A platform may need to report various information about its status when an 1321exception is taken, for example the current exception level, the CPU security 1322state (secure/non-secure), the exception type, and so on. This function is 1323called in the following circumstances: 1324 1325- In BL1, whenever an exception is taken. 1326- In BL2, whenever an exception is taken. 1327 1328The default implementation doesn't do anything, to avoid making assumptions 1329about the way the platform displays its status information. 1330 1331For AArch64, this function receives the exception type as its argument. 1332Possible values for exceptions types are listed in the 1333``include/common/bl_common.h`` header file. Note that these constants are not 1334related to any architectural exception code; they are just a TF-A convention. 1335 1336For AArch32, this function receives the exception mode as its argument. 1337Possible values for exception modes are listed in the 1338``include/lib/aarch32/arch.h`` header file. 1339 1340Function : plat_reset_handler() 1341~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1342 1343:: 1344 1345 Argument : void 1346 Return : void 1347 1348A platform may need to do additional initialization after reset. This function 1349allows the platform to do the platform specific initializations. Platform 1350specific errata workarounds could also be implemented here. The API should 1351preserve the values of callee saved registers x19 to x29. 1352 1353The default implementation doesn't do anything. If a platform needs to override 1354the default implementation, refer to the :ref:`Firmware Design` for general 1355guidelines. 1356 1357Function : plat_disable_acp() 1358~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1359 1360:: 1361 1362 Argument : void 1363 Return : void 1364 1365This API allows a platform to disable the Accelerator Coherency Port (if 1366present) during a cluster power down sequence. The default weak implementation 1367doesn't do anything. Since this API is called during the power down sequence, 1368it has restrictions for stack usage and it can use the registers x0 - x17 as 1369scratch registers. It should preserve the value in x18 register as it is used 1370by the caller to store the return address. 1371 1372Function : plat_error_handler() 1373~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1374 1375:: 1376 1377 Argument : int 1378 Return : void 1379 1380This API is called when the generic code encounters an error situation from 1381which it cannot continue. It allows the platform to perform error reporting or 1382recovery actions (for example, reset the system). This function must not return. 1383 1384The parameter indicates the type of error using standard codes from ``errno.h``. 1385Possible errors reported by the generic code are: 1386 1387- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 1388 Board Boot is enabled) 1389- ``-ENOENT``: the requested image or certificate could not be found or an IO 1390 error was detected 1391- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 1392 error is usually an indication of an incorrect array size 1393 1394The default implementation simply spins. 1395 1396Function : plat_panic_handler() 1397~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1398 1399:: 1400 1401 Argument : void 1402 Return : void 1403 1404This API is called when the generic code encounters an unexpected error 1405situation from which it cannot recover. This function must not return, 1406and must be implemented in assembly because it may be called before the C 1407environment is initialized. 1408 1409.. note:: 1410 The address from where it was called is stored in x30 (Link Register). 1411 The default implementation simply spins. 1412 1413Function : plat_system_reset() 1414~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1415 1416:: 1417 1418 Argument : void 1419 Return : void 1420 1421This function is used by the platform to resets the system. It can be used 1422in any specific use-case where system needs to be resetted. For example, 1423in case of DRTM implementation this function reset the system after 1424writing the DRTM error code in the non-volatile storage. This function 1425never returns. Failure in reset results in panic. 1426 1427Function : plat_get_bl_image_load_info() 1428~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1429 1430:: 1431 1432 Argument : void 1433 Return : bl_load_info_t * 1434 1435This function returns pointer to the list of images that the platform has 1436populated to load. This function is invoked in BL2 to load the 1437BL3xx images. 1438 1439Function : plat_get_next_bl_params() 1440~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1441 1442:: 1443 1444 Argument : void 1445 Return : bl_params_t * 1446 1447This function returns a pointer to the shared memory that the platform has 1448kept aside to pass TF-A related information that next BL image needs. This 1449function is invoked in BL2 to pass this information to the next BL 1450image. 1451 1452Function : plat_get_stack_protector_canary() 1453~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1454 1455:: 1456 1457 Argument : void 1458 Return : u_register_t 1459 1460This function returns a random value that is used to initialize the canary used 1461when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1462value will weaken the protection as the attacker could easily write the right 1463value as part of the attack most of the time. Therefore, it should return a 1464true random number. 1465 1466.. warning:: 1467 For the protection to be effective, the global data need to be placed at 1468 a lower address than the stack bases. Failure to do so would allow an 1469 attacker to overwrite the canary as part of the stack buffer overflow attack. 1470 1471Function : plat_flush_next_bl_params() 1472~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1473 1474:: 1475 1476 Argument : void 1477 Return : void 1478 1479This function flushes to main memory all the image params that are passed to 1480next image. This function is invoked in BL2 to flush this information 1481to the next BL image. 1482 1483Function : plat_log_get_prefix() 1484~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1485 1486:: 1487 1488 Argument : unsigned int 1489 Return : const char * 1490 1491This function defines the prefix string corresponding to the `log_level` to be 1492prepended to all the log output from TF-A. The `log_level` (argument) will 1493correspond to one of the standard log levels defined in debug.h. The platform 1494can override the common implementation to define a different prefix string for 1495the log output. The implementation should be robust to future changes that 1496increase the number of log levels. 1497 1498Function : plat_get_soc_version() 1499~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1500 1501:: 1502 1503 Argument : void 1504 Return : int32_t 1505 1506This function returns soc version which mainly consist of below fields 1507 1508:: 1509 1510 soc_version[30:24] = JEP-106 continuation code for the SiP 1511 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 1512 soc_version[15:0] = Implementation defined SoC ID 1513 1514Function : plat_get_soc_revision() 1515~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1516 1517:: 1518 1519 Argument : void 1520 Return : int32_t 1521 1522This function returns soc revision in below format 1523 1524:: 1525 1526 soc_revision[0:30] = SOC revision of specific SOC 1527 1528Function : plat_is_smccc_feature_available() 1529~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1530 1531:: 1532 1533 Argument : u_register_t 1534 Return : int32_t 1535 1536This function returns SMC_ARCH_CALL_SUCCESS if the platform supports 1537the SMCCC function specified in the argument; otherwise returns 1538SMC_ARCH_CALL_NOT_SUPPORTED. 1539 1540Function : plat_mboot_measure_image() 1541~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1542 1543:: 1544 1545 Argument : unsigned int, image_info_t * 1546 Return : int 1547 1548When the MEASURED_BOOT flag is enabled: 1549 1550- This function measures the given image and records its measurement using 1551 the measured boot backend driver. 1552- On the Arm FVP port, this function measures the given image using its 1553 passed id and information and then records that measurement in the 1554 Event Log buffer. 1555- This function must return 0 on success, a signed integer error code 1556 otherwise. 1557 1558When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 1559 1560Function : plat_mboot_measure_critical_data() 1561~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1562 1563:: 1564 1565 Argument : unsigned int, const void *, size_t 1566 Return : int 1567 1568When the MEASURED_BOOT flag is enabled: 1569 1570- This function measures the given critical data structure and records its 1571 measurement using the measured boot backend driver. 1572- This function must return 0 on success, a signed integer error code 1573 otherwise. 1574 1575When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 1576 1577Function : plat_can_cmo() 1578~~~~~~~~~~~~~~~~~~~~~~~~~ 1579 1580:: 1581 1582 Argument : void 1583 Return : uint64_t 1584 1585When CONDITIONAL_CMO flag is enabled: 1586 1587- This function indicates whether cache management operations should be 1588 performed. It returns 0 if CMOs should be skipped and non-zero 1589 otherwise. 1590- The function must not clobber x1, x2 and x3. It's also not safe to rely on 1591 stack. Otherwise obey AAPCS. 1592 1593Modifications specific to a Boot Loader stage 1594--------------------------------------------- 1595 1596Boot Loader Stage 1 (BL1) 1597------------------------- 1598 1599BL1 implements the reset vector where execution starts from after a cold or 1600warm boot. For each CPU, BL1 is responsible for the following tasks: 1601 1602#. Handling the reset as described in section 2.2 1603 1604#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1605 only this CPU executes the remaining BL1 code, including loading and passing 1606 control to the BL2 stage. 1607 1608#. Identifying and starting the Firmware Update process (if required). 1609 1610#. Loading the BL2 image from non-volatile storage into secure memory at the 1611 address specified by the platform defined constant ``BL2_BASE``. 1612 1613#. Populating a ``meminfo`` structure with the following information in memory, 1614 accessible by BL2 immediately upon entry. 1615 1616 :: 1617 1618 meminfo.total_base = Base address of secure RAM visible to BL2 1619 meminfo.total_size = Size of secure RAM visible to BL2 1620 1621 By default, BL1 places this ``meminfo`` structure at the end of secure 1622 memory visible to BL2. 1623 1624 It is possible for the platform to decide where it wants to place the 1625 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1626 BL2 by overriding the weak default implementation of 1627 ``bl1_plat_handle_post_image_load`` API. 1628 1629The following functions need to be implemented by the platform port to enable 1630BL1 to perform the above tasks. 1631 1632Function : bl1_early_platform_setup() [mandatory] 1633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1634 1635:: 1636 1637 Argument : void 1638 Return : void 1639 1640This function executes with the MMU and data caches disabled. It is only called 1641by the primary CPU. 1642 1643On Arm standard platforms, this function: 1644 1645- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1646 1647- Initializes a UART (PL011 console), which enables access to the ``printf`` 1648 family of functions in BL1. 1649 1650- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1651 the CCI slave interface corresponding to the cluster that includes the 1652 primary CPU. 1653 1654Function : bl1_plat_arch_setup() [mandatory] 1655~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1656 1657:: 1658 1659 Argument : void 1660 Return : void 1661 1662This function performs any platform-specific and architectural setup that the 1663platform requires. Platform-specific setup might include configuration of 1664memory controllers and the interconnect. 1665 1666In Arm standard platforms, this function enables the MMU. 1667 1668This function helps fulfill requirement 2 above. 1669 1670Function : bl1_platform_setup() [mandatory] 1671~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1672 1673:: 1674 1675 Argument : void 1676 Return : void 1677 1678This function executes with the MMU and data caches enabled. It is responsible 1679for performing any remaining platform-specific setup that can occur after the 1680MMU and data cache have been enabled. 1681 1682if support for multiple boot sources is required, it initializes the boot 1683sequence used by plat_try_next_boot_source(). 1684 1685In Arm standard platforms, this function initializes the storage abstraction 1686layer used to load the next bootloader image. 1687 1688This function helps fulfill requirement 4 above. 1689 1690Function : bl1_plat_sec_mem_layout() [mandatory] 1691~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1692 1693:: 1694 1695 Argument : void 1696 Return : meminfo * 1697 1698This function should only be called on the cold boot path. It executes with the 1699MMU and data caches enabled. The pointer returned by this function must point to 1700a ``meminfo`` structure containing the extents and availability of secure RAM for 1701the BL1 stage. 1702 1703:: 1704 1705 meminfo.total_base = Base address of secure RAM visible to BL1 1706 meminfo.total_size = Size of secure RAM visible to BL1 1707 1708This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1709populates a similar structure to tell BL2 the extents of memory available for 1710its own use. 1711 1712This function helps fulfill requirements 4 and 5 above. 1713 1714Function : bl1_plat_prepare_exit() [optional] 1715~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1716 1717:: 1718 1719 Argument : entry_point_info_t * 1720 Return : void 1721 1722This function is called prior to exiting BL1 in response to the 1723``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1724platform specific clean up or bookkeeping operations before transferring 1725control to the next image. It receives the address of the ``entry_point_info_t`` 1726structure passed from BL2. This function runs with MMU disabled. 1727 1728Function : bl1_plat_set_ep_info() [optional] 1729~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1730 1731:: 1732 1733 Argument : unsigned int image_id, entry_point_info_t *ep_info 1734 Return : void 1735 1736This function allows platforms to override ``ep_info`` for the given ``image_id``. 1737 1738The default implementation just returns. 1739 1740Function : bl1_plat_get_next_image_id() [optional] 1741~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1742 1743:: 1744 1745 Argument : void 1746 Return : unsigned int 1747 1748This and the following function must be overridden to enable the FWU feature. 1749 1750BL1 calls this function after platform setup to identify the next image to be 1751loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1752with the normal boot sequence, which loads and executes BL2. If the platform 1753returns a different image id, BL1 assumes that Firmware Update is required. 1754 1755The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1756platforms override this function to detect if firmware update is required, and 1757if so, return the first image in the firmware update process. 1758 1759Function : bl1_plat_get_image_desc() [optional] 1760~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1761 1762:: 1763 1764 Argument : unsigned int image_id 1765 Return : image_desc_t * 1766 1767BL1 calls this function to get the image descriptor information ``image_desc_t`` 1768for the provided ``image_id`` from the platform. 1769 1770The default implementation always returns a common BL2 image descriptor. Arm 1771standard platforms return an image descriptor corresponding to BL2 or one of 1772the firmware update images defined in the Trusted Board Boot Requirements 1773specification. 1774 1775Function : bl1_plat_handle_pre_image_load() [optional] 1776~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1777 1778:: 1779 1780 Argument : unsigned int image_id 1781 Return : int 1782 1783This function can be used by the platforms to update/use image information 1784corresponding to ``image_id``. This function is invoked in BL1, both in cold 1785boot and FWU code path, before loading the image. 1786 1787Function : bl1_plat_handle_post_image_load() [optional] 1788~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1789 1790:: 1791 1792 Argument : unsigned int image_id 1793 Return : int 1794 1795This function can be used by the platforms to update/use image information 1796corresponding to ``image_id``. This function is invoked in BL1, both in cold 1797boot and FWU code path, after loading and authenticating the image. 1798 1799The default weak implementation of this function calculates the amount of 1800Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1801structure at the beginning of this free memory and populates it. The address 1802of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1803information to BL2. 1804 1805Function : bl1_plat_fwu_done() [optional] 1806~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1807 1808:: 1809 1810 Argument : unsigned int image_id, uintptr_t image_src, 1811 unsigned int image_size 1812 Return : void 1813 1814BL1 calls this function when the FWU process is complete. It must not return. 1815The platform may override this function to take platform specific action, for 1816example to initiate the normal boot flow. 1817 1818The default implementation spins forever. 1819 1820Function : bl1_plat_mem_check() [mandatory] 1821~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1822 1823:: 1824 1825 Argument : uintptr_t mem_base, unsigned int mem_size, 1826 unsigned int flags 1827 Return : int 1828 1829BL1 calls this function while handling FWU related SMCs, more specifically when 1830copying or authenticating an image. Its responsibility is to ensure that the 1831region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1832that this memory corresponds to either a secure or non-secure memory region as 1833indicated by the security state of the ``flags`` argument. 1834 1835This function can safely assume that the value resulting from the addition of 1836``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1837overflow. 1838 1839This function must return 0 on success, a non-null error code otherwise. 1840 1841The default implementation of this function asserts therefore platforms must 1842override it when using the FWU feature. 1843 1844Function : bl1_plat_mboot_init() [optional] 1845~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1846 1847:: 1848 1849 Argument : void 1850 Return : void 1851 1852When the MEASURED_BOOT flag is enabled: 1853 1854- This function is used to initialize the backend driver(s) of measured boot. 1855- On the Arm FVP port, this function is used to initialize the Event Log 1856 backend driver, and also to write header information in the Event Log buffer. 1857 1858When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 1859 1860Function : bl1_plat_mboot_finish() [optional] 1861~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1862 1863:: 1864 1865 Argument : void 1866 Return : void 1867 1868When the MEASURED_BOOT flag is enabled: 1869 1870- This function is used to finalize the measured boot backend driver(s), 1871 and also, set the information for the next bootloader component to 1872 extend the measurement if needed. 1873- On the Arm FVP port, this function is used to pass the base address of 1874 the Event Log buffer and its size to BL2 via tb_fw_config to extend the 1875 Event Log buffer with the measurement of various images loaded by BL2. 1876 It results in panic on error. 1877 1878When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 1879 1880Boot Loader Stage 2 (BL2) 1881------------------------- 1882 1883The BL2 stage is executed only by the primary CPU, which is determined in BL1 1884using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1885``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1886``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1887non-volatile storage to secure/non-secure RAM. After all the images are loaded 1888then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1889images to be passed to the next BL image. 1890 1891The following functions must be implemented by the platform port to enable BL2 1892to perform the above tasks. 1893 1894Function : bl2_early_platform_setup2() [mandatory] 1895~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1896 1897:: 1898 1899 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1900 Return : void 1901 1902This function executes with the MMU and data caches disabled. It is only called 1903by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1904are platform specific. 1905 1906On Arm standard platforms, the arguments received are : 1907 1908 arg0 - Points to load address of FW_CONFIG 1909 1910 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1911 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1912 1913On Arm standard platforms, this function also: 1914 1915- Initializes a UART (PL011 console), which enables access to the ``printf`` 1916 family of functions in BL2. 1917 1918- Initializes the storage abstraction layer used to load further bootloader 1919 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1920 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1921 1922Function : bl2_plat_arch_setup() [mandatory] 1923~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1924 1925:: 1926 1927 Argument : void 1928 Return : void 1929 1930This function executes with the MMU and data caches disabled. It is only called 1931by the primary CPU. 1932 1933The purpose of this function is to perform any architectural initialization 1934that varies across platforms. 1935 1936On Arm standard platforms, this function enables the MMU. 1937 1938Function : bl2_platform_setup() [mandatory] 1939~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1940 1941:: 1942 1943 Argument : void 1944 Return : void 1945 1946This function may execute with the MMU and data caches enabled if the platform 1947port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1948called by the primary CPU. 1949 1950The purpose of this function is to perform any platform initialization 1951specific to BL2. 1952 1953In Arm standard platforms, this function performs security setup, including 1954configuration of the TrustZone controller to allow non-secure masters access 1955to most of DRAM. Part of DRAM is reserved for secure world use. 1956 1957Function : bl2_plat_handle_pre_image_load() [optional] 1958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1959 1960:: 1961 1962 Argument : unsigned int 1963 Return : int 1964 1965This function can be used by the platforms to update/use image information 1966for given ``image_id``. This function is currently invoked in BL2 before 1967loading each image. 1968 1969Function : bl2_plat_handle_post_image_load() [optional] 1970~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1971 1972:: 1973 1974 Argument : unsigned int 1975 Return : int 1976 1977This function can be used by the platforms to update/use image information 1978for given ``image_id``. This function is currently invoked in BL2 after 1979loading each image. 1980 1981Function : bl2_plat_preload_setup [optional] 1982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1983 1984:: 1985 1986 Argument : void 1987 Return : void 1988 1989This optional function performs any BL2 platform initialization 1990required before image loading, that is not done later in 1991bl2_platform_setup(). Specifically, if support for multiple 1992boot sources is required, it initializes the boot sequence used by 1993plat_try_next_boot_source(). 1994 1995Function : plat_try_next_boot_source() [optional] 1996~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1997 1998:: 1999 2000 Argument : void 2001 Return : int 2002 2003This optional function passes to the next boot source in the redundancy 2004sequence. 2005 2006This function moves the current boot redundancy source to the next 2007element in the boot sequence. If there are no more boot sources then it 2008must return 0, otherwise it must return 1. The default implementation 2009of this always returns 0. 2010 2011Function : bl2_plat_mboot_init() [optional] 2012~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2013 2014:: 2015 2016 Argument : void 2017 Return : void 2018 2019When the MEASURED_BOOT flag is enabled: 2020 2021- This function is used to initialize the backend driver(s) of measured boot. 2022- On the Arm FVP port, this function is used to initialize the Event Log 2023 backend driver with the Event Log buffer information (base address and 2024 size) received from BL1. It results in panic on error. 2025 2026When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 2027 2028Function : bl2_plat_mboot_finish() [optional] 2029~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2030 2031:: 2032 2033 Argument : void 2034 Return : void 2035 2036When the MEASURED_BOOT flag is enabled: 2037 2038- This function is used to finalize the measured boot backend driver(s), 2039 and also, set the information for the next bootloader component to extend 2040 the measurement if needed. 2041- On the Arm FVP port, this function is used to pass the Event Log buffer 2042 information (base address and size) to non-secure(BL33) and trusted OS(BL32) 2043 via nt_fw and tos_fw config respectively. It results in panic on error. 2044 2045When the MEASURED_BOOT flag is disabled, this function doesn't do anything. 2046 2047Boot Loader Stage 2 (BL2) at EL3 2048-------------------------------- 2049 2050When the platform has a non-TF-A Boot ROM it is desirable to jump 2051directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 2052execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` 2053document for more information. 2054 2055All mandatory functions of BL2 must be implemented, except the functions 2056bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 2057their work is done now by bl2_el3_early_platform_setup and 2058bl2_el3_plat_arch_setup. These functions should generally implement 2059the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 2060 2061 2062Function : bl2_el3_early_platform_setup() [mandatory] 2063~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2064 2065:: 2066 2067 Argument : u_register_t, u_register_t, u_register_t, u_register_t 2068 Return : void 2069 2070This function executes with the MMU and data caches disabled. It is only called 2071by the primary CPU. This function receives four parameters which can be used 2072by the platform to pass any needed information from the Boot ROM to BL2. 2073 2074On Arm standard platforms, this function does the following: 2075 2076- Initializes a UART (PL011 console), which enables access to the ``printf`` 2077 family of functions in BL2. 2078 2079- Initializes the storage abstraction layer used to load further bootloader 2080 images. It is necessary to do this early on platforms with a SCP_BL2 image, 2081 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 2082 2083- Initializes the private variables that define the memory layout used. 2084 2085Function : bl2_el3_plat_arch_setup() [mandatory] 2086~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2087 2088:: 2089 2090 Argument : void 2091 Return : void 2092 2093This function executes with the MMU and data caches disabled. It is only called 2094by the primary CPU. 2095 2096The purpose of this function is to perform any architectural initialization 2097that varies across platforms. 2098 2099On Arm standard platforms, this function enables the MMU. 2100 2101Function : bl2_el3_plat_prepare_exit() [optional] 2102~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2103 2104:: 2105 2106 Argument : void 2107 Return : void 2108 2109This function is called prior to exiting BL2 and run the next image. 2110It should be used to perform platform specific clean up or bookkeeping 2111operations before transferring control to the next image. This function 2112runs with MMU disabled. 2113 2114FWU Boot Loader Stage 2 (BL2U) 2115------------------------------ 2116 2117The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 2118process and is executed only by the primary CPU. BL1 passes control to BL2U at 2119``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 2120 2121#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 2122 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 2123 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 2124 should be copied from. Subsequent handling of the SCP_BL2U image is 2125 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 2126 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 2127 2128#. Any platform specific setup required to perform the FWU process. For 2129 example, Arm standard platforms initialize the TZC controller so that the 2130 normal world can access DDR memory. 2131 2132The following functions must be implemented by the platform port to enable 2133BL2U to perform the tasks mentioned above. 2134 2135Function : bl2u_early_platform_setup() [mandatory] 2136~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2137 2138:: 2139 2140 Argument : meminfo *mem_info, void *plat_info 2141 Return : void 2142 2143This function executes with the MMU and data caches disabled. It is only 2144called by the primary CPU. The arguments to this function is the address 2145of the ``meminfo`` structure and platform specific info provided by BL1. 2146 2147The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 2148private storage as the original memory may be subsequently overwritten by BL2U. 2149 2150On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 2151to extract SCP_BL2U image information, which is then copied into a private 2152variable. 2153 2154Function : bl2u_plat_arch_setup() [mandatory] 2155~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2156 2157:: 2158 2159 Argument : void 2160 Return : void 2161 2162This function executes with the MMU and data caches disabled. It is only 2163called by the primary CPU. 2164 2165The purpose of this function is to perform any architectural initialization 2166that varies across platforms, for example enabling the MMU (since the memory 2167map differs across platforms). 2168 2169Function : bl2u_platform_setup() [mandatory] 2170~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2171 2172:: 2173 2174 Argument : void 2175 Return : void 2176 2177This function may execute with the MMU and data caches enabled if the platform 2178port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 2179called by the primary CPU. 2180 2181The purpose of this function is to perform any platform initialization 2182specific to BL2U. 2183 2184In Arm standard platforms, this function performs security setup, including 2185configuration of the TrustZone controller to allow non-secure masters access 2186to most of DRAM. Part of DRAM is reserved for secure world use. 2187 2188Function : bl2u_plat_handle_scp_bl2u() [optional] 2189~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2190 2191:: 2192 2193 Argument : void 2194 Return : int 2195 2196This function is used to perform any platform-specific actions required to 2197handle the SCP firmware. Typically it transfers the image into SCP memory using 2198a platform-specific protocol and waits until SCP executes it and signals to the 2199Application Processor (AP) for BL2U execution to continue. 2200 2201This function returns 0 on success, a negative error code otherwise. 2202This function is included if SCP_BL2U_BASE is defined. 2203 2204Boot Loader Stage 3-1 (BL31) 2205---------------------------- 2206 2207During cold boot, the BL31 stage is executed only by the primary CPU. This is 2208determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 2209control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 2210CPUs. BL31 executes at EL3 and is responsible for: 2211 2212#. Re-initializing all architectural and platform state. Although BL1 performs 2213 some of this initialization, BL31 remains resident in EL3 and must ensure 2214 that EL3 architectural and platform state is completely initialized. It 2215 should make no assumptions about the system state when it receives control. 2216 2217#. Passing control to a normal world BL image, pre-loaded at a platform- 2218 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 2219 populated by BL2 in memory to do this. 2220 2221#. Providing runtime firmware services. Currently, BL31 only implements a 2222 subset of the Power State Coordination Interface (PSCI) API as a runtime 2223 service. See :ref:`psci_in_bl31` below for details of porting the PSCI 2224 implementation. 2225 2226#. Optionally passing control to the BL32 image, pre-loaded at a platform- 2227 specific address by BL2. BL31 exports a set of APIs that allow runtime 2228 services to specify the security state in which the next image should be 2229 executed and run the corresponding image. On ARM platforms, BL31 uses the 2230 ``bl_params`` list populated by BL2 in memory to do this. 2231 2232If BL31 is a reset vector, It also needs to handle the reset as specified in 2233section 2.2 before the tasks described above. 2234 2235The following functions must be implemented by the platform port to enable BL31 2236to perform the above tasks. 2237 2238Function : bl31_early_platform_setup2() [mandatory] 2239~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2240 2241:: 2242 2243 Argument : u_register_t, u_register_t, u_register_t, u_register_t 2244 Return : void 2245 2246This function executes with the MMU and data caches disabled. It is only called 2247by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 2248platform specific. 2249 2250In Arm standard platforms, the arguments received are : 2251 2252 arg0 - The pointer to the head of `bl_params_t` list 2253 which is list of executable images following BL31, 2254 2255 arg1 - Points to load address of SOC_FW_CONFIG if present 2256 except in case of Arm FVP and Juno platform. 2257 2258 In case of Arm FVP and Juno platform, points to load address 2259 of FW_CONFIG. 2260 2261 arg2 - Points to load address of HW_CONFIG if present 2262 2263 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 2264 used in release builds. 2265 2266The function runs through the `bl_param_t` list and extracts the entry point 2267information for BL32 and BL33. It also performs the following: 2268 2269- Initialize a UART (PL011 console), which enables access to the ``printf`` 2270 family of functions in BL31. 2271 2272- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 2273 CCI slave interface corresponding to the cluster that includes the primary 2274 CPU. 2275 2276Function : bl31_plat_arch_setup() [mandatory] 2277~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2278 2279:: 2280 2281 Argument : void 2282 Return : void 2283 2284This function executes with the MMU and data caches disabled. It is only called 2285by the primary CPU. 2286 2287The purpose of this function is to perform any architectural initialization 2288that varies across platforms. 2289 2290On Arm standard platforms, this function enables the MMU. 2291 2292Function : bl31_platform_setup() [mandatory] 2293~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2294 2295:: 2296 2297 Argument : void 2298 Return : void 2299 2300This function may execute with the MMU and data caches enabled if the platform 2301port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 2302called by the primary CPU. 2303 2304The purpose of this function is to complete platform initialization so that both 2305BL31 runtime services and normal world software can function correctly. 2306 2307On Arm standard platforms, this function does the following: 2308 2309- Initialize the generic interrupt controller. 2310 2311 Depending on the GIC driver selected by the platform, the appropriate GICv2 2312 or GICv3 initialization will be done, which mainly consists of: 2313 2314 - Enable secure interrupts in the GIC CPU interface. 2315 - Disable the legacy interrupt bypass mechanism. 2316 - Configure the priority mask register to allow interrupts of all priorities 2317 to be signaled to the CPU interface. 2318 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 2319 - Target all secure SPIs to CPU0. 2320 - Enable these secure interrupts in the GIC distributor. 2321 - Configure all other interrupts as non-secure. 2322 - Enable signaling of secure interrupts in the GIC distributor. 2323 2324- Enable system-level implementation of the generic timer counter through the 2325 memory mapped interface. 2326 2327- Grant access to the system counter timer module 2328 2329- Initialize the power controller device. 2330 2331 In particular, initialise the locks that prevent concurrent accesses to the 2332 power controller device. 2333 2334Function : bl31_plat_runtime_setup() [optional] 2335~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2336 2337:: 2338 2339 Argument : void 2340 Return : void 2341 2342The purpose of this function is allow the platform to perform any BL31 runtime 2343setup just prior to BL31 exit during cold boot. The default weak 2344implementation of this function will invoke ``console_switch_state()`` to switch 2345console output to consoles marked for use in the ``runtime`` state. 2346 2347Function : bl31_plat_get_next_image_ep_info() [mandatory] 2348~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2349 2350:: 2351 2352 Argument : uint32_t 2353 Return : entry_point_info * 2354 2355This function may execute with the MMU and data caches enabled if the platform 2356port does the necessary initializations in ``bl31_plat_arch_setup()``. 2357 2358This function is called by ``bl31_main()`` to retrieve information provided by 2359BL2 for the next image in the security state specified by the argument. BL31 2360uses this information to pass control to that image in the specified security 2361state. This function must return a pointer to the ``entry_point_info`` structure 2362(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2363should return NULL otherwise. 2364 2365Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1] 2366~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2367 2368:: 2369 2370 Argument : uintptr_t, size_t *, uintptr_t, size_t 2371 Return : int 2372 2373This function returns the Platform attestation token. 2374 2375The parameters of the function are: 2376 2377 arg0 - A pointer to the buffer where the Platform token should be copied by 2378 this function. The buffer must be big enough to hold the Platform 2379 token. 2380 2381 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2382 function returns the platform token length in this parameter. 2383 2384 arg2 - A pointer to the buffer where the challenge object is stored. 2385 2386 arg3 - The length of the challenge object in bytes. Possible values are 32, 2387 48 and 64. 2388 2389The function returns 0 on success, -EINVAL on failure. 2390 2391Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] 2392~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2393 2394:: 2395 2396 Argument : uintptr_t, size_t *, unsigned int 2397 Return : int 2398 2399This function returns the delegated realm attestation key which will be used to 2400sign Realm attestation token. The API currently only supports P-384 ECC curve 2401key. 2402 2403The parameters of the function are: 2404 2405 arg0 - A pointer to the buffer where the attestation key should be copied 2406 by this function. The buffer must be big enough to hold the 2407 attestation key. 2408 2409 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2410 function returns the attestation key length in this parameter. 2411 2412 arg2 - The type of the elliptic curve to which the requested attestation key 2413 belongs. 2414 2415The function returns 0 on success, -EINVAL on failure. 2416 2417Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1] 2418~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2419 2420:: 2421 2422 Argument : uintptr_t * 2423 Return : size_t 2424 2425This function returns the size of the shared area between EL3 and RMM (or 0 on 2426failure). A pointer to the shared area (or a NULL pointer on failure) is stored 2427in the pointer passed as argument. 2428 2429Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1] 2430~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2431 2432:: 2433 2434 Arguments : rmm_manifest_t *manifest 2435 Return : int 2436 2437When ENABLE_RME is enabled, this function populates a boot manifest for the 2438RMM image and stores it in the area specified by manifest. 2439 2440When ENABLE_RME is disabled, this function is not used. 2441 2442Function : bl31_plat_enable_mmu [optional] 2443~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2444 2445:: 2446 2447 Argument : uint32_t 2448 Return : void 2449 2450This function enables the MMU. The boot code calls this function with MMU and 2451caches disabled. This function should program necessary registers to enable 2452translation, and upon return, the MMU on the calling PE must be enabled. 2453 2454The function must honor flags passed in the first argument. These flags are 2455defined by the translation library, and can be found in the file 2456``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2457 2458On DynamIQ systems, this function must not use stack while enabling MMU, which 2459is how the function in xlat table library version 2 is implemented. 2460 2461Function : plat_init_apkey [optional] 2462~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2463 2464:: 2465 2466 Argument : void 2467 Return : uint128_t 2468 2469This function returns the 128-bit value which can be used to program ARMv8.3 2470pointer authentication keys. 2471 2472The value should be obtained from a reliable source of randomness. 2473 2474This function is only needed if ARMv8.3 pointer authentication is used in the 2475Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero. 2476 2477Function : plat_get_syscnt_freq2() [mandatory] 2478~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2479 2480:: 2481 2482 Argument : void 2483 Return : unsigned int 2484 2485This function is used by the architecture setup code to retrieve the counter 2486frequency for the CPU's generic timer. This value will be programmed into the 2487``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2488of the system counter, which is retrieved from the first entry in the frequency 2489modes table. 2490 2491#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 2492~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2493 2494When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2495bytes) aligned to the cache line boundary that should be allocated per-cpu to 2496accommodate all the bakery locks. 2497 2498If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2499calculates the size of the ``.bakery_lock`` input section, aligns it to the 2500nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2501and stores the result in a linker symbol. This constant prevents a platform 2502from relying on the linker and provide a more efficient mechanism for 2503accessing per-cpu bakery lock information. 2504 2505If this constant is defined and its value is not equal to the value 2506calculated by the linker then a link time assertion is raised. A compile time 2507assertion is raised if the value of the constant is not aligned to the cache 2508line boundary. 2509 2510.. _porting_guide_sdei_requirements: 2511 2512SDEI porting requirements 2513~~~~~~~~~~~~~~~~~~~~~~~~~ 2514 2515The |SDEI| dispatcher requires the platform to provide the following macros 2516and functions, of which some are optional, and some others mandatory. 2517 2518Macros 2519...... 2520 2521Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2522^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2523 2524This macro must be defined to the EL3 exception priority level associated with 2525Normal |SDEI| events on the platform. This must have a higher value 2526(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2527 2528Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2529^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2530 2531This macro must be defined to the EL3 exception priority level associated with 2532Critical |SDEI| events on the platform. This must have a lower value 2533(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2534 2535**Note**: |SDEI| exception priorities must be the lowest among Secure 2536priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must 2537be higher than Normal |SDEI| priority. 2538 2539Functions 2540......... 2541 2542Function: int plat_sdei_validate_entry_point() [optional] 2543^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2544 2545:: 2546 2547 Argument: uintptr_t ep, unsigned int client_mode 2548 Return: int 2549 2550This function validates the entry point address of the event handler provided by 2551the client for both event registration and *Complete and Resume* |SDEI| calls. 2552The function ensures that the address is valid in the client translation regime. 2553 2554The second argument is the exception level that the client is executing in. It 2555can be Non-Secure EL1 or Non-Secure EL2. 2556 2557The function must return ``0`` for successful validation, or ``-1`` upon failure. 2558 2559The default implementation always returns ``0``. On Arm platforms, this function 2560translates the entry point address within the client translation regime and 2561further ensures that the resulting physical address is located in Non-secure 2562DRAM. 2563 2564Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2565^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2566 2567:: 2568 2569 Argument: uint64_t 2570 Argument: unsigned int 2571 Return: void 2572 2573|SDEI| specification requires that a PE comes out of reset with the events 2574masked. The client therefore is expected to call ``PE_UNMASK`` to unmask 2575|SDEI| events on the PE. No |SDEI| events can be dispatched until such 2576time. 2577 2578Should a PE receive an interrupt that was bound to an |SDEI| event while the 2579events are masked on the PE, the dispatcher implementation invokes the function 2580``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2581interrupt and the interrupt ID are passed as parameters. 2582 2583The default implementation only prints out a warning message. 2584 2585.. _porting_guide_trng_requirements: 2586 2587TRNG porting requirements 2588~~~~~~~~~~~~~~~~~~~~~~~~~ 2589 2590The |TRNG| backend requires the platform to provide the following values 2591and mandatory functions. 2592 2593Values 2594...... 2595 2596value: uuid_t plat_trng_uuid [mandatory] 2597^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2598 2599This value must be defined to the UUID of the TRNG backend that is specific to 2600the hardware after ``plat_entropy_setup`` function is called. This value must 2601conform to the SMCCC calling convention; The most significant 32 bits of the 2602UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in 2603w0 indicates failure to get a TRNG source. 2604 2605Functions 2606......... 2607 2608Function: void plat_entropy_setup(void) [mandatory] 2609^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2610 2611:: 2612 2613 Argument: none 2614 Return: none 2615 2616This function is expected to do platform-specific initialization of any TRNG 2617hardware. This may include generating a UUID from a hardware-specific seed. 2618 2619Function: bool plat_get_entropy(uint64_t \*out) [mandatory] 2620^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2621 2622:: 2623 2624 Argument: uint64_t * 2625 Return: bool 2626 Out : when the return value is true, the entropy has been written into the 2627 storage pointed to 2628 2629This function writes entropy into storage provided by the caller. If no entropy 2630is available, it must return false and the storage must not be written. 2631 2632.. _psci_in_bl31: 2633 2634Power State Coordination Interface (in BL31) 2635-------------------------------------------- 2636 2637The TF-A implementation of the PSCI API is based around the concept of a 2638*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2639share some state on which power management operations can be performed as 2640specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2641a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2642*power domains* are arranged in a hierarchical tree structure and each 2643*power domain* can be identified in a system by the cpu index of any CPU that 2644is part of that domain and a *power domain level*. A processing element (for 2645example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2646logical grouping of CPUs that share some state, then level 1 is that group of 2647CPUs (for example, a cluster), and level 2 is a group of clusters (for 2648example, the system). More details on the power domain topology and its 2649organization can be found in :ref:`PSCI Power Domain Tree Structure`. 2650 2651BL31's platform initialization code exports a pointer to the platform-specific 2652power management operations required for the PSCI implementation to function 2653correctly. This information is populated in the ``plat_psci_ops`` structure. The 2654PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2655power management operations on the power domains. For example, the target 2656CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2657handler (if present) is called for the CPU power domain. 2658 2659The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2660describe composite power states specific to a platform. The PSCI implementation 2661defines a generic representation of the power-state parameter, which is an 2662array of local power states where each index corresponds to a power domain 2663level. Each entry contains the local power state the power domain at that power 2664level could enter. It depends on the ``validate_power_state()`` handler to 2665convert the power-state parameter (possibly encoding a composite power state) 2666passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2667 2668The following functions form part of platform port of PSCI functionality. 2669 2670Function : plat_psci_stat_accounting_start() [optional] 2671~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2672 2673:: 2674 2675 Argument : const psci_power_state_t * 2676 Return : void 2677 2678This is an optional hook that platforms can implement for residency statistics 2679accounting before entering a low power state. The ``pwr_domain_state`` field of 2680``state_info`` (first argument) can be inspected if stat accounting is done 2681differently at CPU level versus higher levels. As an example, if the element at 2682index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2683state, special hardware logic may be programmed in order to keep track of the 2684residency statistics. For higher levels (array indices > 0), the residency 2685statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2686default implementation will use PMF to capture timestamps. 2687 2688Function : plat_psci_stat_accounting_stop() [optional] 2689~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2690 2691:: 2692 2693 Argument : const psci_power_state_t * 2694 Return : void 2695 2696This is an optional hook that platforms can implement for residency statistics 2697accounting after exiting from a low power state. The ``pwr_domain_state`` field 2698of ``state_info`` (first argument) can be inspected if stat accounting is done 2699differently at CPU level versus higher levels. As an example, if the element at 2700index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2701state, special hardware logic may be programmed in order to keep track of the 2702residency statistics. For higher levels (array indices > 0), the residency 2703statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2704default implementation will use PMF to capture timestamps. 2705 2706Function : plat_psci_stat_get_residency() [optional] 2707~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2708 2709:: 2710 2711 Argument : unsigned int, const psci_power_state_t *, unsigned int 2712 Return : u_register_t 2713 2714This is an optional interface that is is invoked after resuming from a low power 2715state and provides the time spent resident in that low power state by the power 2716domain at a particular power domain level. When a CPU wakes up from suspend, 2717all its parent power domain levels are also woken up. The generic PSCI code 2718invokes this function for each parent power domain that is resumed and it 2719identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2720argument) describes the low power state that the power domain has resumed from. 2721The current CPU is the first CPU in the power domain to resume from the low 2722power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2723CPU in the power domain to suspend and may be needed to calculate the residency 2724for that power domain. 2725 2726Function : plat_get_target_pwr_state() [optional] 2727~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2728 2729:: 2730 2731 Argument : unsigned int, const plat_local_state_t *, unsigned int 2732 Return : plat_local_state_t 2733 2734The PSCI generic code uses this function to let the platform participate in 2735state coordination during a power management operation. The function is passed 2736a pointer to an array of platform specific local power state ``states`` (second 2737argument) which contains the requested power state for each CPU at a particular 2738power domain level ``lvl`` (first argument) within the power domain. The function 2739is expected to traverse this array of upto ``ncpus`` (third argument) and return 2740a coordinated target power state by the comparing all the requested power 2741states. The target power state should not be deeper than any of the requested 2742power states. 2743 2744A weak definition of this API is provided by default wherein it assumes 2745that the platform assigns a local state value in order of increasing depth 2746of the power state i.e. for two power states X & Y, if X < Y 2747then X represents a shallower power state than Y. As a result, the 2748coordinated target local power state for a power domain will be the minimum 2749of the requested local power state values. 2750 2751Function : plat_get_power_domain_tree_desc() [mandatory] 2752~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2753 2754:: 2755 2756 Argument : void 2757 Return : const unsigned char * 2758 2759This function returns a pointer to the byte array containing the power domain 2760topology tree description. The format and method to construct this array are 2761described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI 2762initialization code requires this array to be described by the platform, either 2763statically or dynamically, to initialize the power domain topology tree. In case 2764the array is populated dynamically, then plat_core_pos_by_mpidr() and 2765plat_my_core_pos() should also be implemented suitably so that the topology tree 2766description matches the CPU indices returned by these APIs. These APIs together 2767form the platform interface for the PSCI topology framework. 2768 2769Function : plat_setup_psci_ops() [mandatory] 2770~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2771 2772:: 2773 2774 Argument : uintptr_t, const plat_psci_ops ** 2775 Return : int 2776 2777This function may execute with the MMU and data caches enabled if the platform 2778port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2779called by the primary CPU. 2780 2781This function is called by PSCI initialization code. Its purpose is to let 2782the platform layer know about the warm boot entrypoint through the 2783``sec_entrypoint`` (first argument) and to export handler routines for 2784platform-specific psci power management actions by populating the passed 2785pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2786 2787A description of each member of this structure is given below. Please refer to 2788the Arm FVP specific implementation of these handlers in 2789``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the 2790platform wants to support, the associated operation or operations in this 2791structure must be provided and implemented (Refer section 4 of 2792:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI 2793function in a platform port, the operation should be removed from this 2794structure instead of providing an empty implementation. 2795 2796plat_psci_ops.cpu_standby() 2797........................... 2798 2799Perform the platform-specific actions to enter the standby state for a cpu 2800indicated by the passed argument. This provides a fast path for CPU standby 2801wherein overheads of PSCI state management and lock acquisition is avoided. 2802For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2803the suspend state type specified in the ``power-state`` parameter should be 2804STANDBY and the target power domain level specified should be the CPU. The 2805handler should put the CPU into a low power retention state (usually by 2806issuing a wfi instruction) and ensure that it can be woken up from that 2807state by a normal interrupt. The generic code expects the handler to succeed. 2808 2809plat_psci_ops.pwr_domain_on() 2810............................. 2811 2812Perform the platform specific actions to power on a CPU, specified 2813by the ``MPIDR`` (first argument). The generic code expects the platform to 2814return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 2815 2816plat_psci_ops.pwr_domain_off() 2817.............................. 2818 2819Perform the platform specific actions to prepare to power off the calling CPU 2820and its higher parent power domain levels as indicated by the ``target_state`` 2821(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2822 2823The ``target_state`` encodes the platform coordinated target local power states 2824for the CPU power domain and its parent power domain levels. The handler 2825needs to perform power management operation corresponding to the local state 2826at each power level. 2827 2828For this handler, the local power state for the CPU power domain will be a 2829power down state where as it could be either power down, retention or run state 2830for the higher power domain levels depending on the result of state 2831coordination. The generic code expects the handler to succeed. 2832 2833plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 2834........................................................... 2835 2836This optional function may be used as a performance optimization to replace 2837or complement pwr_domain_suspend() on some platforms. Its calling semantics 2838are identical to pwr_domain_suspend(), except the PSCI implementation only 2839calls this function when suspending to a power down state, and it guarantees 2840that data caches are enabled. 2841 2842When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2843before calling pwr_domain_suspend(). If the target_state corresponds to a 2844power down state and it is safe to perform some or all of the platform 2845specific actions in that function with data caches enabled, it may be more 2846efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2847= 1, data caches remain enabled throughout, and so there is no advantage to 2848moving platform specific actions to this function. 2849 2850plat_psci_ops.pwr_domain_suspend() 2851.................................. 2852 2853Perform the platform specific actions to prepare to suspend the calling 2854CPU and its higher parent power domain levels as indicated by the 2855``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2856API implementation. 2857 2858The ``target_state`` has a similar meaning as described in 2859the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2860target local power states for the CPU power domain and its parent 2861power domain levels. The handler needs to perform power management operation 2862corresponding to the local state at each power level. The generic code 2863expects the handler to succeed. 2864 2865The difference between turning a power domain off versus suspending it is that 2866in the former case, the power domain is expected to re-initialize its state 2867when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2868case, the power domain is expected to save enough state so that it can resume 2869execution by restoring this state when its powered on (see 2870``pwr_domain_suspend_finish()``). 2871 2872When suspending a core, the platform can also choose to power off the GICv3 2873Redistributor and ITS through an implementation-defined sequence. To achieve 2874this safely, the ITS context must be saved first. The architectural part is 2875implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2876sequence is implementation defined and it is therefore the responsibility of 2877the platform code to implement the necessary sequence. Then the GIC 2878Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2879Powering off the Redistributor requires the implementation to support it and it 2880is the responsibility of the platform code to execute the right implementation 2881defined sequence. 2882 2883When a system suspend is requested, the platform can also make use of the 2884``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2885it has saved the context of the Redistributors and ITS of all the cores in the 2886system. The context of the Distributor can be large and may require it to be 2887allocated in a special area if it cannot fit in the platform's global static 2888data, for example in DRAM. The Distributor can then be powered down using an 2889implementation-defined sequence. 2890 2891If the build option ``PSCI_OS_INIT_MODE`` is enabled, the generic code expects 2892the platform to return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or 2893PSCI_E_INVALID_PARAMS as appropriate for any invalid requests. 2894 2895plat_psci_ops.pwr_domain_pwr_down_wfi() 2896....................................... 2897 2898This is an optional function and, if implemented, is expected to perform 2899platform specific actions including the ``wfi`` invocation which allows the 2900CPU to powerdown. Since this function is invoked outside the PSCI locks, 2901the actions performed in this hook must be local to the CPU or the platform 2902must ensure that races between multiple CPUs cannot occur. 2903 2904The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2905operation and it encodes the platform coordinated target local power states for 2906the CPU power domain and its parent power domain levels. This function must 2907not return back to the caller (by calling wfi in an infinite loop to ensure 2908some CPUs power down mitigations work properly). 2909 2910If this function is not implemented by the platform, PSCI generic 2911implementation invokes ``psci_power_down_wfi()`` for power down. 2912 2913plat_psci_ops.pwr_domain_on_finish() 2914.................................... 2915 2916This function is called by the PSCI implementation after the calling CPU is 2917powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2918It performs the platform-specific setup required to initialize enough state for 2919this CPU to enter the normal world and also provide secure runtime firmware 2920services. 2921 2922The ``target_state`` (first argument) is the prior state of the power domains 2923immediately before the CPU was turned on. It indicates which power domains 2924above the CPU might require initialization due to having previously been in 2925low power states. The generic code expects the handler to succeed. 2926 2927plat_psci_ops.pwr_domain_on_finish_late() [optional] 2928........................................................... 2929 2930This optional function is called by the PSCI implementation after the calling 2931CPU is fully powered on with respective data caches enabled. The calling CPU and 2932the associated cluster are guaranteed to be participating in coherency. This 2933function gives the flexibility to perform any platform-specific actions safely, 2934such as initialization or modification of shared data structures, without the 2935overhead of explicit cache maintainace operations. 2936 2937The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` 2938operation. The generic code expects the handler to succeed. 2939 2940plat_psci_ops.pwr_domain_suspend_finish() 2941......................................... 2942 2943This function is called by the PSCI implementation after the calling CPU is 2944powered on and released from reset in response to an asynchronous wakeup 2945event, for example a timer interrupt that was programmed by the CPU during the 2946``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2947setup required to restore the saved state for this CPU to resume execution 2948in the normal world and also provide secure runtime firmware services. 2949 2950The ``target_state`` (first argument) has a similar meaning as described in 2951the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2952to succeed. 2953 2954If the Distributor, Redistributors or ITS have been powered off as part of a 2955suspend, their context must be restored in this function in the reverse order 2956to how they were saved during suspend sequence. 2957 2958plat_psci_ops.system_off() 2959.......................... 2960 2961This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2962call. It performs the platform-specific system poweroff sequence after 2963notifying the Secure Payload Dispatcher. 2964 2965plat_psci_ops.system_reset() 2966............................ 2967 2968This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2969call. It performs the platform-specific system reset sequence after 2970notifying the Secure Payload Dispatcher. 2971 2972plat_psci_ops.validate_power_state() 2973.................................... 2974 2975This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2976call to validate the ``power_state`` parameter of the PSCI API and if valid, 2977populate it in ``req_state`` (second argument) array as power domain level 2978specific local states. If the ``power_state`` is invalid, the platform must 2979return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 2980normal world PSCI client. 2981 2982plat_psci_ops.validate_ns_entrypoint() 2983...................................... 2984 2985This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2986``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2987parameter passed by the normal world. If the ``entry_point`` is invalid, 2988the platform must return PSCI_E_INVALID_ADDRESS as error, which is 2989propagated back to the normal world PSCI client. 2990 2991plat_psci_ops.get_sys_suspend_power_state() 2992........................................... 2993 2994This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2995call to get the ``req_state`` parameter from platform which encodes the power 2996domain level specific local states to suspend to system affinity level. The 2997``req_state`` will be utilized to do the PSCI state coordination and 2998``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2999enter system suspend. 3000 3001plat_psci_ops.get_pwr_lvl_state_idx() 3002..................................... 3003 3004This is an optional function and, if implemented, is invoked by the PSCI 3005implementation to convert the ``local_state`` (first argument) at a specified 3006``pwr_lvl`` (second argument) to an index between 0 and 3007``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 3008supports more than two local power states at each power domain level, that is 3009``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 3010local power states. 3011 3012plat_psci_ops.translate_power_state_by_mpidr() 3013.............................................. 3014 3015This is an optional function and, if implemented, verifies the ``power_state`` 3016(second argument) parameter of the PSCI API corresponding to a target power 3017domain. The target power domain is identified by using both ``MPIDR`` (first 3018argument) and the power domain level encoded in ``power_state``. The power domain 3019level specific local states are to be extracted from ``power_state`` and be 3020populated in the ``output_state`` (third argument) array. The functionality 3021is similar to the ``validate_power_state`` function described above and is 3022envisaged to be used in case the validity of ``power_state`` depend on the 3023targeted power domain. If the ``power_state`` is invalid for the targeted power 3024domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 3025function is not implemented, then the generic implementation relies on 3026``validate_power_state`` function to translate the ``power_state``. 3027 3028This function can also be used in case the platform wants to support local 3029power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 3030APIs as described in Section 5.18 of `PSCI`_. 3031 3032plat_psci_ops.get_node_hw_state() 3033................................. 3034 3035This is an optional function. If implemented this function is intended to return 3036the power state of a node (identified by the first parameter, the ``MPIDR``) in 3037the power domain topology (identified by the second parameter, ``power_level``), 3038as retrieved from a power controller or equivalent component on the platform. 3039Upon successful completion, the implementation must map and return the final 3040status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 3041must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 3042appropriate. 3043 3044Implementations are not expected to handle ``power_levels`` greater than 3045``PLAT_MAX_PWR_LVL``. 3046 3047plat_psci_ops.system_reset2() 3048............................. 3049 3050This is an optional function. If implemented this function is 3051called during the ``SYSTEM_RESET2`` call to perform a reset 3052based on the first parameter ``reset_type`` as specified in 3053`PSCI`_. The parameter ``cookie`` can be used to pass additional 3054reset information. If the ``reset_type`` is not supported, the 3055function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 3056resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 3057and vendor reset can return other PSCI error codes as defined 3058in `PSCI`_. On success this function will not return. 3059 3060plat_psci_ops.write_mem_protect() 3061................................. 3062 3063This is an optional function. If implemented it enables or disables the 3064``MEM_PROTECT`` functionality based on the value of ``val``. 3065A non-zero value enables ``MEM_PROTECT`` and a value of zero 3066disables it. Upon encountering failures it must return a negative value 3067and on success it must return 0. 3068 3069plat_psci_ops.read_mem_protect() 3070................................ 3071 3072This is an optional function. If implemented it returns the current 3073state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 3074failures it must return a negative value and on success it must 3075return 0. 3076 3077plat_psci_ops.mem_protect_chk() 3078............................... 3079 3080This is an optional function. If implemented it checks if a memory 3081region defined by a base address ``base`` and with a size of ``length`` 3082bytes is protected by ``MEM_PROTECT``. If the region is protected 3083then it must return 0, otherwise it must return a negative number. 3084 3085.. _porting_guide_imf_in_bl31: 3086 3087Interrupt Management framework (in BL31) 3088---------------------------------------- 3089 3090BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 3091generated in either security state and targeted to EL1 or EL2 in the non-secure 3092state or EL3/S-EL1 in the secure state. The design of this framework is 3093described in the :ref:`Interrupt Management Framework` 3094 3095A platform should export the following APIs to support the IMF. The following 3096text briefly describes each API and its implementation in Arm standard 3097platforms. The API implementation depends upon the type of interrupt controller 3098present in the platform. Arm standard platform layer supports both 3099`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 3100and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 3101FVP can be configured to use either GICv2 or GICv3 depending on the build flag 3102``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more 3103details). 3104 3105See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. 3106 3107Function : plat_interrupt_type_to_line() [mandatory] 3108~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3109 3110:: 3111 3112 Argument : uint32_t, uint32_t 3113 Return : uint32_t 3114 3115The Arm processor signals an interrupt exception either through the IRQ or FIQ 3116interrupt line. The specific line that is signaled depends on how the interrupt 3117controller (IC) reports different interrupt types from an execution context in 3118either security state. The IMF uses this API to determine which interrupt line 3119the platform IC uses to signal each type of interrupt supported by the framework 3120from a given security state. This API must be invoked at EL3. 3121 3122The first parameter will be one of the ``INTR_TYPE_*`` values (see 3123:ref:`Interrupt Management Framework`) indicating the target type of the 3124interrupt, the second parameter is the security state of the originating 3125execution context. The return result is the bit position in the ``SCR_EL3`` 3126register of the respective interrupt trap: IRQ=1, FIQ=2. 3127 3128In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 3129configured as FIQs and Non-secure interrupts as IRQs from either security 3130state. 3131 3132In the case of Arm standard platforms using GICv3, the interrupt line to be 3133configured depends on the security state of the execution context when the 3134interrupt is signalled and are as follows: 3135 3136- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 3137 NS-EL0/1/2 context. 3138- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 3139 in the NS-EL0/1/2 context. 3140- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 3141 context. 3142 3143Function : plat_ic_get_pending_interrupt_type() [mandatory] 3144~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3145 3146:: 3147 3148 Argument : void 3149 Return : uint32_t 3150 3151This API returns the type of the highest priority pending interrupt at the 3152platform IC. The IMF uses the interrupt type to retrieve the corresponding 3153handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 3154pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 3155``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 3156 3157In the case of Arm standard platforms using GICv2, the *Highest Priority 3158Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 3159the pending interrupt. The type of interrupt depends upon the id value as 3160follows. 3161 3162#. id < 1022 is reported as a S-EL1 interrupt 3163#. id = 1022 is reported as a Non-secure interrupt. 3164#. id = 1023 is reported as an invalid interrupt type. 3165 3166In the case of Arm standard platforms using GICv3, the system register 3167``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 3168is read to determine the id of the pending interrupt. The type of interrupt 3169depends upon the id value as follows. 3170 3171#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 3172#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 3173#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 3174#. All other interrupt id's are reported as EL3 interrupt. 3175 3176Function : plat_ic_get_pending_interrupt_id() [mandatory] 3177~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3178 3179:: 3180 3181 Argument : void 3182 Return : uint32_t 3183 3184This API returns the id of the highest priority pending interrupt at the 3185platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 3186pending. 3187 3188In the case of Arm standard platforms using GICv2, the *Highest Priority 3189Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 3190pending interrupt. The id that is returned by API depends upon the value of 3191the id read from the interrupt controller as follows. 3192 3193#. id < 1022. id is returned as is. 3194#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 3195 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 3196 This id is returned by the API. 3197#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 3198 3199In the case of Arm standard platforms using GICv3, if the API is invoked from 3200EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 3201group 0 Register*, is read to determine the id of the pending interrupt. The id 3202that is returned by API depends upon the value of the id read from the 3203interrupt controller as follows. 3204 3205#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 3206#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 3207 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 3208 Register* is read to determine the id of the group 1 interrupt. This id 3209 is returned by the API as long as it is a valid interrupt id 3210#. If the id is any of the special interrupt identifiers, 3211 ``INTR_ID_UNAVAILABLE`` is returned. 3212 3213When the API invoked from S-EL1 for GICv3 systems, the id read from system 3214register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 3215Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 3216``INTR_ID_UNAVAILABLE`` is returned. 3217 3218Function : plat_ic_acknowledge_interrupt() [mandatory] 3219~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3220 3221:: 3222 3223 Argument : void 3224 Return : uint32_t 3225 3226This API is used by the CPU to indicate to the platform IC that processing of 3227the highest pending interrupt has begun. It should return the raw, unmodified 3228value obtained from the interrupt controller when acknowledging an interrupt. 3229The actual interrupt number shall be extracted from this raw value using the API 3230`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. 3231 3232This function in Arm standard platforms using GICv2, reads the *Interrupt 3233Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 3234priority pending interrupt from pending to active in the interrupt controller. 3235It returns the value read from the ``GICC_IAR``, unmodified. 3236 3237In the case of Arm standard platforms using GICv3, if the API is invoked 3238from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 3239Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 3240reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 3241group 1*. The read changes the state of the highest pending interrupt from 3242pending to active in the interrupt controller. The value read is returned 3243unmodified. 3244 3245The TSP uses this API to start processing of the secure physical timer 3246interrupt. 3247 3248Function : plat_ic_end_of_interrupt() [mandatory] 3249~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3250 3251:: 3252 3253 Argument : uint32_t 3254 Return : void 3255 3256This API is used by the CPU to indicate to the platform IC that processing of 3257the interrupt corresponding to the id (passed as the parameter) has 3258finished. The id should be the same as the id returned by the 3259``plat_ic_acknowledge_interrupt()`` API. 3260 3261Arm standard platforms write the id to the *End of Interrupt Register* 3262(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 3263system register in case of GICv3 depending on where the API is invoked from, 3264EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 3265controller. 3266 3267The TSP uses this API to finish processing of the secure physical timer 3268interrupt. 3269 3270Function : plat_ic_get_interrupt_type() [mandatory] 3271~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3272 3273:: 3274 3275 Argument : uint32_t 3276 Return : uint32_t 3277 3278This API returns the type of the interrupt id passed as the parameter. 3279``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 3280interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 3281returned depending upon how the interrupt has been configured by the platform 3282IC. This API must be invoked at EL3. 3283 3284Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 3285and Non-secure interrupts as Group1 interrupts. It reads the group value 3286corresponding to the interrupt id from the relevant *Interrupt Group Register* 3287(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 3288 3289In the case of Arm standard platforms using GICv3, both the *Interrupt Group 3290Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 3291(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 3292as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 3293 3294Common helper functions 3295----------------------- 3296Function : elx_panic() 3297~~~~~~~~~~~~~~~~~~~~~~ 3298 3299:: 3300 3301 Argument : void 3302 Return : void 3303 3304This API is called from assembly files when reporting a critical failure 3305that has occured in lower EL and is been trapped in EL3. This call 3306**must not** return. 3307 3308Function : el3_panic() 3309~~~~~~~~~~~~~~~~~~~~~~ 3310 3311:: 3312 3313 Argument : void 3314 Return : void 3315 3316This API is called from assembly files when encountering a critical failure that 3317cannot be recovered from. This function assumes that it is invoked from a C 3318runtime environment i.e. valid stack exists. This call **must not** return. 3319 3320Function : panic() 3321~~~~~~~~~~~~~~~~~~ 3322 3323:: 3324 3325 Argument : void 3326 Return : void 3327 3328This API called from C files when encountering a critical failure that cannot 3329be recovered from. This function in turn prints backtrace (if enabled) and calls 3330el3_panic(). This call **must not** return. 3331 3332Crash Reporting mechanism (in BL31) 3333----------------------------------- 3334 3335BL31 implements a crash reporting mechanism which prints the various registers 3336of the CPU to enable quick crash analysis and debugging. This mechanism relies 3337on the platform implementing ``plat_crash_console_init``, 3338``plat_crash_console_putc`` and ``plat_crash_console_flush``. 3339 3340The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 3341implementation of all of them. Platforms may include this file to their 3342makefiles in order to benefit from them. By default, they will cause the crash 3343output to be routed over the normal console infrastructure and get printed on 3344consoles configured to output in crash state. ``console_set_scope()`` can be 3345used to control whether a console is used for crash output. 3346 3347.. note:: 3348 Platforms are responsible for making sure that they only mark consoles for 3349 use in the crash scope that are able to support this, i.e. that are written 3350 in assembly and conform with the register clobber rules for putc() 3351 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. 3352 3353In some cases (such as debugging very early crashes that happen before the 3354normal boot console can be set up), platforms may want to control crash output 3355more explicitly. These platforms may instead provide custom implementations for 3356these. They are executed outside of a C environment and without a stack. Many 3357console drivers provide functions named ``console_xxx_core_init/putc/flush`` 3358that are designed to be used by these functions. See Arm platforms (like juno) 3359for an example of this. 3360 3361Function : plat_crash_console_init [mandatory] 3362~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3363 3364:: 3365 3366 Argument : void 3367 Return : int 3368 3369This API is used by the crash reporting mechanism to initialize the crash 3370console. It must only use the general purpose registers x0 through x7 to do the 3371initialization and returns 1 on success. 3372 3373Function : plat_crash_console_putc [mandatory] 3374~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3375 3376:: 3377 3378 Argument : int 3379 Return : int 3380 3381This API is used by the crash reporting mechanism to print a character on the 3382designated crash console. It must only use general purpose registers x1 and 3383x2 to do its work. The parameter and the return value are in general purpose 3384register x0. 3385 3386Function : plat_crash_console_flush [mandatory] 3387~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3388 3389:: 3390 3391 Argument : void 3392 Return : void 3393 3394This API is used by the crash reporting mechanism to force write of all buffered 3395data on the designated crash console. It should only use general purpose 3396registers x0 through x5 to do its work. 3397 3398.. _External Abort handling and RAS Support: 3399 3400External Abort handling and RAS Support 3401--------------------------------------- 3402 3403Function : plat_ea_handler 3404~~~~~~~~~~~~~~~~~~~~~~~~~~ 3405 3406:: 3407 3408 Argument : int 3409 Argument : uint64_t 3410 Argument : void * 3411 Argument : void * 3412 Argument : uint64_t 3413 Return : void 3414 3415This function is invoked by the RAS framework for the platform to handle an 3416External Abort received at EL3. The intention of the function is to attempt to 3417resolve the cause of External Abort and return; if that's not possible, to 3418initiate orderly shutdown of the system. 3419 3420The first parameter (``int ea_reason``) indicates the reason for External Abort. 3421Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 3422 3423The second parameter (``uint64_t syndrome``) is the respective syndrome 3424presented to EL3 after having received the External Abort. Depending on the 3425nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 3426can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 3427 3428The third parameter (``void *cookie``) is unused for now. The fourth parameter 3429(``void *handle``) is a pointer to the preempted context. The fifth parameter 3430(``uint64_t flags``) indicates the preempted security state. These parameters 3431are received from the top-level exception handler. 3432 3433If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this 3434function iterates through RAS handlers registered by the platform. If any of the 3435RAS handlers resolve the External Abort, no further action is taken. 3436 3437If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers 3438could resolve the External Abort, the default implementation prints an error 3439message, and panics. 3440 3441Function : plat_handle_uncontainable_ea 3442~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3443 3444:: 3445 3446 Argument : int 3447 Argument : uint64_t 3448 Return : void 3449 3450This function is invoked by the RAS framework when an External Abort of 3451Uncontainable type is received at EL3. Due to the critical nature of 3452Uncontainable errors, the intention of this function is to initiate orderly 3453shutdown of the system, and is not expected to return. 3454 3455This function must be implemented in assembly. 3456 3457The first and second parameters are the same as that of ``plat_ea_handler``. 3458 3459The default implementation of this function calls 3460``report_unhandled_exception``. 3461 3462Function : plat_handle_double_fault 3463~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3464 3465:: 3466 3467 Argument : int 3468 Argument : uint64_t 3469 Return : void 3470 3471This function is invoked by the RAS framework when another External Abort is 3472received at EL3 while one is already being handled. I.e., a call to 3473``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 3474this function is to initiate orderly shutdown of the system, and is not expected 3475recover or return. 3476 3477This function must be implemented in assembly. 3478 3479The first and second parameters are the same as that of ``plat_ea_handler``. 3480 3481The default implementation of this function calls 3482``report_unhandled_exception``. 3483 3484Function : plat_handle_el3_ea 3485~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3486 3487:: 3488 3489 Return : void 3490 3491This function is invoked when an External Abort is received while executing in 3492EL3. Due to its critical nature, the intention of this function is to initiate 3493orderly shutdown of the system, and is not expected recover or return. 3494 3495This function must be implemented in assembly. 3496 3497The default implementation of this function calls 3498``report_unhandled_exception``. 3499 3500Function : plat_handle_rng_trap 3501~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3502 3503:: 3504 3505 Argument : uint64_t 3506 Argument : cpu_context_t * 3507 Return : int 3508 3509This function is invoked by BL31's exception handler when there is a synchronous 3510system register trap caused by access to the RNDR or RNDRRS registers. It allows 3511platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to 3512emulate those system registers by returing back some entropy to the lower EL. 3513 3514The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3515syndrome register, which encodes the instruction that was trapped. The interesting 3516information in there is the target register (``get_sysreg_iss_rt()``). 3517 3518The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3519lower exception level, at the time when the execution of the ``mrs`` instruction 3520was trapped. Its content can be changed, to put the entropy into the target 3521register. 3522 3523The return value indicates how to proceed: 3524 3525- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3526- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3527 to the same instruction, so its execution will be repeated. 3528- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3529 to the next instruction. 3530 3531This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP. 3532 3533Build flags 3534----------- 3535 3536There are some build flags which can be defined by the platform to control 3537inclusion or exclusion of certain BL stages from the FIP image. These flags 3538need to be defined in the platform makefile which will get included by the 3539build system. 3540 3541- **NEED_BL33** 3542 By default, this flag is defined ``yes`` by the build system and ``BL33`` 3543 build option should be supplied as a build option. The platform has the 3544 option of excluding the BL33 image in the ``fip`` image by defining this flag 3545 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 3546 are used, this flag will be set to ``no`` automatically. 3547 3548Platform include paths 3549---------------------- 3550 3551Platforms are allowed to add more include paths to be passed to the compiler. 3552The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in 3553particular for the file ``platform_def.h``. 3554 3555Example: 3556 3557.. code:: c 3558 3559 PLAT_INCLUDES += -Iinclude/plat/myplat/include 3560 3561C Library 3562--------- 3563 3564To avoid subtle toolchain behavioral dependencies, the header files provided 3565by the compiler are not used. The software is built with the ``-nostdinc`` flag 3566to ensure no headers are included from the toolchain inadvertently. Instead the 3567required headers are included in the TF-A source tree. The library only 3568contains those C library definitions required by the local implementation. If 3569more functionality is required, the needed library functions will need to be 3570added to the local implementation. 3571 3572Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3573been written specifically for TF-A. Some implementation files have been obtained 3574from `FreeBSD`_, others have been written specifically for TF-A as well. The 3575files can be found in ``include/lib/libc`` and ``lib/libc``. 3576 3577SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 3578can be obtained from http://github.com/freebsd/freebsd. 3579 3580Storage abstraction layer 3581------------------------- 3582 3583In order to improve platform independence and portability a storage abstraction 3584layer is used to load data from non-volatile platform storage. Currently 3585storage access is only required by BL1 and BL2 phases and performed inside the 3586``load_image()`` function in ``bl_common.c``. 3587 3588.. uml:: resources/diagrams/plantuml/io_framework_usage_overview.puml 3589 3590It is mandatory to implement at least one storage driver. For the Arm 3591development platforms the Firmware Image Package (FIP) driver is provided as 3592the default means to load data from storage (see :ref:`firmware_design_fip`). 3593The storage layer is described in the header file 3594``include/drivers/io/io_storage.h``. The implementation of the common library is 3595in ``drivers/io/io_storage.c`` and the driver files are located in 3596``drivers/io/``. 3597 3598.. uml:: resources/diagrams/plantuml/io_arm_class_diagram.puml 3599 3600Each IO driver must provide ``io_dev_*`` structures, as described in 3601``drivers/io/io_driver.h``. These are returned via a mandatory registration 3602function that is called on platform initialization. The semi-hosting driver 3603implementation in ``io_semihosting.c`` can be used as an example. 3604 3605Each platform should register devices and their drivers via the storage 3606abstraction layer. These drivers then need to be initialized by bootloader 3607phases as required in their respective ``blx_platform_setup()`` functions. 3608 3609.. uml:: resources/diagrams/plantuml/io_dev_registration.puml 3610 3611The storage abstraction layer provides mechanisms (``io_dev_init()``) to 3612initialize storage devices before IO operations are called. 3613 3614.. uml:: resources/diagrams/plantuml/io_dev_init_and_check.puml 3615 3616The basic operations supported by the layer 3617include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3618Drivers do not have to implement all operations, but each platform must 3619provide at least one driver for a device capable of supporting generic 3620operations such as loading a bootloader image. 3621 3622The current implementation only allows for known images to be loaded by the 3623firmware. These images are specified by using their identifiers, as defined in 3624``include/plat/common/common_def.h`` (or a separate header file included from 3625there). The platform layer (``plat_get_image_source()``) then returns a reference 3626to a device and a driver-specific ``spec`` which will be understood by the driver 3627to allow access to the image data. 3628 3629The layer is designed in such a way that is it possible to chain drivers with 3630other drivers. For example, file-system drivers may be implemented on top of 3631physical block devices, both represented by IO devices with corresponding 3632drivers. In such a case, the file-system "binding" with the block device may 3633be deferred until the file-system device is initialised. 3634 3635The abstraction currently depends on structures being statically allocated 3636by the drivers and callers, as the system does not yet provide a means of 3637dynamically allocating memory. This may also have the affect of limiting the 3638amount of open resources per driver. 3639 3640-------------- 3641 3642*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* 3643 3644.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 3645.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 3646.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 3647.. _FreeBSD: https://www.freebsd.org 3648.. _SCC: http://www.simple-cc.org/ 3649.. _DRTM: https://developer.arm.com/documentation/den0113/a 3650