1Trusted Firmware-A Porting Guide 2================================ 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Please note that this document has been updated for the new platform API 16as required by the PSCI v1.0 implementation. Please refer to the 17`Migration Guide`_ for the previous platform API. 18 19Porting Trusted Firmware-A (TF-A) to a new platform involves making some 20mandatory and optional modifications for both the cold and warm boot paths. 21Modifications consist of: 22 23- Implementing a platform-specific function or variable, 24- Setting up the execution context in a certain way, or 25- Defining certain constants (for example #defines). 26 27The platform-specific functions and variables are declared in 28`include/plat/common/platform.h`_. The firmware provides a default implementation 29of variables and functions to fulfill the optional requirements. These 30implementations are all weakly defined; they are provided to ease the porting 31effort. Each platform port can override them with its own implementation if the 32default implementation is inadequate. 33 34Platform ports that want to be aligned with standard Arm platforms (for example 35FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the 36corresponding source files in ``plat/arm/common/``. These provide standard 37implementations for some of the required platform porting functions. However, 38using these functions requires the platform port to implement additional 39Arm standard platform porting functions. These additional functions are not 40documented here. 41 42Some modifications are common to all Boot Loader (BL) stages. Section 2 43discusses these in detail. The subsequent sections discuss the remaining 44modifications for each BL stage in detail. 45 46This document should be read in conjunction with the TF-A `User Guide`_. 47 48Common modifications 49-------------------- 50 51This section covers the modifications that should be made by the platform for 52each BL stage to correctly port the firmware stack. They are categorized as 53either mandatory or optional. 54 55Common mandatory modifications 56------------------------------ 57 58A platform port must enable the Memory Management Unit (MMU) as well as the 59instruction and data caches for each BL stage. Setting up the translation 60tables is the responsibility of the platform port because memory maps differ 61across platforms. A memory translation library (see ``lib/xlat_tables/``) is 62provided to help in this setup. 63 64Note that although this library supports non-identity mappings, this is intended 65only for re-mapping peripheral physical addresses and allows platforms with high 66I/O addresses to reduce their virtual address space. All other addresses 67corresponding to code and data must currently use an identity mapping. 68 69Also, the only translation granule size supported in TF-A is 4KB, as various 70parts of the code assume that is the case. It is not possible to switch to 7116 KB or 64 KB granule sizes at the moment. 72 73In Arm standard platforms, each BL stage configures the MMU in the 74platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 75an identity mapping for all addresses. 76 77If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 78block of identity mapped secure memory with Device-nGnRE attributes aligned to 79page boundary (4K) for each BL stage. All sections which allocate coherent 80memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 81section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 82possible for the firmware to place variables in it using the following C code 83directive: 84 85:: 86 87 __section("bakery_lock") 88 89Or alternatively the following assembler code directive: 90 91:: 92 93 .section bakery_lock 94 95The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 96used to allocate any data structures that are accessed both when a CPU is 97executing with its MMU and caches enabled, and when it's running with its MMU 98and caches disabled. Examples are given below. 99 100The following variables, functions and constants must be defined by the platform 101for the firmware to work correctly. 102 103File : platform\_def.h [mandatory] 104~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 105 106Each platform must ensure that a header file of this name is in the system 107include path with the following constants defined. This may require updating the 108list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the Arm development 109platforms, this file is found in ``plat/arm/board/<plat_name>/include/``. 110 111Platform ports may optionally use the file `include/plat/common/common\_def.h`_, 112which provides typical values for some of the constants below. These values are 113likely to be suitable for all platform ports. 114 115Platform ports that want to be aligned with standard Arm platforms (for example 116FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides 117standard values for some of the constants below. However, this requires the 118platform port to define additional platform porting constants in 119``platform_def.h``. These additional constants are not documented here. 120 121- **#define : PLATFORM\_LINKER\_FORMAT** 122 123 Defines the linker format used by the platform, for example 124 ``elf64-littleaarch64``. 125 126- **#define : PLATFORM\_LINKER\_ARCH** 127 128 Defines the processor architecture for the linker by the platform, for 129 example ``aarch64``. 130 131- **#define : PLATFORM\_STACK\_SIZE** 132 133 Defines the normal stack memory available to each CPU. This constant is used 134 by `plat/common/aarch64/platform\_mp\_stack.S`_ and 135 `plat/common/aarch64/platform\_up\_stack.S`_. 136 137- **define : CACHE\_WRITEBACK\_GRANULE** 138 139 Defines the size in bits of the largest cache line across all the cache 140 levels in the platform. 141 142- **#define : FIRMWARE\_WELCOME\_STR** 143 144 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 145 function. 146 147- **#define : PLATFORM\_CORE\_COUNT** 148 149 Defines the total number of CPUs implemented by the platform across all 150 clusters in the system. 151 152- **#define : PLAT\_NUM\_PWR\_DOMAINS** 153 154 Defines the total number of nodes in the power domain topology 155 tree at all the power domain levels used by the platform. 156 This macro is used by the PSCI implementation to allocate 157 data structures to represent power domain topology. 158 159- **#define : PLAT\_MAX\_PWR\_LVL** 160 161 Defines the maximum power domain level that the power management operations 162 should apply to. More often, but not always, the power domain level 163 corresponds to affinity level. This macro allows the PSCI implementation 164 to know the highest power domain level that it should consider for power 165 management operations in the system that the platform implements. For 166 example, the Base AEM FVP implements two clusters with a configurable 167 number of CPUs and it reports the maximum power domain level as 1. 168 169- **#define : PLAT\_MAX\_OFF\_STATE** 170 171 Defines the local power state corresponding to the deepest power down 172 possible at every power domain level in the platform. The local power 173 states for each level may be sparsely allocated between 0 and this value 174 with 0 being reserved for the RUN state. The PSCI implementation uses this 175 value to initialize the local power states of the power domain nodes and 176 to specify the requested power state for a PSCI\_CPU\_OFF call. 177 178- **#define : PLAT\_MAX\_RET\_STATE** 179 180 Defines the local power state corresponding to the deepest retention state 181 possible at every power domain level in the platform. This macro should be 182 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the 183 PSCI implementation to distinguish between retention and power down local 184 power states within PSCI\_CPU\_SUSPEND call. 185 186- **#define : PLAT\_MAX\_PWR\_LVL\_STATES** 187 188 Defines the maximum number of local power states per power domain level 189 that the platform supports. The default value of this macro is 2 since 190 most platforms just support a maximum of two local power states at each 191 power domain level (power-down and retention). If the platform needs to 192 account for more local power states, then it must redefine this macro. 193 194 Currently, this macro is used by the Generic PSCI implementation to size 195 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting. 196 197- **#define : BL1\_RO\_BASE** 198 199 Defines the base address in secure ROM where BL1 originally lives. Must be 200 aligned on a page-size boundary. 201 202- **#define : BL1\_RO\_LIMIT** 203 204 Defines the maximum address in secure ROM that BL1's actual content (i.e. 205 excluding any data section allocated at runtime) can occupy. 206 207- **#define : BL1\_RW\_BASE** 208 209 Defines the base address in secure RAM where BL1's read-write data will live 210 at runtime. Must be aligned on a page-size boundary. 211 212- **#define : BL1\_RW\_LIMIT** 213 214 Defines the maximum address in secure RAM that BL1's read-write data can 215 occupy at runtime. 216 217- **#define : BL2\_BASE** 218 219 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 220 Must be aligned on a page-size boundary. This constant is not applicable 221 when BL2_IN_XIP_MEM is set to '1'. 222 223- **#define : BL2\_LIMIT** 224 225 Defines the maximum address in secure RAM that the BL2 image can occupy. 226 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 227 228- **#define : BL2\_RO\_BASE** 229 230 Defines the base address in secure XIP memory where BL2 RO section originally 231 lives. Must be aligned on a page-size boundary. This constant is only needed 232 when BL2_IN_XIP_MEM is set to '1'. 233 234- **#define : BL2\_RO\_LIMIT** 235 236 Defines the maximum address in secure XIP memory that BL2's actual content 237 (i.e. excluding any data section allocated at runtime) can occupy. This 238 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 239 240- **#define : BL2\_RW\_BASE** 241 242 Defines the base address in secure RAM where BL2's read-write data will live 243 at runtime. Must be aligned on a page-size boundary. This constant is only 244 needed when BL2_IN_XIP_MEM is set to '1'. 245 246- **#define : BL2\_RW\_LIMIT** 247 248 Defines the maximum address in secure RAM that BL2's read-write data can 249 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 250 to '1'. 251 252- **#define : BL31\_BASE** 253 254 Defines the base address in secure RAM where BL2 loads the BL31 binary 255 image. Must be aligned on a page-size boundary. 256 257- **#define : BL31\_LIMIT** 258 259 Defines the maximum address in secure RAM that the BL31 image can occupy. 260 261For every image, the platform must define individual identifiers that will be 262used by BL1 or BL2 to load the corresponding image into memory from non-volatile 263storage. For the sake of performance, integer numbers will be used as 264identifiers. The platform will use those identifiers to return the relevant 265information about the image to be loaded (file handler, load address, 266authentication information, etc.). The following image identifiers are 267mandatory: 268 269- **#define : BL2\_IMAGE\_ID** 270 271 BL2 image identifier, used by BL1 to load BL2. 272 273- **#define : BL31\_IMAGE\_ID** 274 275 BL31 image identifier, used by BL2 to load BL31. 276 277- **#define : BL33\_IMAGE\_ID** 278 279 BL33 image identifier, used by BL2 to load BL33. 280 281If Trusted Board Boot is enabled, the following certificate identifiers must 282also be defined: 283 284- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID** 285 286 BL2 content certificate identifier, used by BL1 to load the BL2 content 287 certificate. 288 289- **#define : TRUSTED\_KEY\_CERT\_ID** 290 291 Trusted key certificate identifier, used by BL2 to load the trusted key 292 certificate. 293 294- **#define : SOC\_FW\_KEY\_CERT\_ID** 295 296 BL31 key certificate identifier, used by BL2 to load the BL31 key 297 certificate. 298 299- **#define : SOC\_FW\_CONTENT\_CERT\_ID** 300 301 BL31 content certificate identifier, used by BL2 to load the BL31 content 302 certificate. 303 304- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID** 305 306 BL33 key certificate identifier, used by BL2 to load the BL33 key 307 certificate. 308 309- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID** 310 311 BL33 content certificate identifier, used by BL2 to load the BL33 content 312 certificate. 313 314- **#define : FWU\_CERT\_ID** 315 316 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the 317 FWU content certificate. 318 319- **#define : PLAT\_CRYPTOCELL\_BASE** 320 321 This defines the base address of Arm® TrustZone® CryptoCell and must be 322 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 323 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 324 set. 325 326If the AP Firmware Updater Configuration image, BL2U is used, the following 327must also be defined: 328 329- **#define : BL2U\_BASE** 330 331 Defines the base address in secure memory where BL1 copies the BL2U binary 332 image. Must be aligned on a page-size boundary. 333 334- **#define : BL2U\_LIMIT** 335 336 Defines the maximum address in secure memory that the BL2U image can occupy. 337 338- **#define : BL2U\_IMAGE\_ID** 339 340 BL2U image identifier, used by BL1 to fetch an image descriptor 341 corresponding to BL2U. 342 343If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following 344must also be defined: 345 346- **#define : SCP\_BL2U\_IMAGE\_ID** 347 348 SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor 349 corresponding to SCP\_BL2U. 350 NOTE: TF-A does not provide source code for this image. 351 352If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must 353also be defined: 354 355- **#define : NS\_BL1U\_BASE** 356 357 Defines the base address in non-secure ROM where NS\_BL1U executes. 358 Must be aligned on a page-size boundary. 359 NOTE: TF-A does not provide source code for this image. 360 361- **#define : NS\_BL1U\_IMAGE\_ID** 362 363 NS\_BL1U image identifier, used by BL1 to fetch an image descriptor 364 corresponding to NS\_BL1U. 365 366If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also 367be defined: 368 369- **#define : NS\_BL2U\_BASE** 370 371 Defines the base address in non-secure memory where NS\_BL2U executes. 372 Must be aligned on a page-size boundary. 373 NOTE: TF-A does not provide source code for this image. 374 375- **#define : NS\_BL2U\_IMAGE\_ID** 376 377 NS\_BL2U image identifier, used by BL1 to fetch an image descriptor 378 corresponding to NS\_BL2U. 379 380For the the Firmware update capability of TRUSTED BOARD BOOT, the following 381macros may also be defined: 382 383- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES** 384 385 Total number of images that can be loaded simultaneously. If the platform 386 doesn't specify any value, it defaults to 10. 387 388If a SCP\_BL2 image is supported by the platform, the following constants must 389also be defined: 390 391- **#define : SCP\_BL2\_IMAGE\_ID** 392 393 SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory 394 from platform storage before being transfered to the SCP. 395 396- **#define : SCP\_FW\_KEY\_CERT\_ID** 397 398 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key 399 certificate (mandatory when Trusted Board Boot is enabled). 400 401- **#define : SCP\_FW\_CONTENT\_CERT\_ID** 402 403 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2 404 content certificate (mandatory when Trusted Board Boot is enabled). 405 406If a BL32 image is supported by the platform, the following constants must 407also be defined: 408 409- **#define : BL32\_IMAGE\_ID** 410 411 BL32 image identifier, used by BL2 to load BL32. 412 413- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID** 414 415 BL32 key certificate identifier, used by BL2 to load the BL32 key 416 certificate (mandatory when Trusted Board Boot is enabled). 417 418- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID** 419 420 BL32 content certificate identifier, used by BL2 to load the BL32 content 421 certificate (mandatory when Trusted Board Boot is enabled). 422 423- **#define : BL32\_BASE** 424 425 Defines the base address in secure memory where BL2 loads the BL32 binary 426 image. Must be aligned on a page-size boundary. 427 428- **#define : BL32\_LIMIT** 429 430 Defines the maximum address that the BL32 image can occupy. 431 432If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 433platform, the following constants must also be defined: 434 435- **#define : TSP\_SEC\_MEM\_BASE** 436 437 Defines the base address of the secure memory used by the TSP image on the 438 platform. This must be at the same address or below ``BL32_BASE``. 439 440- **#define : TSP\_SEC\_MEM\_SIZE** 441 442 Defines the size of the secure memory used by the BL32 image on the 443 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate 444 the memory required by the BL32 image, defined by ``BL32_BASE`` and 445 ``BL32_LIMIT``. 446 447- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER** 448 449 Defines the ID of the secure physical generic timer interrupt used by the 450 TSP's interrupt handling code. 451 452If the platform port uses the translation table library code, the following 453constants must also be defined: 454 455- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC** 456 457 Optional flag that can be set per-image to enable the dynamic allocation of 458 regions even when the MMU is enabled. If not defined, only static 459 functionality will be available, if defined and set to 1 it will also 460 include the dynamic functionality. 461 462- **#define : MAX\_XLAT\_TABLES** 463 464 Defines the maximum number of translation tables that are allocated by the 465 translation table library code. To minimize the amount of runtime memory 466 used, choose the smallest value needed to map the required virtual addresses 467 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 468 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 469 as well. 470 471- **#define : MAX\_MMAP\_REGIONS** 472 473 Defines the maximum number of regions that are allocated by the translation 474 table library code. A region consists of physical base address, virtual base 475 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 476 defined in the ``mmap_region_t`` structure. The platform defines the regions 477 that should be mapped. Then, the translation table library will create the 478 corresponding tables and descriptors at runtime. To minimize the amount of 479 runtime memory used, choose the smallest value needed to register the 480 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 481 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 482 the dynamic regions as well. 483 484- **#define : ADDR\_SPACE\_SIZE** 485 486 Defines the total size of the address space in bytes. For example, for a 32 487 bit address space, this value should be ``(1ULL << 32)``. This definition is 488 now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and 489 ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead. 490 491- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE** 492 493 Defines the total size of the virtual address space in bytes. For example, 494 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 495 496- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE** 497 498 Defines the total size of the physical address space in bytes. For example, 499 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 500 501If the platform port uses the IO storage framework, the following constants 502must also be defined: 503 504- **#define : MAX\_IO\_DEVICES** 505 506 Defines the maximum number of registered IO devices. Attempting to register 507 more devices than this value using ``io_register_device()`` will fail with 508 -ENOMEM. 509 510- **#define : MAX\_IO\_HANDLES** 511 512 Defines the maximum number of open IO handles. Attempting to open more IO 513 entities than this value using ``io_open()`` will fail with -ENOMEM. 514 515- **#define : MAX\_IO\_BLOCK\_DEVICES** 516 517 Defines the maximum number of registered IO block devices. Attempting to 518 register more devices this value using ``io_dev_open()`` will fail 519 with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES. 520 With this macro, multiple block devices could be supported at the same 521 time. 522 523If the platform needs to allocate data within the per-cpu data framework in 524BL31, it should define the following macro. Currently this is only required if 525the platform decides not to use the coherent memory section by undefining the 526``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 527required memory within the the per-cpu data to minimize wastage. 528 529- **#define : PLAT\_PCPU\_DATA\_SIZE** 530 531 Defines the memory (in bytes) to be reserved within the per-cpu data 532 structure for use by the platform layer. 533 534The following constants are optional. They should be defined when the platform 535memory layout implies some image overlaying like in Arm standard platforms. 536 537- **#define : BL31\_PROGBITS\_LIMIT** 538 539 Defines the maximum address in secure RAM that the BL31's progbits sections 540 can occupy. 541 542- **#define : TSP\_PROGBITS\_LIMIT** 543 544 Defines the maximum address that the TSP's progbits sections can occupy. 545 546If the platform port uses the PL061 GPIO driver, the following constant may 547optionally be defined: 548 549- **PLAT\_PL061\_MAX\_GPIOS** 550 Maximum number of GPIOs required by the platform. This allows control how 551 much memory is allocated for PL061 GPIO controllers. The default value is 552 553 #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS)) 554 555If the platform port uses the partition driver, the following constant may 556optionally be defined: 557 558- **PLAT\_PARTITION\_MAX\_ENTRIES** 559 Maximum number of partition entries required by the platform. This allows 560 control how much memory is allocated for partition entries. The default 561 value is 128. 562 `For example, define the build flag in platform.mk`_: 563 PLAT\_PARTITION\_MAX\_ENTRIES := 12 564 $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES)) 565 566The following constant is optional. It should be defined to override the default 567behaviour of the ``assert()`` function (for example, to save memory). 568 569- **PLAT\_LOG\_LEVEL\_ASSERT** 570 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 571 ``assert()`` prints the name of the file, the line number and the asserted 572 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 573 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 574 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 575 defined, it defaults to ``LOG_LEVEL``. 576 577If the platform port uses the Activity Monitor Unit, the following constants 578may be defined: 579 580- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK** 581 This mask reflects the set of group counters that should be enabled. The 582 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 583 can be at most 0xffff. If the platform does not define this mask, no group 1 584 counters are enabled. If the platform defines this mask, the following 585 constant needs to also be defined. 586 587- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS** 588 This value is used to allocate an array to save and restore the counters 589 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 590 This value should be equal to the highest bit position set in the 591 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 592 593File : plat\_macros.S [mandatory] 594~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 595 596Each platform must ensure a file of this name is in the system include path with 597the following macro defined. In the Arm development platforms, this file is 598found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 599 600- **Macro : plat\_crash\_print\_regs** 601 602 This macro allows the crash reporting routine to print relevant platform 603 registers in case of an unhandled exception in BL31. This aids in debugging 604 and this macro can be defined to be empty in case register reporting is not 605 desired. 606 607 For instance, GIC or interconnect registers may be helpful for 608 troubleshooting. 609 610Handling Reset 611-------------- 612 613BL1 by default implements the reset vector where execution starts from a cold 614or warm boot. BL31 can be optionally set as a reset vector using the 615``RESET_TO_BL31`` make variable. 616 617For each CPU, the reset vector code is responsible for the following tasks: 618 619#. Distinguishing between a cold boot and a warm boot. 620 621#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 622 the CPU is placed in a platform-specific state until the primary CPU 623 performs the necessary steps to remove it from this state. 624 625#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 626 specific address in the BL31 image in the same processor mode as it was 627 when released from reset. 628 629The following functions need to be implemented by the platform port to enable 630reset vector code to perform the above tasks. 631 632Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0] 633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 634 635:: 636 637 Argument : void 638 Return : uintptr_t 639 640This function is called with the MMU and caches disabled 641(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 642distinguishing between a warm and cold reset for the current CPU using 643platform-specific means. If it's a warm reset, then it returns the warm 644reset entrypoint point provided to ``plat_setup_psci_ops()`` during 645BL31 initialization. If it's a cold reset then this function must return zero. 646 647This function does not follow the Procedure Call Standard used by the 648Application Binary Interface for the Arm 64-bit architecture. The caller should 649not assume that callee saved registers are preserved across a call to this 650function. 651 652This function fulfills requirement 1 and 3 listed above. 653 654Note that for platforms that support programming the reset address, it is 655expected that a CPU will start executing code directly at the right address, 656both on a cold and warm reset. In this case, there is no need to identify the 657type of reset nor to query the warm reset entrypoint. Therefore, implementing 658this function is not required on such platforms. 659 660Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 661~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 662 663:: 664 665 Argument : void 666 667This function is called with the MMU and data caches disabled. It is responsible 668for placing the executing secondary CPU in a platform-specific state until the 669primary CPU performs the necessary actions to bring it out of that state and 670allow entry into the OS. This function must not return. 671 672In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 673itself off. The primary CPU is responsible for powering up the secondary CPUs 674when normal world software requires them. When booting an EL3 payload instead, 675they stay powered on and are put in a holding pen until their mailbox gets 676populated. 677 678This function fulfills requirement 2 above. 679 680Note that for platforms that can't release secondary CPUs out of reset, only the 681primary CPU will execute the cold boot code. Therefore, implementing this 682function is not required on such platforms. 683 684Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 685~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 686 687:: 688 689 Argument : void 690 Return : unsigned int 691 692This function identifies whether the current CPU is the primary CPU or a 693secondary CPU. A return value of zero indicates that the CPU is not the 694primary CPU, while a non-zero return value indicates that the CPU is the 695primary CPU. 696 697Note that for platforms that can't release secondary CPUs out of reset, only the 698primary CPU will execute the cold boot code. Therefore, there is no need to 699distinguish between primary and secondary CPUs and implementing this function is 700not required. 701 702Function : platform\_mem\_init() [mandatory] 703~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 704 705:: 706 707 Argument : void 708 Return : void 709 710This function is called before any access to data is made by the firmware, in 711order to carry out any essential memory initialization. 712 713Function: plat\_get\_rotpk\_info() 714~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 715 716:: 717 718 Argument : void *, void **, unsigned int *, unsigned int * 719 Return : int 720 721This function is mandatory when Trusted Board Boot is enabled. It returns a 722pointer to the ROTPK stored in the platform (or a hash of it) and its length. 723The ROTPK must be encoded in DER format according to the following ASN.1 724structure: 725 726:: 727 728 AlgorithmIdentifier ::= SEQUENCE { 729 algorithm OBJECT IDENTIFIER, 730 parameters ANY DEFINED BY algorithm OPTIONAL 731 } 732 733 SubjectPublicKeyInfo ::= SEQUENCE { 734 algorithm AlgorithmIdentifier, 735 subjectPublicKey BIT STRING 736 } 737 738In case the function returns a hash of the key: 739 740:: 741 742 DigestInfo ::= SEQUENCE { 743 digestAlgorithm AlgorithmIdentifier, 744 digest OCTET STRING 745 } 746 747The function returns 0 on success. Any other value is treated as error by the 748Trusted Board Boot. The function also reports extra information related 749to the ROTPK in the flags parameter: 750 751:: 752 753 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 754 hash. 755 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 756 verification while the platform ROTPK is not deployed. 757 When this flag is set, the function does not need to 758 return a platform ROTPK, and the authentication 759 framework uses the ROTPK in the certificate without 760 verifying it against the platform value. This flag 761 must not be used in a deployed production environment. 762 763Function: plat\_get\_nv\_ctr() 764~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 765 766:: 767 768 Argument : void *, unsigned int * 769 Return : int 770 771This function is mandatory when Trusted Board Boot is enabled. It returns the 772non-volatile counter value stored in the platform in the second argument. The 773cookie in the first argument may be used to select the counter in case the 774platform provides more than one (for example, on platforms that use the default 775TBBR CoT, the cookie will correspond to the OID values defined in 776TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID). 777 778The function returns 0 on success. Any other value means the counter value could 779not be retrieved from the platform. 780 781Function: plat\_set\_nv\_ctr() 782~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 783 784:: 785 786 Argument : void *, unsigned int 787 Return : int 788 789This function is mandatory when Trusted Board Boot is enabled. It sets a new 790counter value in the platform. The cookie in the first argument may be used to 791select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is 792the updated counter value to be written to the NV counter. 793 794The function returns 0 on success. Any other value means the counter value could 795not be updated. 796 797Function: plat\_set\_nv\_ctr2() 798~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 799 800:: 801 802 Argument : void *, const auth_img_desc_t *, unsigned int 803 Return : int 804 805This function is optional when Trusted Board Boot is enabled. If this 806interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 807first argument passed is a cookie and is typically used to 808differentiate between a Non Trusted NV Counter and a Trusted NV 809Counter. The second argument is a pointer to an authentication image 810descriptor and may be used to decide if the counter is allowed to be 811updated or not. The third argument is the updated counter value to 812be written to the NV counter. 813 814The function returns 0 on success. Any other value means the counter value 815either could not be updated or the authentication image descriptor indicates 816that it is not allowed to be updated. 817 818Common mandatory function modifications 819--------------------------------------- 820 821The following functions are mandatory functions which need to be implemented 822by the platform port. 823 824Function : plat\_my\_core\_pos() 825~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 826 827:: 828 829 Argument : void 830 Return : unsigned int 831 832This funtion returns the index of the calling CPU which is used as a 833CPU-specific linear index into blocks of memory (for example while allocating 834per-CPU stacks). This function will be invoked very early in the 835initialization sequence which mandates that this function should be 836implemented in assembly and should not rely on the avalability of a C 837runtime environment. This function can clobber x0 - x8 and must preserve 838x9 - x29. 839 840This function plays a crucial role in the power domain topology framework in 841PSCI and details of this can be found in `Power Domain Topology Design`_. 842 843Function : plat\_core\_pos\_by\_mpidr() 844~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 845 846:: 847 848 Argument : u_register_t 849 Return : int 850 851This function validates the ``MPIDR`` of a CPU and converts it to an index, 852which can be used as a CPU-specific linear index into blocks of memory. In 853case the ``MPIDR`` is invalid, this function returns -1. This function will only 854be invoked by BL31 after the power domain topology is initialized and can 855utilize the C runtime environment. For further details about how TF-A 856represents the power domain topology and how this relates to the linear CPU 857index, please refer `Power Domain Topology Design`_. 858 859Common optional modifications 860----------------------------- 861 862The following are helper functions implemented by the firmware that perform 863common platform-specific tasks. A platform may choose to override these 864definitions. 865 866Function : plat\_set\_my\_stack() 867~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 868 869:: 870 871 Argument : void 872 Return : void 873 874This function sets the current stack pointer to the normal memory stack that 875has been allocated for the current CPU. For BL images that only require a 876stack for the primary CPU, the UP version of the function is used. The size 877of the stack allocated to each CPU is specified by the platform defined 878constant ``PLATFORM_STACK_SIZE``. 879 880Common implementations of this function for the UP and MP BL images are 881provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 882`plat/common/aarch64/platform\_mp\_stack.S`_ 883 884Function : plat\_get\_my\_stack() 885~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 886 887:: 888 889 Argument : void 890 Return : uintptr_t 891 892This function returns the base address of the normal memory stack that 893has been allocated for the current CPU. For BL images that only require a 894stack for the primary CPU, the UP version of the function is used. The size 895of the stack allocated to each CPU is specified by the platform defined 896constant ``PLATFORM_STACK_SIZE``. 897 898Common implementations of this function for the UP and MP BL images are 899provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 900`plat/common/aarch64/platform\_mp\_stack.S`_ 901 902Function : plat\_report\_exception() 903~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 904 905:: 906 907 Argument : unsigned int 908 Return : void 909 910A platform may need to report various information about its status when an 911exception is taken, for example the current exception level, the CPU security 912state (secure/non-secure), the exception type, and so on. This function is 913called in the following circumstances: 914 915- In BL1, whenever an exception is taken. 916- In BL2, whenever an exception is taken. 917 918The default implementation doesn't do anything, to avoid making assumptions 919about the way the platform displays its status information. 920 921For AArch64, this function receives the exception type as its argument. 922Possible values for exceptions types are listed in the 923`include/common/bl\_common.h`_ header file. Note that these constants are not 924related to any architectural exception code; they are just a TF-A convention. 925 926For AArch32, this function receives the exception mode as its argument. 927Possible values for exception modes are listed in the 928`include/lib/aarch32/arch.h`_ header file. 929 930Function : plat\_reset\_handler() 931~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 932 933:: 934 935 Argument : void 936 Return : void 937 938A platform may need to do additional initialization after reset. This function 939allows the platform to do the platform specific intializations. Platform 940specific errata workarounds could also be implemented here. The api should 941preserve the values of callee saved registers x19 to x29. 942 943The default implementation doesn't do anything. If a platform needs to override 944the default implementation, refer to the `Firmware Design`_ for general 945guidelines. 946 947Function : plat\_disable\_acp() 948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 949 950:: 951 952 Argument : void 953 Return : void 954 955This API allows a platform to disable the Accelerator Coherency Port (if 956present) during a cluster power down sequence. The default weak implementation 957doesn't do anything. Since this API is called during the power down sequence, 958it has restrictions for stack usage and it can use the registers x0 - x17 as 959scratch registers. It should preserve the value in x18 register as it is used 960by the caller to store the return address. 961 962Function : plat\_error\_handler() 963~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 964 965:: 966 967 Argument : int 968 Return : void 969 970This API is called when the generic code encounters an error situation from 971which it cannot continue. It allows the platform to perform error reporting or 972recovery actions (for example, reset the system). This function must not return. 973 974The parameter indicates the type of error using standard codes from ``errno.h``. 975Possible errors reported by the generic code are: 976 977- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 978 Board Boot is enabled) 979- ``-ENOENT``: the requested image or certificate could not be found or an IO 980 error was detected 981- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 982 error is usually an indication of an incorrect array size 983 984The default implementation simply spins. 985 986Function : plat\_panic\_handler() 987~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 988 989:: 990 991 Argument : void 992 Return : void 993 994This API is called when the generic code encounters an unexpected error 995situation from which it cannot recover. This function must not return, 996and must be implemented in assembly because it may be called before the C 997environment is initialized. 998 999Note: The address from where it was called is stored in x30 (Link Register). 1000The default implementation simply spins. 1001 1002Function : plat\_get\_bl\_image\_load\_info() 1003~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1004 1005:: 1006 1007 Argument : void 1008 Return : bl_load_info_t * 1009 1010This function returns pointer to the list of images that the platform has 1011populated to load. This function is currently invoked in BL2 to load the 1012BL3xx images, when LOAD\_IMAGE\_V2 is enabled. 1013 1014Function : plat\_get\_next\_bl\_params() 1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1016 1017:: 1018 1019 Argument : void 1020 Return : bl_params_t * 1021 1022This function returns a pointer to the shared memory that the platform has 1023kept aside to pass TF-A related information that next BL image needs. This 1024function is currently invoked in BL2 to pass this information to the next BL 1025image, when LOAD\_IMAGE\_V2 is enabled. 1026 1027Function : plat\_get\_stack\_protector\_canary() 1028~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1029 1030:: 1031 1032 Argument : void 1033 Return : u_register_t 1034 1035This function returns a random value that is used to initialize the canary used 1036when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable 1037value will weaken the protection as the attacker could easily write the right 1038value as part of the attack most of the time. Therefore, it should return a 1039true random number. 1040 1041Note: For the protection to be effective, the global data need to be placed at 1042a lower address than the stack bases. Failure to do so would allow an attacker 1043to overwrite the canary as part of the stack buffer overflow attack. 1044 1045Function : plat\_flush\_next\_bl\_params() 1046~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1047 1048:: 1049 1050 Argument : void 1051 Return : void 1052 1053This function flushes to main memory all the image params that are passed to 1054next image. This function is currently invoked in BL2 to flush this information 1055to the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1056 1057Function : plat\_log\_get\_prefix() 1058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1059 1060:: 1061 1062 Argument : unsigned int 1063 Return : const char * 1064 1065This function defines the prefix string corresponding to the `log_level` to be 1066prepended to all the log output from TF-A. The `log_level` (argument) will 1067correspond to one of the standard log levels defined in debug.h. The platform 1068can override the common implementation to define a different prefix string for 1069the log output. The implementation should be robust to future changes that 1070increase the number of log levels. 1071 1072Function : plat\_get\_mbedtls\_heap() 1073~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1074 1075:: 1076 1077 Arguments : void **heap_addr, size_t *heap_size 1078 Return : int 1079 1080This function is invoked during Mbed TLS library initialisation to get 1081a heap, by means of a starting address and a size. This heap will then be used 1082internally by the Mbed TLS library. The heap is requested from the current BL 1083stage, i.e. the current BL image inside which Mbed TLS is used. 1084 1085In the default implementation a heap is statically allocated inside every image 1086(i.e. every BL stage) that utilises Mbed TLS. So, in this case, the function 1087simply returns the address and size of this "pre-allocated" heap. However, by 1088overriding the default implementation, platforms have the potential to optimise 1089memory usage. For example, on some Arm platforms, the Mbed TLS heap is shared 1090between BL1 and BL2 stages and, thus, the necessary space is not reserved 1091twice. 1092 1093On success the function should return 0 and a negative error code otherwise. 1094 1095Modifications specific to a Boot Loader stage 1096--------------------------------------------- 1097 1098Boot Loader Stage 1 (BL1) 1099------------------------- 1100 1101BL1 implements the reset vector where execution starts from after a cold or 1102warm boot. For each CPU, BL1 is responsible for the following tasks: 1103 1104#. Handling the reset as described in section 2.2 1105 1106#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1107 only this CPU executes the remaining BL1 code, including loading and passing 1108 control to the BL2 stage. 1109 1110#. Identifying and starting the Firmware Update process (if required). 1111 1112#. Loading the BL2 image from non-volatile storage into secure memory at the 1113 address specified by the platform defined constant ``BL2_BASE``. 1114 1115#. Populating a ``meminfo`` structure with the following information in memory, 1116 accessible by BL2 immediately upon entry. 1117 1118 :: 1119 1120 meminfo.total_base = Base address of secure RAM visible to BL2 1121 meminfo.total_size = Size of secure RAM visible to BL2 1122 meminfo.free_base = Base address of secure RAM available for 1123 allocation to BL2 1124 meminfo.free_size = Size of secure RAM available for allocation to BL2 1125 1126 By default, BL1 places this ``meminfo`` structure at the beginning of the 1127 free memory available for its use. Since BL1 cannot allocate memory 1128 dynamically at the moment, its free memory will be available for BL2's use 1129 as-is. However, this means that BL2 must read the ``meminfo`` structure 1130 before it starts using its free memory (this is discussed in Section 3.2). 1131 1132 It is possible for the platform to decide where it wants to place the 1133 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1134 BL2 by overriding the weak default implementation of 1135 ``bl1_plat_handle_post_image_load`` API. 1136 1137The following functions need to be implemented by the platform port to enable 1138BL1 to perform the above tasks. 1139 1140Function : bl1\_early\_platform\_setup() [mandatory] 1141~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1142 1143:: 1144 1145 Argument : void 1146 Return : void 1147 1148This function executes with the MMU and data caches disabled. It is only called 1149by the primary CPU. 1150 1151On Arm standard platforms, this function: 1152 1153- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1154 1155- Initializes a UART (PL011 console), which enables access to the ``printf`` 1156 family of functions in BL1. 1157 1158- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1159 the CCI slave interface corresponding to the cluster that includes the 1160 primary CPU. 1161 1162Function : bl1\_plat\_arch\_setup() [mandatory] 1163~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1164 1165:: 1166 1167 Argument : void 1168 Return : void 1169 1170This function performs any platform-specific and architectural setup that the 1171platform requires. Platform-specific setup might include configuration of 1172memory controllers and the interconnect. 1173 1174In Arm standard platforms, this function enables the MMU. 1175 1176This function helps fulfill requirement 2 above. 1177 1178Function : bl1\_platform\_setup() [mandatory] 1179~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1180 1181:: 1182 1183 Argument : void 1184 Return : void 1185 1186This function executes with the MMU and data caches enabled. It is responsible 1187for performing any remaining platform-specific setup that can occur after the 1188MMU and data cache have been enabled. 1189 1190if support for multiple boot sources is required, it initializes the boot 1191sequence used by plat\_try\_next\_boot\_source(). 1192 1193In Arm standard platforms, this function initializes the storage abstraction 1194layer used to load the next bootloader image. 1195 1196This function helps fulfill requirement 4 above. 1197 1198Function : bl1\_plat\_sec\_mem\_layout() [mandatory] 1199~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1200 1201:: 1202 1203 Argument : void 1204 Return : meminfo * 1205 1206This function should only be called on the cold boot path. It executes with the 1207MMU and data caches enabled. The pointer returned by this function must point to 1208a ``meminfo`` structure containing the extents and availability of secure RAM for 1209the BL1 stage. 1210 1211:: 1212 1213 meminfo.total_base = Base address of secure RAM visible to BL1 1214 meminfo.total_size = Size of secure RAM visible to BL1 1215 meminfo.free_base = Base address of secure RAM available for allocation 1216 to BL1 1217 meminfo.free_size = Size of secure RAM available for allocation to BL1 1218 1219This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1220populates a similar structure to tell BL2 the extents of memory available for 1221its own use. 1222 1223This function helps fulfill requirements 4 and 5 above. 1224 1225Function : bl1\_plat\_prepare\_exit() [optional] 1226~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1227 1228:: 1229 1230 Argument : entry_point_info_t * 1231 Return : void 1232 1233This function is called prior to exiting BL1 in response to the 1234``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1235platform specific clean up or bookkeeping operations before transferring 1236control to the next image. It receives the address of the ``entry_point_info_t`` 1237structure passed from BL2. This function runs with MMU disabled. 1238 1239Function : bl1\_plat\_set\_ep\_info() [optional] 1240~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1241 1242:: 1243 1244 Argument : unsigned int image_id, entry_point_info_t *ep_info 1245 Return : void 1246 1247This function allows platforms to override ``ep_info`` for the given ``image_id``. 1248 1249The default implementation just returns. 1250 1251Function : bl1\_plat\_get\_next\_image\_id() [optional] 1252~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1253 1254:: 1255 1256 Argument : void 1257 Return : unsigned int 1258 1259This and the following function must be overridden to enable the FWU feature. 1260 1261BL1 calls this function after platform setup to identify the next image to be 1262loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1263with the normal boot sequence, which loads and executes BL2. If the platform 1264returns a different image id, BL1 assumes that Firmware Update is required. 1265 1266The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1267platforms override this function to detect if firmware update is required, and 1268if so, return the first image in the firmware update process. 1269 1270Function : bl1\_plat\_get\_image\_desc() [optional] 1271~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1272 1273:: 1274 1275 Argument : unsigned int image_id 1276 Return : image_desc_t * 1277 1278BL1 calls this function to get the image descriptor information ``image_desc_t`` 1279for the provided ``image_id`` from the platform. 1280 1281The default implementation always returns a common BL2 image descriptor. Arm 1282standard platforms return an image descriptor corresponding to BL2 or one of 1283the firmware update images defined in the Trusted Board Boot Requirements 1284specification. 1285 1286Function : bl1\_plat\_handle\_pre\_image\_load() [optional] 1287~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1288 1289:: 1290 1291 Argument : unsigned int image_id 1292 Return : int 1293 1294This function can be used by the platforms to update/use image information 1295corresponding to ``image_id``. This function is invoked in BL1, both in cold 1296boot and FWU code path, before loading the image. 1297 1298Function : bl1\_plat\_handle\_post\_image\_load() [optional] 1299~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1300 1301:: 1302 1303 Argument : unsigned int image_id 1304 Return : int 1305 1306This function can be used by the platforms to update/use image information 1307corresponding to ``image_id``. This function is invoked in BL1, both in cold 1308boot and FWU code path, after loading and authenticating the image. 1309 1310The default weak implementation of this function calculates the amount of 1311Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1312structure at the beginning of this free memory and populates it. The address 1313of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1314information to BL2. 1315 1316Function : bl1\_plat\_fwu\_done() [optional] 1317~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1318 1319:: 1320 1321 Argument : unsigned int image_id, uintptr_t image_src, 1322 unsigned int image_size 1323 Return : void 1324 1325BL1 calls this function when the FWU process is complete. It must not return. 1326The platform may override this function to take platform specific action, for 1327example to initiate the normal boot flow. 1328 1329The default implementation spins forever. 1330 1331Function : bl1\_plat\_mem\_check() [mandatory] 1332~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1333 1334:: 1335 1336 Argument : uintptr_t mem_base, unsigned int mem_size, 1337 unsigned int flags 1338 Return : int 1339 1340BL1 calls this function while handling FWU related SMCs, more specifically when 1341copying or authenticating an image. Its responsibility is to ensure that the 1342region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1343that this memory corresponds to either a secure or non-secure memory region as 1344indicated by the security state of the ``flags`` argument. 1345 1346This function can safely assume that the value resulting from the addition of 1347``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1348overflow. 1349 1350This function must return 0 on success, a non-null error code otherwise. 1351 1352The default implementation of this function asserts therefore platforms must 1353override it when using the FWU feature. 1354 1355Boot Loader Stage 2 (BL2) 1356------------------------- 1357 1358The BL2 stage is executed only by the primary CPU, which is determined in BL1 1359using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1360``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for: 1361 1362#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform 1363 provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of 1364 the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function. 1365 The platform also defines the address in memory where SCP\_BL2 is loaded 1366 through the optional constant ``SCP_BL2_BASE``. BL2 uses this information 1367 to determine if there is enough memory to load the SCP\_BL2 image. 1368 Subsequent handling of the SCP\_BL2 image is platform-specific and is 1369 implemented in the ``bl2_plat_handle_scp_bl2()`` function. 1370 If ``SCP_BL2_BASE`` is not defined then this step is not performed. 1371 1372#. Loading the BL31 binary image into secure RAM from non-volatile storage. To 1373 load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it 1374 by BL1. This structure allows BL2 to calculate how much secure RAM is 1375 available for its use. The platform also defines the address in secure RAM 1376 where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this 1377 information to determine if there is enough memory to load the BL31 image. 1378 1379#. (Optional) Loading the BL32 binary image (if present) from platform 1380 provided non-volatile storage. To load the BL32 image, BL2 makes use of 1381 the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function. 1382 The platform also defines the address in memory where BL32 is loaded 1383 through the optional constant ``BL32_BASE``. BL2 uses this information 1384 to determine if there is enough memory to load the BL32 image. 1385 If ``BL32_BASE`` is not defined then this and the next step is not performed. 1386 1387#. (Optional) Arranging to pass control to the BL32 image (if present) that 1388 has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info`` 1389 structure in memory provided by the platform with information about how 1390 BL31 should pass control to the BL32 image. 1391 1392#. (Optional) Loading the normal world BL33 binary image (if not loaded by 1393 other means) into non-secure DRAM from platform storage and arranging for 1394 BL31 to pass control to this image. This address is determined using the 1395 ``plat_get_ns_image_entrypoint()`` function described below. 1396 1397#. BL2 populates an ``entry_point_info`` structure in memory provided by the 1398 platform with information about how BL31 should pass control to the 1399 other BL images. 1400 1401The following functions must be implemented by the platform port to enable BL2 1402to perform the above tasks. 1403 1404Function : bl2\_early\_platform\_setup() [mandatory] 1405~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1406 1407:: 1408 1409 Argument : meminfo * 1410 Return : void 1411 1412This function executes with the MMU and data caches disabled. It is only called 1413by the primary CPU. The arguments to this function is the address of the 1414``meminfo`` structure populated by BL1. 1415 1416The platform may copy the contents of the ``meminfo`` structure into a private 1417variable as the original memory may be subsequently overwritten by BL2. The 1418copied structure is made available to all BL2 code through the 1419``bl2_plat_sec_mem_layout()`` function. 1420 1421On Arm standard platforms, this function also: 1422 1423- Initializes a UART (PL011 console), which enables access to the ``printf`` 1424 family of functions in BL2. 1425 1426- Initializes the storage abstraction layer used to load further bootloader 1427 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1428 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1429 1430Function : bl2\_plat\_arch\_setup() [mandatory] 1431~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1432 1433:: 1434 1435 Argument : void 1436 Return : void 1437 1438This function executes with the MMU and data caches disabled. It is only called 1439by the primary CPU. 1440 1441The purpose of this function is to perform any architectural initialization 1442that varies across platforms. 1443 1444On Arm standard platforms, this function enables the MMU. 1445 1446Function : bl2\_platform\_setup() [mandatory] 1447~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1448 1449:: 1450 1451 Argument : void 1452 Return : void 1453 1454This function may execute with the MMU and data caches enabled if the platform 1455port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1456called by the primary CPU. 1457 1458The purpose of this function is to perform any platform initialization 1459specific to BL2. 1460 1461In Arm standard platforms, this function performs security setup, including 1462configuration of the TrustZone controller to allow non-secure masters access 1463to most of DRAM. Part of DRAM is reserved for secure world use. 1464 1465Function : bl2\_plat\_sec\_mem\_layout() [mandatory] 1466~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1467 1468:: 1469 1470 Argument : void 1471 Return : meminfo * 1472 1473This function should only be called on the cold boot path. It may execute with 1474the MMU and data caches enabled if the platform port does the necessary 1475initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU. 1476 1477The purpose of this function is to return a pointer to a ``meminfo`` structure 1478populated with the extents of secure RAM available for BL2 to use. See 1479``bl2_early_platform_setup()`` above. 1480 1481Following functions are optionally used only when LOAD\_IMAGE\_V2 is enabled. 1482 1483Function : bl2\_plat\_handle\_pre\_image\_load() [optional] 1484~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1485 1486:: 1487 1488 Argument : unsigned int 1489 Return : int 1490 1491This function can be used by the platforms to update/use image information 1492for given ``image_id``. This function is currently invoked in BL2 before 1493loading each image, when LOAD\_IMAGE\_V2 is enabled. 1494 1495Function : bl2\_plat\_handle\_post\_image\_load() [optional] 1496~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1497 1498:: 1499 1500 Argument : unsigned int 1501 Return : int 1502 1503This function can be used by the platforms to update/use image information 1504for given ``image_id``. This function is currently invoked in BL2 after 1505loading each image, when LOAD\_IMAGE\_V2 is enabled. 1506 1507Following functions are required only when LOAD\_IMAGE\_V2 is disabled. 1508 1509Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory] 1510~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1511 1512:: 1513 1514 Argument : meminfo * 1515 Return : void 1516 1517This function is used to get the memory limits where BL2 can load the 1518SCP\_BL2 image. The meminfo provided by this is used by load\_image() to 1519validate whether the SCP\_BL2 image can be loaded within the given 1520memory from the given base. 1521 1522Function : bl2\_plat\_handle\_scp\_bl2() [mandatory] 1523~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1524 1525:: 1526 1527 Argument : image_info * 1528 Return : int 1529 1530This function is called after loading SCP\_BL2 image and it is used to perform 1531any platform-specific actions required to handle the SCP firmware. Typically it 1532transfers the image into SCP memory using a platform-specific protocol and waits 1533until SCP executes it and signals to the Application Processor (AP) for BL2 1534execution to continue. 1535 1536This function returns 0 on success, a negative error code otherwise. 1537 1538Function : bl2\_plat\_get\_bl31\_params() [mandatory] 1539~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1540 1541:: 1542 1543 Argument : void 1544 Return : bl31_params * 1545 1546BL2 platform code needs to return a pointer to a ``bl31_params`` structure it 1547will use for passing information to BL31. The ``bl31_params`` structure carries 1548the following information. 1549- Header describing the version information for interpreting the bl31\_param 1550structure 1551- Information about executing the BL33 image in the ``bl33_ep_info`` field 1552- Information about executing the BL32 image in the ``bl32_ep_info`` field 1553- Information about the type and extents of BL31 image in the 1554``bl31_image_info`` field 1555- Information about the type and extents of BL32 image in the 1556``bl32_image_info`` field 1557- Information about the type and extents of BL33 image in the 1558``bl33_image_info`` field 1559 1560The memory pointed by this structure and its sub-structures should be 1561accessible from BL31 initialisation code. BL31 might choose to copy the 1562necessary content, or maintain the structures until BL33 is initialised. 1563 1564Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory] 1565~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1566 1567:: 1568 1569 Argument : void 1570 Return : entry_point_info * 1571 1572BL2 platform code returns a pointer which is used to populate the entry point 1573information for BL31 entry point. The location pointed by it should be 1574accessible from BL1 while processing the synchronous exception to run to BL31. 1575 1576In Arm standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem 1577structure in BL2 memory. 1578 1579Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory] 1580~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1581 1582:: 1583 1584 Argument : image_info *, entry_point_info * 1585 Return : void 1586 1587In the normal boot flow, this function is called after loading BL31 image and 1588it can be used to overwrite the entry point set by loader and also set the 1589security state and SPSR which represents the entry point system state for BL31. 1590 1591When booting an EL3 payload instead, this function is called after populating 1592its entry point address and can be used for the same purpose for the payload 1593image. It receives a null pointer as its first argument in this case. 1594 1595Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory] 1596~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1597 1598:: 1599 1600 Argument : image_info *, entry_point_info * 1601 Return : void 1602 1603This function is called after loading BL32 image and it can be used to 1604overwrite the entry point set by loader and also set the security state 1605and SPSR which represents the entry point system state for BL32. 1606 1607Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory] 1608~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1609 1610:: 1611 1612 Argument : image_info *, entry_point_info * 1613 Return : void 1614 1615This function is called after loading BL33 image and it can be used to 1616overwrite the entry point set by loader and also set the security state 1617and SPSR which represents the entry point system state for BL33. 1618 1619In the preloaded BL33 alternative boot flow, this function is called after 1620populating its entry point address. It is passed a null pointer as its first 1621argument in this case. 1622 1623Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory] 1624~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1625 1626:: 1627 1628 Argument : meminfo * 1629 Return : void 1630 1631This function is used to get the memory limits where BL2 can load the 1632BL32 image. The meminfo provided by this is used by load\_image() to 1633validate whether the BL32 image can be loaded with in the given 1634memory from the given base. 1635 1636Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory] 1637~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1638 1639:: 1640 1641 Argument : meminfo * 1642 Return : void 1643 1644This function is used to get the memory limits where BL2 can load the 1645BL33 image. The meminfo provided by this is used by load\_image() to 1646validate whether the BL33 image can be loaded with in the given 1647memory from the given base. 1648 1649This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1650build options are used. 1651 1652Function : bl2\_plat\_flush\_bl31\_params() [mandatory] 1653~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1654 1655:: 1656 1657 Argument : void 1658 Return : void 1659 1660Once BL2 has populated all the structures that needs to be read by BL1 1661and BL31 including the bl31\_params structures and its sub-structures, 1662the bl31\_ep\_info structure and any platform specific data. It flushes 1663all these data to the main memory so that it is available when we jump to 1664later Bootloader stages with MMU off 1665 1666Function : plat\_get\_ns\_image\_entrypoint() [mandatory] 1667~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1668 1669:: 1670 1671 Argument : void 1672 Return : uintptr_t 1673 1674As previously described, BL2 is responsible for arranging for control to be 1675passed to a normal world BL image through BL31. This function returns the 1676entrypoint of that image, which BL31 uses to jump to it. 1677 1678BL2 is responsible for loading the normal world BL33 image (e.g. UEFI). 1679 1680This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1681build options are used. 1682 1683Function : bl2\_plat\_preload\_setup [optional] 1684~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1685 1686:: 1687 1688 Argument : void 1689 Return : void 1690 1691This optional function performs any BL2 platform initialization 1692required before image loading, that is not done later in 1693bl2\_platform\_setup(). Specifically, if support for multiple 1694boot sources is required, it initializes the boot sequence used by 1695plat\_try\_next\_boot\_source(). 1696 1697Function : plat\_try\_next\_boot\_source() [optional] 1698~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1699 1700:: 1701 1702 Argument : void 1703 Return : int 1704 1705This optional function passes to the next boot source in the redundancy 1706sequence. 1707 1708This function moves the current boot redundancy source to the next 1709element in the boot sequence. If there are no more boot sources then it 1710must return 0, otherwise it must return 1. The default implementation 1711of this always returns 0. 1712 1713Boot Loader Stage 2 (BL2) at EL3 1714-------------------------------- 1715 1716When the platform has a non-TF-A Boot ROM it is desirable to jump 1717directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1718execute at EL3 instead of executing at EL1. Refer to the `Firmware 1719Design`_ for more information. 1720 1721All mandatory functions of BL2 must be implemented, except the functions 1722bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because 1723their work is done now by bl2\_el3\_early\_platform\_setup and 1724bl2\_el3\_plat\_arch\_setup. These functions should generally implement 1725the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined. 1726 1727 1728Function : bl2\_el3\_early\_platform\_setup() [mandatory] 1729~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1730 1731:: 1732 1733 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1734 Return : void 1735 1736This function executes with the MMU and data caches disabled. It is only called 1737by the primary CPU. This function receives four parameters which can be used 1738by the platform to pass any needed information from the Boot ROM to BL2. 1739 1740On Arm standard platforms, this function does the following: 1741 1742- Initializes a UART (PL011 console), which enables access to the ``printf`` 1743 family of functions in BL2. 1744 1745- Initializes the storage abstraction layer used to load further bootloader 1746 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1747 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1748 1749- Initializes the private variables that define the memory layout used. 1750 1751Function : bl2\_el3\_plat\_arch\_setup() [mandatory] 1752~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1753 1754:: 1755 1756 Argument : void 1757 Return : void 1758 1759This function executes with the MMU and data caches disabled. It is only called 1760by the primary CPU. 1761 1762The purpose of this function is to perform any architectural initialization 1763that varies across platforms. 1764 1765On Arm standard platforms, this function enables the MMU. 1766 1767Function : bl2\_el3\_plat\_prepare\_exit() [optional] 1768~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1769 1770:: 1771 1772 Argument : void 1773 Return : void 1774 1775This function is called prior to exiting BL2 and run the next image. 1776It should be used to perform platform specific clean up or bookkeeping 1777operations before transferring control to the next image. This function 1778runs with MMU disabled. 1779 1780FWU Boot Loader Stage 2 (BL2U) 1781------------------------------ 1782 1783The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1784process and is executed only by the primary CPU. BL1 passes control to BL2U at 1785``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1786 1787#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure 1788 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1. 1789 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U 1790 should be copied from. Subsequent handling of the SCP\_BL2U image is 1791 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1792 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1793 1794#. Any platform specific setup required to perform the FWU process. For 1795 example, Arm standard platforms initialize the TZC controller so that the 1796 normal world can access DDR memory. 1797 1798The following functions must be implemented by the platform port to enable 1799BL2U to perform the tasks mentioned above. 1800 1801Function : bl2u\_early\_platform\_setup() [mandatory] 1802~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1803 1804:: 1805 1806 Argument : meminfo *mem_info, void *plat_info 1807 Return : void 1808 1809This function executes with the MMU and data caches disabled. It is only 1810called by the primary CPU. The arguments to this function is the address 1811of the ``meminfo`` structure and platform specific info provided by BL1. 1812 1813The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1814private storage as the original memory may be subsequently overwritten by BL2U. 1815 1816On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1817to extract SCP\_BL2U image information, which is then copied into a private 1818variable. 1819 1820Function : bl2u\_plat\_arch\_setup() [mandatory] 1821~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1822 1823:: 1824 1825 Argument : void 1826 Return : void 1827 1828This function executes with the MMU and data caches disabled. It is only 1829called by the primary CPU. 1830 1831The purpose of this function is to perform any architectural initialization 1832that varies across platforms, for example enabling the MMU (since the memory 1833map differs across platforms). 1834 1835Function : bl2u\_platform\_setup() [mandatory] 1836~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1837 1838:: 1839 1840 Argument : void 1841 Return : void 1842 1843This function may execute with the MMU and data caches enabled if the platform 1844port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1845called by the primary CPU. 1846 1847The purpose of this function is to perform any platform initialization 1848specific to BL2U. 1849 1850In Arm standard platforms, this function performs security setup, including 1851configuration of the TrustZone controller to allow non-secure masters access 1852to most of DRAM. Part of DRAM is reserved for secure world use. 1853 1854Function : bl2u\_plat\_handle\_scp\_bl2u() [optional] 1855~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1856 1857:: 1858 1859 Argument : void 1860 Return : int 1861 1862This function is used to perform any platform-specific actions required to 1863handle the SCP firmware. Typically it transfers the image into SCP memory using 1864a platform-specific protocol and waits until SCP executes it and signals to the 1865Application Processor (AP) for BL2U execution to continue. 1866 1867This function returns 0 on success, a negative error code otherwise. 1868This function is included if SCP\_BL2U\_BASE is defined. 1869 1870Boot Loader Stage 3-1 (BL31) 1871---------------------------- 1872 1873During cold boot, the BL31 stage is executed only by the primary CPU. This is 1874determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1875control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1876CPUs. BL31 executes at EL3 and is responsible for: 1877 1878#. Re-initializing all architectural and platform state. Although BL1 performs 1879 some of this initialization, BL31 remains resident in EL3 and must ensure 1880 that EL3 architectural and platform state is completely initialized. It 1881 should make no assumptions about the system state when it receives control. 1882 1883#. Passing control to a normal world BL image, pre-loaded at a platform- 1884 specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2 1885 populated in memory to do this. 1886 1887#. Providing runtime firmware services. Currently, BL31 only implements a 1888 subset of the Power State Coordination Interface (PSCI) API as a runtime 1889 service. See Section 3.3 below for details of porting the PSCI 1890 implementation. 1891 1892#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1893 specific address by BL2. BL31 exports a set of apis that allow runtime 1894 services to specify the security state in which the next image should be 1895 executed and run the corresponding image. BL31 uses the ``entry_point_info`` 1896 structure populated by BL2 to do this. 1897 1898If BL31 is a reset vector, It also needs to handle the reset as specified in 1899section 2.2 before the tasks described above. 1900 1901The following functions must be implemented by the platform port to enable BL31 1902to perform the above tasks. 1903 1904Function : bl31\_early\_platform\_setup() [mandatory] 1905~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1906 1907:: 1908 1909 Argument : bl31_params *, void * 1910 Return : void 1911 1912This function executes with the MMU and data caches disabled. It is only called 1913by the primary CPU. The arguments to this function are: 1914 1915- The address of the ``bl31_params`` structure populated by BL2. 1916- An opaque pointer that the platform may use as needed. 1917 1918The platform can copy the contents of the ``bl31_params`` structure and its 1919sub-structures into private variables if the original memory may be 1920subsequently overwritten by BL31 and similarly the ``void *`` pointing 1921to the platform data also needs to be saved. 1922 1923In Arm standard platforms, BL2 passes a pointer to a ``bl31_params`` structure 1924in BL2 memory. BL31 copies the information in this pointer to internal data 1925structures. It also performs the following: 1926 1927- Initialize a UART (PL011 console), which enables access to the ``printf`` 1928 family of functions in BL31. 1929 1930- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1931 CCI slave interface corresponding to the cluster that includes the primary 1932 CPU. 1933 1934Function : bl31\_plat\_arch\_setup() [mandatory] 1935~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1936 1937:: 1938 1939 Argument : void 1940 Return : void 1941 1942This function executes with the MMU and data caches disabled. It is only called 1943by the primary CPU. 1944 1945The purpose of this function is to perform any architectural initialization 1946that varies across platforms. 1947 1948On Arm standard platforms, this function enables the MMU. 1949 1950Function : bl31\_platform\_setup() [mandatory] 1951~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1952 1953:: 1954 1955 Argument : void 1956 Return : void 1957 1958This function may execute with the MMU and data caches enabled if the platform 1959port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1960called by the primary CPU. 1961 1962The purpose of this function is to complete platform initialization so that both 1963BL31 runtime services and normal world software can function correctly. 1964 1965On Arm standard platforms, this function does the following: 1966 1967- Initialize the generic interrupt controller. 1968 1969 Depending on the GIC driver selected by the platform, the appropriate GICv2 1970 or GICv3 initialization will be done, which mainly consists of: 1971 1972 - Enable secure interrupts in the GIC CPU interface. 1973 - Disable the legacy interrupt bypass mechanism. 1974 - Configure the priority mask register to allow interrupts of all priorities 1975 to be signaled to the CPU interface. 1976 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1977 - Target all secure SPIs to CPU0. 1978 - Enable these secure interrupts in the GIC distributor. 1979 - Configure all other interrupts as non-secure. 1980 - Enable signaling of secure interrupts in the GIC distributor. 1981 1982- Enable system-level implementation of the generic timer counter through the 1983 memory mapped interface. 1984 1985- Grant access to the system counter timer module 1986 1987- Initialize the power controller device. 1988 1989 In particular, initialise the locks that prevent concurrent accesses to the 1990 power controller device. 1991 1992Function : bl31\_plat\_runtime\_setup() [optional] 1993~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1994 1995:: 1996 1997 Argument : void 1998 Return : void 1999 2000The purpose of this function is allow the platform to perform any BL31 runtime 2001setup just prior to BL31 exit during cold boot. The default weak 2002implementation of this function will invoke ``console_switch_state()`` to switch 2003console output to consoles marked for use in the ``runtime`` state. 2004 2005Function : bl31\_plat\_get\_next\_image\_ep\_info() [mandatory] 2006~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2007 2008:: 2009 2010 Argument : uint32_t 2011 Return : entry_point_info * 2012 2013This function may execute with the MMU and data caches enabled if the platform 2014port does the necessary initializations in ``bl31_plat_arch_setup()``. 2015 2016This function is called by ``bl31_main()`` to retrieve information provided by 2017BL2 for the next image in the security state specified by the argument. BL31 2018uses this information to pass control to that image in the specified security 2019state. This function must return a pointer to the ``entry_point_info`` structure 2020(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2021should return NULL otherwise. 2022 2023Function : bl31_plat_enable_mmu [optional] 2024~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2025 2026:: 2027 2028 Argument : uint32_t 2029 Return : void 2030 2031This function enables the MMU. The boot code calls this function with MMU and 2032caches disabled. This function should program necessary registers to enable 2033translation, and upon return, the MMU on the calling PE must be enabled. 2034 2035The function must honor flags passed in the first argument. These flags are 2036defined by the translation library, and can be found in the file 2037``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2038 2039On DynamIQ systems, this function must not use stack while enabling MMU, which 2040is how the function in xlat table library version 2 is implementated. 2041 2042Function : plat\_get\_syscnt\_freq2() [mandatory] 2043~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2044 2045:: 2046 2047 Argument : void 2048 Return : unsigned int 2049 2050This function is used by the architecture setup code to retrieve the counter 2051frequency for the CPU's generic timer. This value will be programmed into the 2052``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2053of the system counter, which is retrieved from the first entry in the frequency 2054modes table. 2055 2056#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional] 2057~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2058 2059When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2060bytes) aligned to the cache line boundary that should be allocated per-cpu to 2061accommodate all the bakery locks. 2062 2063If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2064calculates the size of the ``bakery_lock`` input section, aligns it to the 2065nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2066and stores the result in a linker symbol. This constant prevents a platform 2067from relying on the linker and provide a more efficient mechanism for 2068accessing per-cpu bakery lock information. 2069 2070If this constant is defined and its value is not equal to the value 2071calculated by the linker then a link time assertion is raised. A compile time 2072assertion is raised if the value of the constant is not aligned to the cache 2073line boundary. 2074 2075SDEI porting requirements 2076~~~~~~~~~~~~~~~~~~~~~~~~~ 2077 2078The SDEI dispatcher requires the platform to provide the following macros 2079and functions, of which some are optional, and some others mandatory. 2080 2081Macros 2082...... 2083 2084Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2085^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2086 2087This macro must be defined to the EL3 exception priority level associated with 2088Normal SDEI events on the platform. This must have a higher value (therefore of 2089lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2090 2091Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2092^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2093 2094This macro must be defined to the EL3 exception priority level associated with 2095Critical SDEI events on the platform. This must have a lower value (therefore of 2096higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2097 2098**Note**: SDEI exception priorities must be the lowest among Secure priorities. 2099Among the SDEI exceptions, Critical SDEI priority must be higher than Normal 2100SDEI priority. 2101 2102Functions 2103......... 2104 2105Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 2106^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2107 2108:: 2109 2110 Argument: uintptr_t 2111 Return: int 2112 2113This function validates the address of client entry points provided for both 2114event registration and *Complete and Resume* SDEI calls. The function takes one 2115argument, which is the address of the handler the SDEI client requested to 2116register. The function must return ``0`` for successful validation, or ``-1`` 2117upon failure. 2118 2119The default implementation always returns ``0``. On Arm platforms, this function 2120is implemented to translate the entry point to physical address, and further to 2121ensure that the address is located in Non-secure DRAM. 2122 2123Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2124^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2125 2126:: 2127 2128 Argument: uint64_t 2129 Argument: unsigned int 2130 Return: void 2131 2132SDEI specification requires that a PE comes out of reset with the events masked. 2133The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 2134the PE. No SDEI events can be dispatched until such time. 2135 2136Should a PE receive an interrupt that was bound to an SDEI event while the 2137events are masked on the PE, the dispatcher implementation invokes the function 2138``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2139interrupt and the interrupt ID are passed as parameters. 2140 2141The default implementation only prints out a warning message. 2142 2143Power State Coordination Interface (in BL31) 2144-------------------------------------------- 2145 2146The TF-A implementation of the PSCI API is based around the concept of a 2147*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2148share some state on which power management operations can be performed as 2149specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2150a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2151*power domains* are arranged in a hierarchical tree structure and each 2152*power domain* can be identified in a system by the cpu index of any CPU that 2153is part of that domain and a *power domain level*. A processing element (for 2154example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2155logical grouping of CPUs that share some state, then level 1 is that group of 2156CPUs (for example, a cluster), and level 2 is a group of clusters (for 2157example, the system). More details on the power domain topology and its 2158organization can be found in `Power Domain Topology Design`_. 2159 2160BL31's platform initialization code exports a pointer to the platform-specific 2161power management operations required for the PSCI implementation to function 2162correctly. This information is populated in the ``plat_psci_ops`` structure. The 2163PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2164power management operations on the power domains. For example, the target 2165CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2166handler (if present) is called for the CPU power domain. 2167 2168The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2169describe composite power states specific to a platform. The PSCI implementation 2170defines a generic representation of the power-state parameter viz which is an 2171array of local power states where each index corresponds to a power domain 2172level. Each entry contains the local power state the power domain at that power 2173level could enter. It depends on the ``validate_power_state()`` handler to 2174convert the power-state parameter (possibly encoding a composite power state) 2175passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2176 2177The following functions form part of platform port of PSCI functionality. 2178 2179Function : plat\_psci\_stat\_accounting\_start() [optional] 2180~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2181 2182:: 2183 2184 Argument : const psci_power_state_t * 2185 Return : void 2186 2187This is an optional hook that platforms can implement for residency statistics 2188accounting before entering a low power state. The ``pwr_domain_state`` field of 2189``state_info`` (first argument) can be inspected if stat accounting is done 2190differently at CPU level versus higher levels. As an example, if the element at 2191index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2192state, special hardware logic may be programmed in order to keep track of the 2193residency statistics. For higher levels (array indices > 0), the residency 2194statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2195default implementation will use PMF to capture timestamps. 2196 2197Function : plat\_psci\_stat\_accounting\_stop() [optional] 2198~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2199 2200:: 2201 2202 Argument : const psci_power_state_t * 2203 Return : void 2204 2205This is an optional hook that platforms can implement for residency statistics 2206accounting after exiting from a low power state. The ``pwr_domain_state`` field 2207of ``state_info`` (first argument) can be inspected if stat accounting is done 2208differently at CPU level versus higher levels. As an example, if the element at 2209index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2210state, special hardware logic may be programmed in order to keep track of the 2211residency statistics. For higher levels (array indices > 0), the residency 2212statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2213default implementation will use PMF to capture timestamps. 2214 2215Function : plat\_psci\_stat\_get\_residency() [optional] 2216~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2217 2218:: 2219 2220 Argument : unsigned int, const psci_power_state_t *, int 2221 Return : u_register_t 2222 2223This is an optional interface that is is invoked after resuming from a low power 2224state and provides the time spent resident in that low power state by the power 2225domain at a particular power domain level. When a CPU wakes up from suspend, 2226all its parent power domain levels are also woken up. The generic PSCI code 2227invokes this function for each parent power domain that is resumed and it 2228identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2229argument) describes the low power state that the power domain has resumed from. 2230The current CPU is the first CPU in the power domain to resume from the low 2231power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2232CPU in the power domain to suspend and may be needed to calculate the residency 2233for that power domain. 2234 2235Function : plat\_get\_target\_pwr\_state() [optional] 2236~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2237 2238:: 2239 2240 Argument : unsigned int, const plat_local_state_t *, unsigned int 2241 Return : plat_local_state_t 2242 2243The PSCI generic code uses this function to let the platform participate in 2244state coordination during a power management operation. The function is passed 2245a pointer to an array of platform specific local power state ``states`` (second 2246argument) which contains the requested power state for each CPU at a particular 2247power domain level ``lvl`` (first argument) within the power domain. The function 2248is expected to traverse this array of upto ``ncpus`` (third argument) and return 2249a coordinated target power state by the comparing all the requested power 2250states. The target power state should not be deeper than any of the requested 2251power states. 2252 2253A weak definition of this API is provided by default wherein it assumes 2254that the platform assigns a local state value in order of increasing depth 2255of the power state i.e. for two power states X & Y, if X < Y 2256then X represents a shallower power state than Y. As a result, the 2257coordinated target local power state for a power domain will be the minimum 2258of the requested local power state values. 2259 2260Function : plat\_get\_power\_domain\_tree\_desc() [mandatory] 2261~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2262 2263:: 2264 2265 Argument : void 2266 Return : const unsigned char * 2267 2268This function returns a pointer to the byte array containing the power domain 2269topology tree description. The format and method to construct this array are 2270described in `Power Domain Topology Design`_. The BL31 PSCI initilization code 2271requires this array to be described by the platform, either statically or 2272dynamically, to initialize the power domain topology tree. In case the array 2273is populated dynamically, then plat\_core\_pos\_by\_mpidr() and 2274plat\_my\_core\_pos() should also be implemented suitably so that the topology 2275tree description matches the CPU indices returned by these APIs. These APIs 2276together form the platform interface for the PSCI topology framework. 2277 2278Function : plat\_setup\_psci\_ops() [mandatory] 2279~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2280 2281:: 2282 2283 Argument : uintptr_t, const plat_psci_ops ** 2284 Return : int 2285 2286This function may execute with the MMU and data caches enabled if the platform 2287port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2288called by the primary CPU. 2289 2290This function is called by PSCI initialization code. Its purpose is to let 2291the platform layer know about the warm boot entrypoint through the 2292``sec_entrypoint`` (first argument) and to export handler routines for 2293platform-specific psci power management actions by populating the passed 2294pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2295 2296A description of each member of this structure is given below. Please refer to 2297the Arm FVP specific implementation of these handlers in 2298`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the 2299platform wants to support, the associated operation or operations in this 2300structure must be provided and implemented (Refer section 4 of 2301`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI 2302function in a platform port, the operation should be removed from this 2303structure instead of providing an empty implementation. 2304 2305plat\_psci\_ops.cpu\_standby() 2306.............................. 2307 2308Perform the platform-specific actions to enter the standby state for a cpu 2309indicated by the passed argument. This provides a fast path for CPU standby 2310wherein overheads of PSCI state management and lock acquistion is avoided. 2311For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2312the suspend state type specified in the ``power-state`` parameter should be 2313STANDBY and the target power domain level specified should be the CPU. The 2314handler should put the CPU into a low power retention state (usually by 2315issuing a wfi instruction) and ensure that it can be woken up from that 2316state by a normal interrupt. The generic code expects the handler to succeed. 2317 2318plat\_psci\_ops.pwr\_domain\_on() 2319................................. 2320 2321Perform the platform specific actions to power on a CPU, specified 2322by the ``MPIDR`` (first argument). The generic code expects the platform to 2323return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure. 2324 2325plat\_psci\_ops.pwr\_domain\_off() 2326.................................. 2327 2328Perform the platform specific actions to prepare to power off the calling CPU 2329and its higher parent power domain levels as indicated by the ``target_state`` 2330(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2331 2332The ``target_state`` encodes the platform coordinated target local power states 2333for the CPU power domain and its parent power domain levels. The handler 2334needs to perform power management operation corresponding to the local state 2335at each power level. 2336 2337For this handler, the local power state for the CPU power domain will be a 2338power down state where as it could be either power down, retention or run state 2339for the higher power domain levels depending on the result of state 2340coordination. The generic code expects the handler to succeed. 2341 2342plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] 2343................................................................. 2344 2345This optional function may be used as a performance optimization to replace 2346or complement pwr_domain_suspend() on some platforms. Its calling semantics 2347are identical to pwr_domain_suspend(), except the PSCI implementation only 2348calls this function when suspending to a power down state, and it guarantees 2349that data caches are enabled. 2350 2351When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2352before calling pwr_domain_suspend(). If the target_state corresponds to a 2353power down state and it is safe to perform some or all of the platform 2354specific actions in that function with data caches enabled, it may be more 2355efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2356= 1, data caches remain enabled throughout, and so there is no advantage to 2357moving platform specific actions to this function. 2358 2359plat\_psci\_ops.pwr\_domain\_suspend() 2360...................................... 2361 2362Perform the platform specific actions to prepare to suspend the calling 2363CPU and its higher parent power domain levels as indicated by the 2364``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2365API implementation. 2366 2367The ``target_state`` has a similar meaning as described in 2368the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2369target local power states for the CPU power domain and its parent 2370power domain levels. The handler needs to perform power management operation 2371corresponding to the local state at each power level. The generic code 2372expects the handler to succeed. 2373 2374The difference between turning a power domain off versus suspending it is that 2375in the former case, the power domain is expected to re-initialize its state 2376when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2377case, the power domain is expected to save enough state so that it can resume 2378execution by restoring this state when its powered on (see 2379``pwr_domain_suspend_finish()``). 2380 2381When suspending a core, the platform can also choose to power off the GICv3 2382Redistributor and ITS through an implementation-defined sequence. To achieve 2383this safely, the ITS context must be saved first. The architectural part is 2384implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2385sequence is implementation defined and it is therefore the responsibility of 2386the platform code to implement the necessary sequence. Then the GIC 2387Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2388Powering off the Redistributor requires the implementation to support it and it 2389is the responsibility of the platform code to execute the right implementation 2390defined sequence. 2391 2392When a system suspend is requested, the platform can also make use of the 2393``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2394it has saved the context of the Redistributors and ITS of all the cores in the 2395system. The context of the Distributor can be large and may require it to be 2396allocated in a special area if it cannot fit in the platform's global static 2397data, for example in DRAM. The Distributor can then be powered down using an 2398implementation-defined sequence. 2399 2400plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi() 2401............................................. 2402 2403This is an optional function and, if implemented, is expected to perform 2404platform specific actions including the ``wfi`` invocation which allows the 2405CPU to powerdown. Since this function is invoked outside the PSCI locks, 2406the actions performed in this hook must be local to the CPU or the platform 2407must ensure that races between multiple CPUs cannot occur. 2408 2409The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2410operation and it encodes the platform coordinated target local power states for 2411the CPU power domain and its parent power domain levels. This function must 2412not return back to the caller. 2413 2414If this function is not implemented by the platform, PSCI generic 2415implementation invokes ``psci_power_down_wfi()`` for power down. 2416 2417plat\_psci\_ops.pwr\_domain\_on\_finish() 2418......................................... 2419 2420This function is called by the PSCI implementation after the calling CPU is 2421powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2422It performs the platform-specific setup required to initialize enough state for 2423this CPU to enter the normal world and also provide secure runtime firmware 2424services. 2425 2426The ``target_state`` (first argument) is the prior state of the power domains 2427immediately before the CPU was turned on. It indicates which power domains 2428above the CPU might require initialization due to having previously been in 2429low power states. The generic code expects the handler to succeed. 2430 2431plat\_psci\_ops.pwr\_domain\_suspend\_finish() 2432.............................................. 2433 2434This function is called by the PSCI implementation after the calling CPU is 2435powered on and released from reset in response to an asynchronous wakeup 2436event, for example a timer interrupt that was programmed by the CPU during the 2437``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2438setup required to restore the saved state for this CPU to resume execution 2439in the normal world and also provide secure runtime firmware services. 2440 2441The ``target_state`` (first argument) has a similar meaning as described in 2442the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2443to succeed. 2444 2445If the Distributor, Redistributors or ITS have been powered off as part of a 2446suspend, their context must be restored in this function in the reverse order 2447to how they were saved during suspend sequence. 2448 2449plat\_psci\_ops.system\_off() 2450............................. 2451 2452This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2453call. It performs the platform-specific system poweroff sequence after 2454notifying the Secure Payload Dispatcher. 2455 2456plat\_psci\_ops.system\_reset() 2457............................... 2458 2459This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2460call. It performs the platform-specific system reset sequence after 2461notifying the Secure Payload Dispatcher. 2462 2463plat\_psci\_ops.validate\_power\_state() 2464........................................ 2465 2466This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2467call to validate the ``power_state`` parameter of the PSCI API and if valid, 2468populate it in ``req_state`` (second argument) array as power domain level 2469specific local states. If the ``power_state`` is invalid, the platform must 2470return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the 2471normal world PSCI client. 2472 2473plat\_psci\_ops.validate\_ns\_entrypoint() 2474.......................................... 2475 2476This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2477``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2478parameter passed by the normal world. If the ``entry_point`` is invalid, 2479the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is 2480propagated back to the normal world PSCI client. 2481 2482plat\_psci\_ops.get\_sys\_suspend\_power\_state() 2483................................................. 2484 2485This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2486call to get the ``req_state`` parameter from platform which encodes the power 2487domain level specific local states to suspend to system affinity level. The 2488``req_state`` will be utilized to do the PSCI state coordination and 2489``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2490enter system suspend. 2491 2492plat\_psci\_ops.get\_pwr\_lvl\_state\_idx() 2493........................................... 2494 2495This is an optional function and, if implemented, is invoked by the PSCI 2496implementation to convert the ``local_state`` (first argument) at a specified 2497``pwr_lvl`` (second argument) to an index between 0 and 2498``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2499supports more than two local power states at each power domain level, that is 2500``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2501local power states. 2502 2503plat\_psci\_ops.translate\_power\_state\_by\_mpidr() 2504.................................................... 2505 2506This is an optional function and, if implemented, verifies the ``power_state`` 2507(second argument) parameter of the PSCI API corresponding to a target power 2508domain. The target power domain is identified by using both ``MPIDR`` (first 2509argument) and the power domain level encoded in ``power_state``. The power domain 2510level specific local states are to be extracted from ``power_state`` and be 2511populated in the ``output_state`` (third argument) array. The functionality 2512is similar to the ``validate_power_state`` function described above and is 2513envisaged to be used in case the validity of ``power_state`` depend on the 2514targeted power domain. If the ``power_state`` is invalid for the targeted power 2515domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this 2516function is not implemented, then the generic implementation relies on 2517``validate_power_state`` function to translate the ``power_state``. 2518 2519This function can also be used in case the platform wants to support local 2520power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY 2521APIs as described in Section 5.18 of `PSCI`_. 2522 2523plat\_psci\_ops.get\_node\_hw\_state() 2524...................................... 2525 2526This is an optional function. If implemented this function is intended to return 2527the power state of a node (identified by the first parameter, the ``MPIDR``) in 2528the power domain topology (identified by the second parameter, ``power_level``), 2529as retrieved from a power controller or equivalent component on the platform. 2530Upon successful completion, the implementation must map and return the final 2531status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2532must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2533appropriate. 2534 2535Implementations are not expected to handle ``power_levels`` greater than 2536``PLAT_MAX_PWR_LVL``. 2537 2538plat\_psci\_ops.system\_reset2() 2539................................ 2540 2541This is an optional function. If implemented this function is 2542called during the ``SYSTEM_RESET2`` call to perform a reset 2543based on the first parameter ``reset_type`` as specified in 2544`PSCI`_. The parameter ``cookie`` can be used to pass additional 2545reset information. If the ``reset_type`` is not supported, the 2546function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2547resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2548and vendor reset can return other PSCI error codes as defined 2549in `PSCI`_. On success this function will not return. 2550 2551plat\_psci\_ops.write\_mem\_protect() 2552.................................... 2553 2554This is an optional function. If implemented it enables or disables the 2555``MEM_PROTECT`` functionality based on the value of ``val``. 2556A non-zero value enables ``MEM_PROTECT`` and a value of zero 2557disables it. Upon encountering failures it must return a negative value 2558and on success it must return 0. 2559 2560plat\_psci\_ops.read\_mem\_protect() 2561..................................... 2562 2563This is an optional function. If implemented it returns the current 2564state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2565failures it must return a negative value and on success it must 2566return 0. 2567 2568plat\_psci\_ops.mem\_protect\_chk() 2569................................... 2570 2571This is an optional function. If implemented it checks if a memory 2572region defined by a base address ``base`` and with a size of ``length`` 2573bytes is protected by ``MEM_PROTECT``. If the region is protected 2574then it must return 0, otherwise it must return a negative number. 2575 2576Interrupt Management framework (in BL31) 2577---------------------------------------- 2578 2579BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2580generated in either security state and targeted to EL1 or EL2 in the non-secure 2581state or EL3/S-EL1 in the secure state. The design of this framework is 2582described in the `IMF Design Guide`_ 2583 2584A platform should export the following APIs to support the IMF. The following 2585text briefly describes each api and its implementation in Arm standard 2586platforms. The API implementation depends upon the type of interrupt controller 2587present in the platform. Arm standard platform layer supports both 2588`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2589and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2590FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2591``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in 2592`User Guide`_ for more details). 2593 2594See also: `Interrupt Controller Abstraction APIs`__. 2595 2596.. __: platform-interrupt-controller-API.rst 2597 2598Function : plat\_interrupt\_type\_to\_line() [mandatory] 2599~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2600 2601:: 2602 2603 Argument : uint32_t, uint32_t 2604 Return : uint32_t 2605 2606The Arm processor signals an interrupt exception either through the IRQ or FIQ 2607interrupt line. The specific line that is signaled depends on how the interrupt 2608controller (IC) reports different interrupt types from an execution context in 2609either security state. The IMF uses this API to determine which interrupt line 2610the platform IC uses to signal each type of interrupt supported by the framework 2611from a given security state. This API must be invoked at EL3. 2612 2613The first parameter will be one of the ``INTR_TYPE_*`` values (see 2614`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2615security state of the originating execution context. The return result is the 2616bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2617FIQ=2. 2618 2619In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2620configured as FIQs and Non-secure interrupts as IRQs from either security 2621state. 2622 2623In the case of Arm standard platforms using GICv3, the interrupt line to be 2624configured depends on the security state of the execution context when the 2625interrupt is signalled and are as follows: 2626 2627- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2628 NS-EL0/1/2 context. 2629- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2630 in the NS-EL0/1/2 context. 2631- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2632 context. 2633 2634Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory] 2635~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2636 2637:: 2638 2639 Argument : void 2640 Return : uint32_t 2641 2642This API returns the type of the highest priority pending interrupt at the 2643platform IC. The IMF uses the interrupt type to retrieve the corresponding 2644handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2645pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2646``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2647 2648In the case of Arm standard platforms using GICv2, the *Highest Priority 2649Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2650the pending interrupt. The type of interrupt depends upon the id value as 2651follows. 2652 2653#. id < 1022 is reported as a S-EL1 interrupt 2654#. id = 1022 is reported as a Non-secure interrupt. 2655#. id = 1023 is reported as an invalid interrupt type. 2656 2657In the case of Arm standard platforms using GICv3, the system register 2658``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2659is read to determine the id of the pending interrupt. The type of interrupt 2660depends upon the id value as follows. 2661 2662#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2663#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2664#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2665#. All other interrupt id's are reported as EL3 interrupt. 2666 2667Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory] 2668~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2669 2670:: 2671 2672 Argument : void 2673 Return : uint32_t 2674 2675This API returns the id of the highest priority pending interrupt at the 2676platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2677pending. 2678 2679In the case of Arm standard platforms using GICv2, the *Highest Priority 2680Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2681pending interrupt. The id that is returned by API depends upon the value of 2682the id read from the interrupt controller as follows. 2683 2684#. id < 1022. id is returned as is. 2685#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2686 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2687 This id is returned by the API. 2688#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2689 2690In the case of Arm standard platforms using GICv3, if the API is invoked from 2691EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2692group 0 Register*, is read to determine the id of the pending interrupt. The id 2693that is returned by API depends upon the value of the id read from the 2694interrupt controller as follows. 2695 2696#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2697#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2698 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2699 Register* is read to determine the id of the group 1 interrupt. This id 2700 is returned by the API as long as it is a valid interrupt id 2701#. If the id is any of the special interrupt identifiers, 2702 ``INTR_ID_UNAVAILABLE`` is returned. 2703 2704When the API invoked from S-EL1 for GICv3 systems, the id read from system 2705register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2706Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else 2707``INTR_ID_UNAVAILABLE`` is returned. 2708 2709Function : plat\_ic\_acknowledge\_interrupt() [mandatory] 2710~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2711 2712:: 2713 2714 Argument : void 2715 Return : uint32_t 2716 2717This API is used by the CPU to indicate to the platform IC that processing of 2718the highest pending interrupt has begun. It should return the raw, unmodified 2719value obtained from the interrupt controller when acknowledging an interrupt. 2720The actual interrupt number shall be extracted from this raw value using the API 2721`plat_ic_get_interrupt_id()`__. 2722 2723.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2724 2725This function in Arm standard platforms using GICv2, reads the *Interrupt 2726Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2727priority pending interrupt from pending to active in the interrupt controller. 2728It returns the value read from the ``GICC_IAR``, unmodified. 2729 2730In the case of Arm standard platforms using GICv3, if the API is invoked 2731from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2732Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2733reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2734group 1*. The read changes the state of the highest pending interrupt from 2735pending to active in the interrupt controller. The value read is returned 2736unmodified. 2737 2738The TSP uses this API to start processing of the secure physical timer 2739interrupt. 2740 2741Function : plat\_ic\_end\_of\_interrupt() [mandatory] 2742~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2743 2744:: 2745 2746 Argument : uint32_t 2747 Return : void 2748 2749This API is used by the CPU to indicate to the platform IC that processing of 2750the interrupt corresponding to the id (passed as the parameter) has 2751finished. The id should be the same as the id returned by the 2752``plat_ic_acknowledge_interrupt()`` API. 2753 2754Arm standard platforms write the id to the *End of Interrupt Register* 2755(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2756system register in case of GICv3 depending on where the API is invoked from, 2757EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2758controller. 2759 2760The TSP uses this API to finish processing of the secure physical timer 2761interrupt. 2762 2763Function : plat\_ic\_get\_interrupt\_type() [mandatory] 2764~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2765 2766:: 2767 2768 Argument : uint32_t 2769 Return : uint32_t 2770 2771This API returns the type of the interrupt id passed as the parameter. 2772``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2773interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2774returned depending upon how the interrupt has been configured by the platform 2775IC. This API must be invoked at EL3. 2776 2777Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2778and Non-secure interrupts as Group1 interrupts. It reads the group value 2779corresponding to the interrupt id from the relevant *Interrupt Group Register* 2780(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2781 2782In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2783Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2784(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2785as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2786 2787Crash Reporting mechanism (in BL31) 2788----------------------------------- 2789 2790NOTE: This section assumes that your platform is enabling the MULTI_CONSOLE_API 2791flag in its platform.mk. Not using this flag is deprecated for new platforms. 2792 2793BL31 implements a crash reporting mechanism which prints the various registers 2794of the CPU to enable quick crash analysis and debugging. By default, the 2795definitions in ``plat/common/aarch64/platform\_helpers.S`` will cause the crash 2796output to be routed over the normal console infrastructure and get printed on 2797consoles configured to output in crash state. ``console_set_scope()`` can be 2798used to control whether a console is used for crash output. 2799 2800In some cases (such as debugging very early crashes that happen before the 2801normal boot console can be set up), platforms may want to control crash output 2802more explicitly. For these, the following functions can be overridden by 2803platform code. They are executed outside of a C environment and without a stack. 2804 2805Function : plat\_crash\_console\_init 2806~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2807 2808:: 2809 2810 Argument : void 2811 Return : int 2812 2813This API is used by the crash reporting mechanism to initialize the crash 2814console. It must only use the general purpose registers x0 through x7 to do the 2815initialization and returns 1 on success. 2816 2817If you are trying to debug crashes before the console driver would normally get 2818registered, you can use this to register a driver from assembly with hardcoded 2819parameters. For example, you could register the 16550 driver like this: 2820 2821:: 2822 2823 .section .data.crash_console /* Reserve space for console structure */ 2824 crash_console: 2825 .zero 6 * 8 /* console_16550_t has 6 8-byte words */ 2826 func plat_crash_console_init 2827 ldr x0, =YOUR_16550_BASE_ADDR 2828 ldr x1, =YOUR_16550_SRCCLK_IN_HZ 2829 ldr x2, =YOUR_16550_TARGET_BAUD_RATE 2830 adrp x3, crash_console 2831 add x3, x3, :lo12:crash_console 2832 b console_16550_register /* tail call, returns 1 on success */ 2833 endfunc plat_crash_console_init 2834 2835If you're trying to debug crashes in BL1, you can call the console_xxx_core_init 2836function exported by some console drivers from here. 2837 2838Function : plat\_crash\_console\_putc 2839~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2840 2841:: 2842 2843 Argument : int 2844 Return : int 2845 2846This API is used by the crash reporting mechanism to print a character on the 2847designated crash console. It must only use general purpose registers x1 and 2848x2 to do its work. The parameter and the return value are in general purpose 2849register x0. 2850 2851If you have registered a normal console driver in ``plat_crash_console_init``, 2852you can keep the default implementation here (which calls ``console_putc()``). 2853 2854If you're trying to debug crashes in BL1, you can call the console_xxx_core_putc 2855function exported by some console drivers from here. 2856 2857Function : plat\_crash\_console\_flush 2858~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2859 2860:: 2861 2862 Argument : void 2863 Return : int 2864 2865This API is used by the crash reporting mechanism to force write of all buffered 2866data on the designated crash console. It should only use general purpose 2867registers x0 through x5 to do its work. The return value is 0 on successful 2868completion; otherwise the return value is -1. 2869 2870If you have registered a normal console driver in ``plat_crash_console_init``, 2871you can keep the default implementation here (which calls ``console_flush()``). 2872 2873If you're trying to debug crashes in BL1, you can call the console_xx_core_flush 2874function exported by some console drivers from here. 2875 2876Extternal Abort handling and RAS Support 2877---------------------------------------- 2878 2879Function : plat_ea_handler 2880~~~~~~~~~~~~~~~~~~~~~~~~~~ 2881 2882:: 2883 2884 Argument : int 2885 Argument : uint64_t 2886 Argument : void * 2887 Argument : void * 2888 Argument : uint64_t 2889 Return : void 2890 2891This function is invoked by the RAS framework for the platform to handle an 2892External Abort received at EL3. The intention of the function is to attempt to 2893resolve the cause of External Abort and return; if that's not possible, to 2894initiate orderly shutdown of the system. 2895 2896The first parameter (``int ea_reason``) indicates the reason for External Abort. 2897Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 2898 2899The second parameter (``uint64_t syndrome``) is the respective syndrome 2900presented to EL3 after having received the External Abort. Depending on the 2901nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 2902can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 2903 2904The third parameter (``void *cookie``) is unused for now. The fourth parameter 2905(``void *handle``) is a pointer to the preempted context. The fifth parameter 2906(``uint64_t flags``) indicates the preempted security state. These parameters 2907are received from the top-level exception handler. 2908 2909If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this 2910function iterates through RAS handlers registered by the platform. If any of the 2911RAS handlers resolve the External Abort, no further action is taken. 2912 2913If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers 2914could resolve the External Abort, the default implementation prints an error 2915message, and panics. 2916 2917Function : plat_handle_uncontainable_ea 2918~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2919 2920:: 2921 2922 Argument : int 2923 Argument : uint64_t 2924 Return : void 2925 2926This function is invoked by the RAS framework when an External Abort of 2927Uncontainable type is received at EL3. Due to the critical nature of 2928Uncontainable errors, the intention of this function is to initiate orderly 2929shutdown of the system, and is not expected to return. 2930 2931This function must be implemented in assembly. 2932 2933The first and second parameters are the same as that of ``plat_ea_handler``. 2934 2935The default implementation of this function calls 2936``report_unhandled_exception``. 2937 2938Function : plat_handle_double_fault 2939~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2940 2941:: 2942 2943 Argument : int 2944 Argument : uint64_t 2945 Return : void 2946 2947This function is invoked by the RAS framework when another External Abort is 2948received at EL3 while one is already being handled. I.e., a call to 2949``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 2950this function is to initiate orderly shutdown of the system, and is not expected 2951recover or return. 2952 2953This function must be implemented in assembly. 2954 2955The first and second parameters are the same as that of ``plat_ea_handler``. 2956 2957The default implementation of this function calls 2958``report_unhandled_exception``. 2959 2960Function : plat_handle_el3_ea 2961~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2962 2963:: 2964 2965 Return : void 2966 2967This function is invoked when an External Abort is received while executing in 2968EL3. Due to its critical nature, the intention of this function is to initiate 2969orderly shutdown of the system, and is not expected recover or return. 2970 2971This function must be implemented in assembly. 2972 2973The default implementation of this function calls 2974``report_unhandled_exception``. 2975 2976Build flags 2977----------- 2978 2979- **ENABLE\_PLAT\_COMPAT** 2980 All the platforms ports conforming to this API specification should define 2981 the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should 2982 be disabled. For more details on compatibility layer, refer 2983 `Migration Guide`_. 2984 2985There are some build flags which can be defined by the platform to control 2986inclusion or exclusion of certain BL stages from the FIP image. These flags 2987need to be defined in the platform makefile which will get included by the 2988build system. 2989 2990- **NEED\_BL33** 2991 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2992 build option should be supplied as a build option. The platform has the 2993 option of excluding the BL33 image in the ``fip`` image by defining this flag 2994 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2995 are used, this flag will be set to ``no`` automatically. 2996 2997C Library 2998--------- 2999 3000To avoid subtle toolchain behavioral dependencies, the header files provided 3001by the compiler are not used. The software is built with the ``-nostdinc`` flag 3002to ensure no headers are included from the toolchain inadvertently. Instead the 3003required headers are included in the TF-A source tree. The library only 3004contains those C library definitions required by the local implementation. If 3005more functionality is required, the needed library functions will need to be 3006added to the local implementation. 3007 3008Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3009been written specifically for TF-A. Fome implementation files have been obtained 3010from `FreeBSD`_, others have been written specifically for TF-A as well. The 3011files can be found in ``include/lib/libc`` and ``lib/libc``. 3012 3013SCC can be found in `http://www.simple-cc.org/`_. A copy of the `FreeBSD`_ 3014sources can be obtained from `http://github.com/freebsd/freebsd`_. 3015 3016Storage abstraction layer 3017------------------------- 3018 3019In order to improve platform independence and portability an storage abstraction 3020layer is used to load data from non-volatile platform storage. 3021 3022Each platform should register devices and their drivers via the Storage layer. 3023These drivers then need to be initialized by bootloader phases as 3024required in their respective ``blx_platform_setup()`` functions. Currently 3025storage access is only required by BL1 and BL2 phases. The ``load_image()`` 3026function uses the storage layer to access non-volatile platform storage. 3027 3028It is mandatory to implement at least one storage driver. For the Arm 3029development platforms the Firmware Image Package (FIP) driver is provided as 3030the default means to load data from storage (see the "Firmware Image Package" 3031section in the `User Guide`_). The storage layer is described in the header file 3032``include/drivers/io/io_storage.h``. The implementation of the common library 3033is in ``drivers/io/io_storage.c`` and the driver files are located in 3034``drivers/io/``. 3035 3036Each IO driver must provide ``io_dev_*`` structures, as described in 3037``drivers/io/io_driver.h``. These are returned via a mandatory registration 3038function that is called on platform initialization. The semi-hosting driver 3039implementation in ``io_semihosting.c`` can be used as an example. 3040 3041The Storage layer provides mechanisms to initialize storage devices before 3042IO operations are called. The basic operations supported by the layer 3043include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3044Drivers do not have to implement all operations, but each platform must 3045provide at least one driver for a device capable of supporting generic 3046operations such as loading a bootloader image. 3047 3048The current implementation only allows for known images to be loaded by the 3049firmware. These images are specified by using their identifiers, as defined in 3050[include/plat/common/platform\_def.h] (or a separate header file included from 3051there). The platform layer (``plat_get_image_source()``) then returns a reference 3052to a device and a driver-specific ``spec`` which will be understood by the driver 3053to allow access to the image data. 3054 3055The layer is designed in such a way that is it possible to chain drivers with 3056other drivers. For example, file-system drivers may be implemented on top of 3057physical block devices, both represented by IO devices with corresponding 3058drivers. In such a case, the file-system "binding" with the block device may 3059be deferred until the file-system device is initialised. 3060 3061The abstraction currently depends on structures being statically allocated 3062by the drivers and callers, as the system does not yet provide a means of 3063dynamically allocating memory. This may also have the affect of limiting the 3064amount of open resources per driver. 3065 3066-------------- 3067 3068*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.* 3069 3070.. _Migration Guide: platform-migration-guide.rst 3071.. _include/plat/common/platform.h: ../include/plat/common/platform.h 3072.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D 3073.. _User Guide: user-guide.rst 3074.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h 3075.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h 3076.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S 3077.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S 3078.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 3079.. _Power Domain Topology Design: psci-pd-tree.rst 3080.. _include/common/bl\_common.h: ../include/common/bl_common.h 3081.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 3082.. _Firmware Design: firmware-design.rst 3083.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 3084.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c 3085.. _IMF Design Guide: interrupt-framework-design.rst 3086.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 3087.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 3088.. _FreeBSD: http://www.freebsd.org 3089.. _SCC: http://www.simple-cc.org/ 3090