1Porting Guide 2============= 3 4Introduction 5------------ 6 7Porting Trusted Firmware-A (TF-A) to a new platform involves making some 8mandatory and optional modifications for both the cold and warm boot paths. 9Modifications consist of: 10 11- Implementing a platform-specific function or variable, 12- Setting up the execution context in a certain way, or 13- Defining certain constants (for example #defines). 14 15The platform-specific functions and variables are declared in 16``include/plat/common/platform.h``. The firmware provides a default 17implementation of variables and functions to fulfill the optional requirements 18in order to ease the porting effort. Each platform port can use them as is or 19provide their own implementation if the default implementation is inadequate. 20 21 .. note:: 22 23 TF-A historically provided default implementations of platform interfaces 24 as *weak* functions. This practice is now discouraged and new platform 25 interfaces as they get introduced in the code base should be *strongly* 26 defined. We intend to convert existing weak functions over time. Until 27 then, you will find references to *weak* functions in this document. 28 29Please review the :ref:`Threat Model` documents as part of the porting 30effort. Some platform interfaces play a key role in mitigating against some of 31the threats. Failing to fulfill these expectations could undermine the security 32guarantees offered by TF-A. These platform responsibilities are highlighted in 33the threat assessment section, under the "`Mitigations implemented?`" box for 34each threat. 35 36Some modifications are common to all Boot Loader (BL) stages. Section 2 37discusses these in detail. The subsequent sections discuss the remaining 38modifications for each BL stage in detail. 39 40Please refer to the :ref:`Platform Ports Policy` for the policy regarding 41compatibility and deprecation of these porting interfaces. 42 43Only Arm development platforms (such as FVP and Juno) may use the 44functions/definitions in ``include/plat/arm/common/`` and the corresponding 45source files in ``plat/arm/common/``. This is done so that there are no 46dependencies between platforms maintained by different people/companies. If you 47want to use any of the functionality present in ``plat/arm`` files, please 48propose a patch that moves the code to ``plat/common`` so that it can be 49discussed. 50 51Common modifications 52-------------------- 53 54This section covers the modifications that should be made by the platform for 55each BL stage to correctly port the firmware stack. They are categorized as 56either mandatory or optional. 57 58Common mandatory modifications 59------------------------------ 60 61A platform port must enable the Memory Management Unit (MMU) as well as the 62instruction and data caches for each BL stage. Setting up the translation 63tables is the responsibility of the platform port because memory maps differ 64across platforms. A memory translation library (see ``lib/xlat_tables_v2/``) is 65provided to help in this setup. 66 67Note that although this library supports non-identity mappings, this is intended 68only for re-mapping peripheral physical addresses and allows platforms with high 69I/O addresses to reduce their virtual address space. All other addresses 70corresponding to code and data must currently use an identity mapping. 71 72Also, the only translation granule size supported in TF-A is 4KB, as various 73parts of the code assume that is the case. It is not possible to switch to 7416 KB or 64 KB granule sizes at the moment. 75 76In Arm standard platforms, each BL stage configures the MMU in the 77platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 78an identity mapping for all addresses. 79 80If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 81block of identity mapped secure memory with Device-nGnRE attributes aligned to 82page boundary (4K) for each BL stage. All sections which allocate coherent 83memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a 84section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its 85possible for the firmware to place variables in it using the following C code 86directive: 87 88:: 89 90 __section(".bakery_lock") 91 92Or alternatively the following assembler code directive: 93 94:: 95 96 .section .bakery_lock 97 98The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are 99used to allocate any data structures that are accessed both when a CPU is 100executing with its MMU and caches enabled, and when it's running with its MMU 101and caches disabled. Examples are given below. 102 103The following variables, functions and constants must be defined by the platform 104for the firmware to work correctly. 105 106.. _platform_def_mandatory: 107 108File : platform_def.h [mandatory] 109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 110 111Each platform must ensure that a header file of this name is in the system 112include path with the following constants defined. This will require updating 113the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 114 115Platform ports may optionally use the file ``include/plat/common/common_def.h``, 116which provides typical values for some of the constants below. These values are 117likely to be suitable for all platform ports. 118 119- **#define : PLATFORM_LINKER_FORMAT** 120 121 Defines the linker format used by the platform, for example 122 ``elf64-littleaarch64``. 123 124- **#define : PLATFORM_LINKER_ARCH** 125 126 Defines the processor architecture for the linker by the platform, for 127 example ``aarch64``. 128 129- **#define : PLATFORM_STACK_SIZE** 130 131 Defines the normal stack memory available to each CPU. This constant is used 132 by ``plat/common/aarch64/platform_mp_stack.S`` and 133 ``plat/common/aarch64/platform_up_stack.S``. 134 135- **#define : CACHE_WRITEBACK_GRANULE** 136 137 Defines the size in bytes of the largest cache line across all the cache 138 levels in the platform. 139 140- **#define : FIRMWARE_WELCOME_STR** 141 142 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 143 function. 144 145- **#define : PLATFORM_CORE_COUNT** 146 147 Defines the total number of CPUs implemented by the platform across all 148 clusters in the system. 149 150- **#define : PLAT_NUM_PWR_DOMAINS** 151 152 Defines the total number of nodes in the power domain topology 153 tree at all the power domain levels used by the platform. 154 This macro is used by the PSCI implementation to allocate 155 data structures to represent power domain topology. 156 157- **#define : PLAT_MAX_PWR_LVL** 158 159 Defines the maximum power domain level that the power management operations 160 should apply to. More often, but not always, the power domain level 161 corresponds to affinity level. This macro allows the PSCI implementation 162 to know the highest power domain level that it should consider for power 163 management operations in the system that the platform implements. For 164 example, the Base AEM FVP implements two clusters with a configurable 165 number of CPUs and it reports the maximum power domain level as 1. 166 167- **#define : PLAT_MAX_OFF_STATE** 168 169 Defines the local power state corresponding to the deepest power down 170 possible at every power domain level in the platform. The local power 171 states for each level may be sparsely allocated between 0 and this value 172 with 0 being reserved for the RUN state. The PSCI implementation uses this 173 value to initialize the local power states of the power domain nodes and 174 to specify the requested power state for a PSCI_CPU_OFF call. 175 176- **#define : PLAT_MAX_RET_STATE** 177 178 Defines the local power state corresponding to the deepest retention state 179 possible at every power domain level in the platform. This macro should be 180 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 181 PSCI implementation to distinguish between retention and power down local 182 power states within PSCI_CPU_SUSPEND call. 183 184- **#define : PLAT_MAX_PWR_LVL_STATES** 185 186 Defines the maximum number of local power states per power domain level 187 that the platform supports. The default value of this macro is 2 since 188 most platforms just support a maximum of two local power states at each 189 power domain level (power-down and retention). If the platform needs to 190 account for more local power states, then it must redefine this macro. 191 192 Currently, this macro is used by the Generic PSCI implementation to size 193 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 194 195- **#define : BL1_RO_BASE** 196 197 Defines the base address in secure ROM where BL1 originally lives. Must be 198 aligned on a page-size boundary. 199 200- **#define : BL1_RO_LIMIT** 201 202 Defines the maximum address in secure ROM that BL1's actual content (i.e. 203 excluding any data section allocated at runtime) can occupy. 204 205- **#define : BL1_RW_BASE** 206 207 Defines the base address in secure RAM where BL1's read-write data will live 208 at runtime. Must be aligned on a page-size boundary. 209 210- **#define : BL1_RW_LIMIT** 211 212 Defines the maximum address in secure RAM that BL1's read-write data can 213 occupy at runtime. 214 215- **#define : BL2_BASE** 216 217 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 218 Must be aligned on a page-size boundary. This constant is not applicable 219 when BL2_IN_XIP_MEM is set to '1'. 220 221- **#define : BL2_LIMIT** 222 223 Defines the maximum address in secure RAM that the BL2 image can occupy. 224 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2_RO_BASE** 227 228 Defines the base address in secure XIP memory where BL2 RO section originally 229 lives. Must be aligned on a page-size boundary. This constant is only needed 230 when BL2_IN_XIP_MEM is set to '1'. 231 232- **#define : BL2_RO_LIMIT** 233 234 Defines the maximum address in secure XIP memory that BL2's actual content 235 (i.e. excluding any data section allocated at runtime) can occupy. This 236 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 237 238- **#define : BL2_RW_BASE** 239 240 Defines the base address in secure RAM where BL2's read-write data will live 241 at runtime. Must be aligned on a page-size boundary. This constant is only 242 needed when BL2_IN_XIP_MEM is set to '1'. 243 244- **#define : BL2_RW_LIMIT** 245 246 Defines the maximum address in secure RAM that BL2's read-write data can 247 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 248 to '1'. 249 250- **#define : BL31_BASE** 251 252 Defines the base address in secure RAM where BL2 loads the BL31 binary 253 image. Must be aligned on a page-size boundary. 254 255- **#define : BL31_LIMIT** 256 257 Defines the maximum address in secure RAM that the BL31 image can occupy. 258 259- **#define : PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE** 260 261 Defines the maximum message size between AP and RSE. Need to define if 262 platform supports RSE. 263 264For every image, the platform must define individual identifiers that will be 265used by BL1 or BL2 to load the corresponding image into memory from non-volatile 266storage. For the sake of performance, integer numbers will be used as 267identifiers. The platform will use those identifiers to return the relevant 268information about the image to be loaded (file handler, load address, 269authentication information, etc.). The following image identifiers are 270mandatory: 271 272- **#define : BL2_IMAGE_ID** 273 274 BL2 image identifier, used by BL1 to load BL2. 275 276- **#define : BL31_IMAGE_ID** 277 278 BL31 image identifier, used by BL2 to load BL31. 279 280- **#define : BL33_IMAGE_ID** 281 282 BL33 image identifier, used by BL2 to load BL33. 283 284If Trusted Board Boot is enabled, the following certificate identifiers must 285also be defined: 286 287- **#define : TRUSTED_BOOT_FW_CERT_ID** 288 289 BL2 content certificate identifier, used by BL1 to load the BL2 content 290 certificate. 291 292- **#define : TRUSTED_KEY_CERT_ID** 293 294 Trusted key certificate identifier, used by BL2 to load the trusted key 295 certificate. 296 297- **#define : SOC_FW_KEY_CERT_ID** 298 299 BL31 key certificate identifier, used by BL2 to load the BL31 key 300 certificate. 301 302- **#define : SOC_FW_CONTENT_CERT_ID** 303 304 BL31 content certificate identifier, used by BL2 to load the BL31 content 305 certificate. 306 307- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 308 309 BL33 key certificate identifier, used by BL2 to load the BL33 key 310 certificate. 311 312- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 313 314 BL33 content certificate identifier, used by BL2 to load the BL33 content 315 certificate. 316 317- **#define : FWU_CERT_ID** 318 319 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 320 FWU content certificate. 321 322If the AP Firmware Updater Configuration image, BL2U is used, the following 323must also be defined: 324 325- **#define : BL2U_BASE** 326 327 Defines the base address in secure memory where BL1 copies the BL2U binary 328 image. Must be aligned on a page-size boundary. 329 330- **#define : BL2U_LIMIT** 331 332 Defines the maximum address in secure memory that the BL2U image can occupy. 333 334- **#define : BL2U_IMAGE_ID** 335 336 BL2U image identifier, used by BL1 to fetch an image descriptor 337 corresponding to BL2U. 338 339If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 340must also be defined: 341 342- **#define : SCP_BL2U_IMAGE_ID** 343 344 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 345 corresponding to SCP_BL2U. 346 347 .. note:: 348 TF-A does not provide source code for this image. 349 350If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 351also be defined: 352 353- **#define : NS_BL1U_BASE** 354 355 Defines the base address in non-secure ROM where NS_BL1U executes. 356 Must be aligned on a page-size boundary. 357 358 .. note:: 359 TF-A does not provide source code for this image. 360 361- **#define : NS_BL1U_IMAGE_ID** 362 363 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 364 corresponding to NS_BL1U. 365 366If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 367be defined: 368 369- **#define : NS_BL2U_BASE** 370 371 Defines the base address in non-secure memory where NS_BL2U executes. 372 Must be aligned on a page-size boundary. 373 374 .. note:: 375 TF-A does not provide source code for this image. 376 377- **#define : NS_BL2U_IMAGE_ID** 378 379 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 380 corresponding to NS_BL2U. 381 382For the the Firmware update capability of TRUSTED BOARD BOOT, the following 383macros may also be defined: 384 385- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 386 387 Total number of images that can be loaded simultaneously. If the platform 388 doesn't specify any value, it defaults to 10. 389 390If a SCP_BL2 image is supported by the platform, the following constants must 391also be defined: 392 393- **#define : SCP_BL2_IMAGE_ID** 394 395 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 396 from platform storage before being transferred to the SCP. 397 398- **#define : SCP_FW_KEY_CERT_ID** 399 400 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 401 certificate (mandatory when Trusted Board Boot is enabled). 402 403- **#define : SCP_FW_CONTENT_CERT_ID** 404 405 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 406 content certificate (mandatory when Trusted Board Boot is enabled). 407 408If a BL32 image is supported by the platform, the following constants must 409also be defined: 410 411- **#define : BL32_IMAGE_ID** 412 413 BL32 image identifier, used by BL2 to load BL32. 414 415- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 416 417 BL32 key certificate identifier, used by BL2 to load the BL32 key 418 certificate (mandatory when Trusted Board Boot is enabled). 419 420- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 421 422 BL32 content certificate identifier, used by BL2 to load the BL32 content 423 certificate (mandatory when Trusted Board Boot is enabled). 424 425- **#define : BL32_BASE** 426 427 Defines the base address in secure memory where BL2 loads the BL32 binary 428 image. Must be aligned on a page-size boundary. 429 430- **#define : BL32_LIMIT** 431 432 Defines the maximum address that the BL32 image can occupy. 433 434If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 435platform, the following constants must also be defined: 436 437- **#define : TSP_SEC_MEM_BASE** 438 439 Defines the base address of the secure memory used by the TSP image on the 440 platform. This must be at the same address or below ``BL32_BASE``. 441 442- **#define : TSP_SEC_MEM_SIZE** 443 444 Defines the size of the secure memory used by the BL32 image on the 445 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 446 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 447 and ``BL32_LIMIT``. 448 449- **#define : TSP_IRQ_SEC_PHY_TIMER** 450 451 Defines the ID of the secure physical generic timer interrupt used by the 452 TSP's interrupt handling code. 453 454If the platform port uses the translation table library code, the following 455constants must also be defined: 456 457- **#define : PLAT_XLAT_TABLES_DYNAMIC** 458 459 Optional flag that can be set per-image to enable the dynamic allocation of 460 regions even when the MMU is enabled. If not defined, only static 461 functionality will be available, if defined and set to 1 it will also 462 include the dynamic functionality. 463 464- **#define : MAX_XLAT_TABLES** 465 466 Defines the maximum number of translation tables that are allocated by the 467 translation table library code. To minimize the amount of runtime memory 468 used, choose the smallest value needed to map the required virtual addresses 469 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 470 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 471 as well. 472 473- **#define : MAX_MMAP_REGIONS** 474 475 Defines the maximum number of regions that are allocated by the translation 476 table library code. A region consists of physical base address, virtual base 477 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 478 defined in the ``mmap_region_t`` structure. The platform defines the regions 479 that should be mapped. Then, the translation table library will create the 480 corresponding tables and descriptors at runtime. To minimize the amount of 481 runtime memory used, choose the smallest value needed to register the 482 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 483 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 484 the dynamic regions as well. 485 486- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 487 488 Defines the total size of the virtual address space in bytes. For example, 489 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 490 491- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 492 493 Defines the total size of the physical address space in bytes. For example, 494 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 495 496If the platform port uses the IO storage framework, the following constants 497must also be defined: 498 499- **#define : MAX_IO_DEVICES** 500 501 Defines the maximum number of registered IO devices. Attempting to register 502 more devices than this value using ``io_register_device()`` will fail with 503 -ENOMEM. 504 505- **#define : MAX_IO_HANDLES** 506 507 Defines the maximum number of open IO handles. Attempting to open more IO 508 entities than this value using ``io_open()`` will fail with -ENOMEM. 509 510- **#define : MAX_IO_BLOCK_DEVICES** 511 512 Defines the maximum number of registered IO block devices. Attempting to 513 register more devices this value using ``io_dev_open()`` will fail 514 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 515 With this macro, multiple block devices could be supported at the same 516 time. 517 518If the platform needs to allocate data within the per-cpu data framework in 519BL31, it should define the following macro. Currently this is only required if 520the platform decides not to use the coherent memory section by undefining the 521``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 522required memory within the the per-cpu data to minimize wastage. 523 524- **#define : PLAT_PCPU_DATA_SIZE** 525 526 Defines the memory (in bytes) to be reserved within the per-cpu data 527 structure for use by the platform layer. 528 529The following constants are optional. They should be defined when the platform 530memory layout implies some image overlaying like in Arm standard platforms. 531 532- **#define : BL31_PROGBITS_LIMIT** 533 534 Defines the maximum address in secure RAM that the BL31's progbits sections 535 can occupy. 536 537- **#define : TSP_PROGBITS_LIMIT** 538 539 Defines the maximum address that the TSP's progbits sections can occupy. 540 541If the platform supports OS-initiated mode, i.e. the build option 542``PSCI_OS_INIT_MODE`` is enabled, and if the platform's maximum power domain 543level for PSCI_CPU_SUSPEND differs from ``PLAT_MAX_PWR_LVL``, the following 544constant must be defined. 545 546- **#define : PLAT_MAX_CPU_SUSPEND_PWR_LVL** 547 548 Defines the maximum power domain level that PSCI_CPU_SUSPEND should apply to. 549 550If the platform port uses the PL061 GPIO driver, the following constant may 551optionally be defined: 552 553- **PLAT_PL061_MAX_GPIOS** 554 Maximum number of GPIOs required by the platform. This allows control how 555 much memory is allocated for PL061 GPIO controllers. The default value is 556 557 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 558 559If the platform port uses the partition driver, the following constant may 560optionally be defined: 561 562- **PLAT_PARTITION_MAX_ENTRIES** 563 Maximum number of partition entries required by the platform. This allows 564 control how much memory is allocated for partition entries. The default 565 value is 128. 566 For example, define the build flag in ``platform.mk``: 567 PLAT_PARTITION_MAX_ENTRIES := 12 568 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 569 570- **PLAT_PARTITION_BLOCK_SIZE** 571 The size of partition block. It could be either 512 bytes or 4096 bytes. 572 The default value is 512. 573 For example, define the build flag in ``platform.mk``: 574 PLAT_PARTITION_BLOCK_SIZE := 4096 575 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) 576 577If the platform port uses the Arm® Ethos™-N NPU driver, the following 578configuration must be performed: 579 580- The NPU SiP service handler must be hooked up. This consists of both the 581 initial setup (``ethosn_smc_setup``) and the handler itself 582 (``ethosn_smc_handler``) 583 584If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support 585enabled, the following constants and configuration must also be defined: 586 587- **ETHOSN_NPU_PROT_FW_NSAID** 588 589 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to 590 access the protected memory that contains the NPU's firmware. 591 592- **ETHOSN_NPU_PROT_DATA_RW_NSAID** 593 594 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 595 read/write access to the protected memory that contains inference data. 596 597- **ETHOSN_NPU_PROT_DATA_RO_NSAID** 598 599 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 600 read-only access to the protected memory that contains inference data. 601 602- **ETHOSN_NPU_NS_RW_DATA_NSAID** 603 604 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 605 read/write access to the non-protected memory. 606 607- **ETHOSN_NPU_NS_RO_DATA_NSAID** 608 609 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 610 read-only access to the non-protected memory. 611 612- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT** 613 614 Defines the physical address range that the NPU's firmware will be loaded 615 into and executed from. 616 617- Configure the platforms TrustZone Controller (TZC) with appropriate regions 618 of protected memory. At minimum this must include a region for the NPU's 619 firmware code and a region for protected inference data, and these must be 620 accessible using the NSAIDs defined above. 621 622- Include the NPU firmware and certificates in the FIP. 623 624- Provide FCONF entries to configure the image source for the NPU firmware 625 and certificates. 626 627- Add MMU mappings such that: 628 629 - BL2 can write the NPU firmware into the region defined by 630 ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT`` 631 - BL31 (SiP service) can read the NPU firmware from the same region 632 633- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images 634 loaded by BL2. 635 636Please see the reference implementation code for the Juno platform as an example. 637 638 639The following constant is optional. It should be defined to override the default 640behaviour of the ``assert()`` function (for example, to save memory). 641 642- **PLAT_LOG_LEVEL_ASSERT** 643 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 644 ``assert()`` prints the name of the file, the line number and the asserted 645 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 646 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 647 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 648 defined, it defaults to ``LOG_LEVEL``. 649 650If the platform port uses the DRTM feature, the following constants must be 651defined: 652 653- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE** 654 655 Maximum Event Log size used by the platform. Platform can decide the maximum 656 size of the Event Log buffer, depending upon the highest hash algorithm 657 chosen and the number of components selected to measure during the DRTM 658 execution flow. 659 660- **#define : PLAT_DRTM_MMAP_ENTRIES** 661 662 Number of the MMAP entries used by the DRTM implementation to calculate the 663 size of address map region of the platform. 664 665File : plat_macros.S [mandatory] 666~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 667 668Each platform must ensure a file of this name is in the system include path with 669the following macro defined. In the Arm development platforms, this file is 670found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 671 672- **Macro : plat_crash_print_regs** 673 674 This macro allows the crash reporting routine to print relevant platform 675 registers in case of an unhandled exception in BL31. This aids in debugging 676 and this macro can be defined to be empty in case register reporting is not 677 desired. 678 679 For instance, GIC or interconnect registers may be helpful for 680 troubleshooting. 681 682Handling Reset 683-------------- 684 685BL1 by default implements the reset vector where execution starts from a cold 686or warm boot. BL31 can be optionally set as a reset vector using the 687``RESET_TO_BL31`` make variable. 688 689For each CPU, the reset vector code is responsible for the following tasks: 690 691#. Distinguishing between a cold boot and a warm boot. 692 693#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 694 the CPU is placed in a platform-specific state until the primary CPU 695 performs the necessary steps to remove it from this state. 696 697#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 698 specific address in the BL31 image in the same processor mode as it was 699 when released from reset. 700 701The following functions need to be implemented by the platform port to enable 702reset vector code to perform the above tasks. 703 704Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 705~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 706 707:: 708 709 Argument : void 710 Return : uintptr_t 711 712This function is called with the MMU and caches disabled 713(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 714distinguishing between a warm and cold reset for the current CPU using 715platform-specific means. If it's a warm reset, then it returns the warm 716reset entrypoint point provided to ``plat_setup_psci_ops()`` during 717BL31 initialization. If it's a cold reset then this function must return zero. 718 719This function does not follow the Procedure Call Standard used by the 720Application Binary Interface for the Arm 64-bit architecture. The caller should 721not assume that callee saved registers are preserved across a call to this 722function. 723 724This function fulfills requirement 1 and 3 listed above. 725 726Note that for platforms that support programming the reset address, it is 727expected that a CPU will start executing code directly at the right address, 728both on a cold and warm reset. In this case, there is no need to identify the 729type of reset nor to query the warm reset entrypoint. Therefore, implementing 730this function is not required on such platforms. 731 732Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 734 735:: 736 737 Argument : void 738 739This function is called with the MMU and data caches disabled. It is responsible 740for placing the executing secondary CPU in a platform-specific state until the 741primary CPU performs the necessary actions to bring it out of that state and 742allow entry into the OS. This function must not return. 743 744In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 745itself off. The primary CPU is responsible for powering up the secondary CPUs 746when normal world software requires them. When booting an EL3 payload instead, 747they stay powered on and are put in a holding pen until their mailbox gets 748populated. 749 750This function fulfills requirement 2 above. 751 752Note that for platforms that can't release secondary CPUs out of reset, only the 753primary CPU will execute the cold boot code. Therefore, implementing this 754function is not required on such platforms. 755 756Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 758 759:: 760 761 Argument : void 762 Return : unsigned int 763 764This function identifies whether the current CPU is the primary CPU or a 765secondary CPU. A return value of zero indicates that the CPU is not the 766primary CPU, while a non-zero return value indicates that the CPU is the 767primary CPU. 768 769Note that for platforms that can't release secondary CPUs out of reset, only the 770primary CPU will execute the cold boot code. Therefore, there is no need to 771distinguish between primary and secondary CPUs and implementing this function is 772not required. 773 774Function : platform_mem_init() [mandatory] 775~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 776 777:: 778 779 Argument : void 780 Return : void 781 782This function is called before any access to data is made by the firmware, in 783order to carry out any essential memory initialization. 784 785Function: plat_get_rotpk_info() 786~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 787 788:: 789 790 Argument : void *, void **, unsigned int *, unsigned int * 791 Return : int 792 793This function is mandatory when Trusted Board Boot is enabled. It returns a 794pointer to the ROTPK stored in the platform (or a hash of it) and its length. 795The ROTPK must be encoded in DER format according to the following ASN.1 796structure: 797 798:: 799 800 AlgorithmIdentifier ::= SEQUENCE { 801 algorithm OBJECT IDENTIFIER, 802 parameters ANY DEFINED BY algorithm OPTIONAL 803 } 804 805 SubjectPublicKeyInfo ::= SEQUENCE { 806 algorithm AlgorithmIdentifier, 807 subjectPublicKey BIT STRING 808 } 809 810In case the function returns a hash of the key: 811 812:: 813 814 DigestInfo ::= SEQUENCE { 815 digestAlgorithm AlgorithmIdentifier, 816 digest OCTET STRING 817 } 818 819The function returns 0 on success. Any other value is treated as error by the 820Trusted Board Boot. The function also reports extra information related 821to the ROTPK in the flags parameter: 822 823:: 824 825 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 826 hash. 827 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 828 verification while the platform ROTPK is not deployed. 829 When this flag is set, the function does not need to 830 return a platform ROTPK, and the authentication 831 framework uses the ROTPK in the certificate without 832 verifying it against the platform value. This flag 833 must not be used in a deployed production environment. 834 835Function: plat_get_nv_ctr() 836~~~~~~~~~~~~~~~~~~~~~~~~~~~ 837 838:: 839 840 Argument : void *, unsigned int * 841 Return : int 842 843This function is mandatory when Trusted Board Boot is enabled. It returns the 844non-volatile counter value stored in the platform in the second argument. The 845cookie in the first argument may be used to select the counter in case the 846platform provides more than one (for example, on platforms that use the default 847TBBR CoT, the cookie will correspond to the OID values defined in 848TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 849 850The function returns 0 on success. Any other value means the counter value could 851not be retrieved from the platform. 852 853Function: plat_set_nv_ctr() 854~~~~~~~~~~~~~~~~~~~~~~~~~~~ 855 856:: 857 858 Argument : void *, unsigned int 859 Return : int 860 861This function is mandatory when Trusted Board Boot is enabled. It sets a new 862counter value in the platform. The cookie in the first argument may be used to 863select the counter (as explained in plat_get_nv_ctr()). The second argument is 864the updated counter value to be written to the NV counter. 865 866The function returns 0 on success. Any other value means the counter value could 867not be updated. 868 869Function: plat_set_nv_ctr2() 870~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 871 872:: 873 874 Argument : void *, const auth_img_desc_t *, unsigned int 875 Return : int 876 877This function is optional when Trusted Board Boot is enabled. If this 878interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 879first argument passed is a cookie and is typically used to 880differentiate between a Non Trusted NV Counter and a Trusted NV 881Counter. The second argument is a pointer to an authentication image 882descriptor and may be used to decide if the counter is allowed to be 883updated or not. The third argument is the updated counter value to 884be written to the NV counter. 885 886The function returns 0 on success. Any other value means the counter value 887either could not be updated or the authentication image descriptor indicates 888that it is not allowed to be updated. 889 890Dynamic Root of Trust for Measurement support (in BL31) 891------------------------------------------------------- 892 893The functions mentioned in this section are mandatory, when platform enables 894DRTM_SUPPORT build flag. 895 896Function : plat_get_addr_mmap() 897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 898 899:: 900 901 Argument : void 902 Return : const mmap_region_t * 903 904This function is used to return the address of the platform *address-map* table, 905which describes the regions of normal memory, memory mapped I/O 906and non-volatile memory. 907 908Function : plat_has_non_host_platforms() 909~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 910 911:: 912 913 Argument : void 914 Return : bool 915 916This function returns *true* if the platform has any trusted devices capable of 917DMA, otherwise returns *false*. 918 919Function : plat_has_unmanaged_dma_peripherals() 920~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 921 922:: 923 924 Argument : void 925 Return : bool 926 927This function returns *true* if platform uses peripherals whose DMA is not 928managed by an SMMU, otherwise returns *false*. 929 930Note - 931If the platform has peripherals that are not managed by the SMMU, then the 932platform should investigate such peripherals to determine whether they can 933be trusted, and such peripherals should be moved under "Non-host platforms" 934if they can be trusted. 935 936Function : plat_get_total_num_smmus() 937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 938 939:: 940 941 Argument : void 942 Return : unsigned int 943 944This function returns the total number of SMMUs in the platform. 945 946Function : plat_enumerate_smmus() 947~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 948:: 949 950 951 Argument : void 952 Return : const uintptr_t *, size_t 953 954This function returns an array of SMMU addresses and the actual number of SMMUs 955reported by the platform. 956 957Function : plat_drtm_get_dma_prot_features() 958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 959 960:: 961 962 Argument : void 963 Return : const plat_drtm_dma_prot_features_t* 964 965This function returns the address of plat_drtm_dma_prot_features_t structure 966containing the maximum number of protected regions and bitmap with the types 967of DMA protection supported by the platform. 968For more details see section 3.3 Table 6 of `DRTM`_ specification. 969 970Function : plat_drtm_dma_prot_get_max_table_bytes() 971~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 972 973:: 974 975 Argument : void 976 Return : uint64_t 977 978This function returns the maximum size of DMA protected regions table in 979bytes. 980 981Function : plat_drtm_get_tpm_features() 982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 983 984:: 985 986 Argument : void 987 Return : const plat_drtm_tpm_features_t* 988 989This function returns the address of *plat_drtm_tpm_features_t* structure 990containing PCR usage schema, TPM-based hash, and firmware hash algorithm 991supported by the platform. 992 993Function : plat_drtm_get_min_size_normal_world_dce() 994~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 995 996:: 997 998 Argument : void 999 Return : uint64_t 1000 1001This function returns the size normal-world DCE of the platform. 1002 1003Function : plat_drtm_get_imp_def_dlme_region_size() 1004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1005 1006:: 1007 1008 Argument : void 1009 Return : uint64_t 1010 1011This function returns the size of implementation defined DLME region 1012of the platform. 1013 1014Function : plat_drtm_get_tcb_hash_table_size() 1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1016 1017:: 1018 1019 Argument : void 1020 Return : uint64_t 1021 1022This function returns the size of TCB hash table of the platform. 1023 1024Function : plat_drtm_get_acpi_tables_region_size() 1025~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1026 1027:: 1028 1029 Argument : void 1030 Return : uint64_t 1031 1032This function returns the size of ACPI tables region of the platform. 1033 1034Function : plat_drtm_get_tcb_hash_features() 1035~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1036 1037:: 1038 1039 Argument : void 1040 Return : uint64_t 1041 1042This function returns the Maximum number of TCB hashes recorded by the 1043platform. 1044For more details see section 3.3 Table 6 of `DRTM`_ specification. 1045 1046Function : plat_drtm_get_dlme_img_auth_features() 1047~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1048 1049:: 1050 1051 Argument : void 1052 Return : uint64_t 1053 1054This function returns the DLME image authentication features. 1055For more details see section 3.3 Table 6 of `DRTM`_ specification. 1056 1057Function : plat_drtm_validate_ns_region() 1058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1059 1060:: 1061 1062 Argument : uintptr_t, uintptr_t 1063 Return : int 1064 1065This function validates that given region is within the Non-Secure region 1066of DRAM. This function takes a region start address and size an input 1067arguments, and returns 0 on success and -1 on failure. 1068 1069Function : plat_set_drtm_error() 1070~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1071 1072:: 1073 1074 Argument : uint64_t 1075 Return : int 1076 1077This function writes a 64 bit error code received as input into 1078non-volatile storage and returns 0 on success and -1 on failure. 1079 1080Function : plat_get_drtm_error() 1081~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1082 1083:: 1084 1085 Argument : uint64_t* 1086 Return : int 1087 1088This function reads a 64 bit error code from the non-volatile storage 1089into the received address, and returns 0 on success and -1 on failure. 1090 1091Common mandatory function modifications 1092--------------------------------------- 1093 1094The following functions are mandatory functions which need to be implemented 1095by the platform port. 1096 1097Function : plat_my_core_pos() 1098~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1099 1100:: 1101 1102 Argument : void 1103 Return : unsigned int 1104 1105This function returns the index of the calling CPU which is used as a 1106CPU-specific linear index into blocks of memory (for example while allocating 1107per-CPU stacks). This function will be invoked very early in the 1108initialization sequence which mandates that this function should be 1109implemented in assembly and should not rely on the availability of a C 1110runtime environment. This function can clobber x0 - x8 and must preserve 1111x9 - x29. 1112 1113This function plays a crucial role in the power domain topology framework in 1114PSCI and details of this can be found in 1115:ref:`PSCI Power Domain Tree Structure`. 1116 1117Function : plat_core_pos_by_mpidr() 1118~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1119 1120:: 1121 1122 Argument : u_register_t 1123 Return : int 1124 1125This function validates the ``MPIDR`` of a CPU and converts it to an index, 1126which can be used as a CPU-specific linear index into blocks of memory. In 1127case the ``MPIDR`` is invalid, this function returns -1. This function will only 1128be invoked by BL31 after the power domain topology is initialized and can 1129utilize the C runtime environment. For further details about how TF-A 1130represents the power domain topology and how this relates to the linear CPU 1131index, please refer :ref:`PSCI Power Domain Tree Structure`. 1132 1133Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 1134~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1135 1136:: 1137 1138 Arguments : void **heap_addr, size_t *heap_size 1139 Return : int 1140 1141This function is invoked during Mbed TLS library initialisation to get a heap, 1142by means of a starting address and a size. This heap will then be used 1143internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 1144must be able to provide a heap to it. 1145 1146A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 1147which a heap is statically reserved during compile time inside every image 1148(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 1149the function simply returns the address and size of this "pre-allocated" heap. 1150For a platform to use this default implementation, only a call to the helper 1151from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 1152 1153However, by writting their own implementation, platforms have the potential to 1154optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 1155shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 1156twice. 1157 1158On success the function should return 0 and a negative error code otherwise. 1159 1160Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] 1161~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1162 1163:: 1164 1165 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, 1166 size_t *key_len, unsigned int *flags, const uint8_t *img_id, 1167 size_t img_id_len 1168 Return : int 1169 1170This function provides a symmetric key (either SSK or BSSK depending on 1171fw_enc_status) which is invoked during runtime decryption of encrypted 1172firmware images. `plat/common/plat_bl_common.c` provides a dummy weak 1173implementation for testing purposes which must be overridden by the platform 1174trying to implement a real world firmware encryption use-case. 1175 1176It also allows the platform to pass symmetric key identifier rather than 1177actual symmetric key which is useful in cases where the crypto backend provides 1178secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` 1179flag must be set in ``flags``. 1180 1181In addition to above a platform may also choose to provide an image specific 1182symmetric key/identifier using img_id. 1183 1184On success the function should return 0 and a negative error code otherwise. 1185 1186Note that this API depends on ``DECRYPTION_SUPPORT`` build flag. 1187 1188Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1] 1189~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1190 1191:: 1192 1193 Argument : const struct fwu_metadata *metadata 1194 Return : void 1195 1196This function is mandatory when PSA_FWU_SUPPORT is enabled. 1197It provides a means to retrieve image specification (offset in 1198non-volatile storage and length) of active/updated images using the passed 1199FWU metadata, and update I/O policies of active/updated images using retrieved 1200image specification information. 1201Further I/O layer operations such as I/O open, I/O read, etc. on these 1202images rely on this function call. 1203 1204In Arm platforms, this function is used to set an I/O policy of the FIP image, 1205container of all active/updated secure and non-secure images. 1206 1207Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1] 1208~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1209 1210:: 1211 1212 Argument : unsigned int image_id, uintptr_t *dev_handle, 1213 uintptr_t *image_spec 1214 Return : int 1215 1216This function is mandatory when PSA_FWU_SUPPORT is enabled. It is 1217responsible for setting up the platform I/O policy of the requested metadata 1218image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will 1219be used to load this image from the platform's non-volatile storage. 1220 1221FWU metadata can not be always stored as a raw image in non-volatile storage 1222to define its image specification (offset in non-volatile storage and length) 1223statically in I/O policy. 1224For example, the FWU metadata image is stored as a partition inside the GUID 1225partition table image. Its specification is defined in the partition table 1226that needs to be parsed dynamically. 1227This function provides a means to retrieve such dynamic information to set 1228the I/O policy of the FWU metadata image. 1229Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata 1230image relies on this function call. 1231 1232It returns '0' on success, otherwise a negative error value on error. 1233Alongside, returns device handle and image specification from the I/O policy 1234of the requested FWU metadata image. 1235 1236Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1] 1237~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1238 1239:: 1240 1241 Argument : void 1242 Return : uint32_t 1243 1244This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the 1245means to retrieve the boot index value from the platform. The boot index is the 1246bank from which the platform has booted the firmware images. 1247 1248By default, the platform will read the metadata structure and try to boot from 1249the active bank. If the platform fails to boot from the active bank due to 1250reasons like an Authentication failure, or on crossing a set number of watchdog 1251resets while booting from the active bank, the platform can then switch to boot 1252from a different bank. This function then returns the bank that the platform 1253should boot its images from. 1254 1255Common optional modifications 1256----------------------------- 1257 1258The following are helper functions implemented by the firmware that perform 1259common platform-specific tasks. A platform may choose to override these 1260definitions. 1261 1262Function : plat_set_my_stack() 1263~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1264 1265:: 1266 1267 Argument : void 1268 Return : void 1269 1270This function sets the current stack pointer to the normal memory stack that 1271has been allocated for the current CPU. For BL images that only require a 1272stack for the primary CPU, the UP version of the function is used. The size 1273of the stack allocated to each CPU is specified by the platform defined 1274constant ``PLATFORM_STACK_SIZE``. 1275 1276Common implementations of this function for the UP and MP BL images are 1277provided in ``plat/common/aarch64/platform_up_stack.S`` and 1278``plat/common/aarch64/platform_mp_stack.S`` 1279 1280Function : plat_get_my_stack() 1281~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1282 1283:: 1284 1285 Argument : void 1286 Return : uintptr_t 1287 1288This function returns the base address of the normal memory stack that 1289has been allocated for the current CPU. For BL images that only require a 1290stack for the primary CPU, the UP version of the function is used. The size 1291of the stack allocated to each CPU is specified by the platform defined 1292constant ``PLATFORM_STACK_SIZE``. 1293 1294Common implementations of this function for the UP and MP BL images are 1295provided in ``plat/common/aarch64/platform_up_stack.S`` and 1296``plat/common/aarch64/platform_mp_stack.S`` 1297 1298Function : plat_report_exception() 1299~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1300 1301:: 1302 1303 Argument : unsigned int 1304 Return : void 1305 1306A platform may need to report various information about its status when an 1307exception is taken, for example the current exception level, the CPU security 1308state (secure/non-secure), the exception type, and so on. This function is 1309called in the following circumstances: 1310 1311- In BL1, whenever an exception is taken. 1312- In BL2, whenever an exception is taken. 1313 1314The default implementation doesn't do anything, to avoid making assumptions 1315about the way the platform displays its status information. 1316 1317For AArch64, this function receives the exception type as its argument. 1318Possible values for exceptions types are listed in the 1319``include/common/bl_common.h`` header file. Note that these constants are not 1320related to any architectural exception code; they are just a TF-A convention. 1321 1322For AArch32, this function receives the exception mode as its argument. 1323Possible values for exception modes are listed in the 1324``include/lib/aarch32/arch.h`` header file. 1325 1326Function : plat_reset_handler() 1327~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1328 1329:: 1330 1331 Argument : void 1332 Return : void 1333 1334A platform may need to do additional initialization after reset. This function 1335allows the platform to do the platform specific initializations. Platform 1336specific errata workarounds could also be implemented here. The API should 1337preserve the values of callee saved registers x19 to x29. 1338 1339The default implementation doesn't do anything. If a platform needs to override 1340the default implementation, refer to the :ref:`Firmware Design` for general 1341guidelines. 1342 1343Function : plat_disable_acp() 1344~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1345 1346:: 1347 1348 Argument : void 1349 Return : void 1350 1351This API allows a platform to disable the Accelerator Coherency Port (if 1352present) during a cluster power down sequence. The default weak implementation 1353doesn't do anything. Since this API is called during the power down sequence, 1354it has restrictions for stack usage and it can use the registers x0 - x17 as 1355scratch registers. It should preserve the value in x18 register as it is used 1356by the caller to store the return address. 1357 1358Function : plat_error_handler() 1359~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1360 1361:: 1362 1363 Argument : int 1364 Return : void 1365 1366This API is called when the generic code encounters an error situation from 1367which it cannot continue. It allows the platform to perform error reporting or 1368recovery actions (for example, reset the system). This function must not return. 1369 1370The parameter indicates the type of error using standard codes from ``errno.h``. 1371Possible errors reported by the generic code are: 1372 1373- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 1374 Board Boot is enabled) 1375- ``-ENOENT``: the requested image or certificate could not be found or an IO 1376 error was detected 1377- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 1378 error is usually an indication of an incorrect array size 1379 1380The default implementation simply spins. 1381 1382Function : plat_panic_handler() 1383~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1384 1385:: 1386 1387 Argument : void 1388 Return : void 1389 1390This API is called when the generic code encounters an unexpected error 1391situation from which it cannot recover. This function must not return, 1392and must be implemented in assembly because it may be called before the C 1393environment is initialized. 1394 1395.. note:: 1396 The address from where it was called is stored in x30 (Link Register). 1397 The default implementation simply spins. 1398 1399Function : plat_system_reset() 1400~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1401 1402:: 1403 1404 Argument : void 1405 Return : void 1406 1407This function is used by the platform to resets the system. It can be used 1408in any specific use-case where system needs to be resetted. For example, 1409in case of DRTM implementation this function reset the system after 1410writing the DRTM error code in the non-volatile storage. This function 1411never returns. Failure in reset results in panic. 1412 1413Function : plat_get_bl_image_load_info() 1414~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1415 1416:: 1417 1418 Argument : void 1419 Return : bl_load_info_t * 1420 1421This function returns pointer to the list of images that the platform has 1422populated to load. This function is invoked in BL2 to load the 1423BL3xx images. 1424 1425Function : plat_get_next_bl_params() 1426~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1427 1428:: 1429 1430 Argument : void 1431 Return : bl_params_t * 1432 1433This function returns a pointer to the shared memory that the platform has 1434kept aside to pass TF-A related information that next BL image needs. This 1435function is invoked in BL2 to pass this information to the next BL 1436image. 1437 1438Function : plat_get_stack_protector_canary() 1439~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1440 1441:: 1442 1443 Argument : void 1444 Return : u_register_t 1445 1446This function returns a random value that is used to initialize the canary used 1447when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1448value will weaken the protection as the attacker could easily write the right 1449value as part of the attack most of the time. Therefore, it should return a 1450true random number. 1451 1452.. warning:: 1453 For the protection to be effective, the global data need to be placed at 1454 a lower address than the stack bases. Failure to do so would allow an 1455 attacker to overwrite the canary as part of the stack buffer overflow attack. 1456 1457Function : plat_flush_next_bl_params() 1458~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1459 1460:: 1461 1462 Argument : void 1463 Return : void 1464 1465This function flushes to main memory all the image params that are passed to 1466next image. This function is invoked in BL2 to flush this information 1467to the next BL image. 1468 1469Function : plat_log_get_prefix() 1470~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1471 1472:: 1473 1474 Argument : unsigned int 1475 Return : const char * 1476 1477This function defines the prefix string corresponding to the `log_level` to be 1478prepended to all the log output from TF-A. The `log_level` (argument) will 1479correspond to one of the standard log levels defined in debug.h. The platform 1480can override the common implementation to define a different prefix string for 1481the log output. The implementation should be robust to future changes that 1482increase the number of log levels. 1483 1484Function : plat_get_soc_version() 1485~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1486 1487:: 1488 1489 Argument : void 1490 Return : int32_t 1491 1492This function returns soc version which mainly consist of below fields 1493 1494:: 1495 1496 soc_version[30:24] = JEP-106 continuation code for the SiP 1497 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 1498 soc_version[15:0] = Implementation defined SoC ID 1499 1500Function : plat_get_soc_revision() 1501~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1502 1503:: 1504 1505 Argument : void 1506 Return : int32_t 1507 1508This function returns soc revision in below format 1509 1510:: 1511 1512 soc_revision[0:30] = SOC revision of specific SOC 1513 1514Function : plat_is_smccc_feature_available() 1515~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1516 1517:: 1518 1519 Argument : u_register_t 1520 Return : int32_t 1521 1522This function returns SMC_ARCH_CALL_SUCCESS if the platform supports 1523the SMCCC function specified in the argument; otherwise returns 1524SMC_ARCH_CALL_NOT_SUPPORTED. 1525 1526Function : plat_can_cmo() 1527~~~~~~~~~~~~~~~~~~~~~~~~~ 1528 1529:: 1530 1531 Argument : void 1532 Return : uint64_t 1533 1534When CONDITIONAL_CMO flag is enabled: 1535 1536- This function indicates whether cache management operations should be 1537 performed. It returns 0 if CMOs should be skipped and non-zero 1538 otherwise. 1539- The function must not clobber x1, x2 and x3. It's also not safe to rely on 1540 stack. Otherwise obey AAPCS. 1541 1542Struct: plat_try_images_ops [optional] 1543~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1544 1545This optional structure holds platform hooks for alternative images load. 1546It has to be defined in platform code and registered by calling 1547plat_setup_try_img_ops() function, passing it the address of the 1548plat_try_images_ops struct. 1549 1550Function : plat_setup_try_img_ops [optional] 1551............................................ 1552 1553:: 1554 1555 Argument : const struct plat_try_images_ops * 1556 Return : void 1557 1558This optional function is called to register platform try images ops, given 1559as argument. 1560 1561Function : plat_try_images_ops.next_instance [optional] 1562....................................................... 1563 1564:: 1565 1566 Argument : unsigned int image_id 1567 Return : int 1568 1569This optional function tries to load images from alternative places. 1570In case PSA FWU is not used, it can be any instance or media. If PSA FWU is 1571used, it is mandatory that the backup image is on the same media. 1572This is required for MTD devices like NAND. 1573The argument is the ID of the image for which we are looking for an alternative 1574place. It returns 0 in case of success and a negative errno value otherwise. 1575 1576Modifications specific to a Boot Loader stage 1577--------------------------------------------- 1578 1579Boot Loader Stage 1 (BL1) 1580------------------------- 1581 1582BL1 implements the reset vector where execution starts from after a cold or 1583warm boot. For each CPU, BL1 is responsible for the following tasks: 1584 1585#. Handling the reset as described in section 2.2 1586 1587#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1588 only this CPU executes the remaining BL1 code, including loading and passing 1589 control to the BL2 stage. 1590 1591#. Identifying and starting the Firmware Update process (if required). 1592 1593#. Loading the BL2 image from non-volatile storage into secure memory at the 1594 address specified by the platform defined constant ``BL2_BASE``. 1595 1596#. Populating a ``meminfo`` structure with the following information in memory, 1597 accessible by BL2 immediately upon entry. 1598 1599 :: 1600 1601 meminfo.total_base = Base address of secure RAM visible to BL2 1602 meminfo.total_size = Size of secure RAM visible to BL2 1603 1604 By default, BL1 places this ``meminfo`` structure at the end of secure 1605 memory visible to BL2. 1606 1607 It is possible for the platform to decide where it wants to place the 1608 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1609 BL2 by overriding the weak default implementation of 1610 ``bl1_plat_handle_post_image_load`` API. 1611 1612The following functions need to be implemented by the platform port to enable 1613BL1 to perform the above tasks. 1614 1615Function : bl1_early_platform_setup() [mandatory] 1616~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1617 1618:: 1619 1620 Argument : void 1621 Return : void 1622 1623This function executes with the MMU and data caches disabled. It is only called 1624by the primary CPU. 1625 1626On Arm standard platforms, this function: 1627 1628- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1629 1630- Initializes a UART (PL011 console), which enables access to the ``printf`` 1631 family of functions in BL1. 1632 1633- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1634 the CCI slave interface corresponding to the cluster that includes the 1635 primary CPU. 1636 1637Function : bl1_plat_arch_setup() [mandatory] 1638~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1639 1640:: 1641 1642 Argument : void 1643 Return : void 1644 1645This function performs any platform-specific and architectural setup that the 1646platform requires. Platform-specific setup might include configuration of 1647memory controllers and the interconnect. 1648 1649In Arm standard platforms, this function enables the MMU. 1650 1651This function helps fulfill requirement 2 above. 1652 1653Function : bl1_platform_setup() [mandatory] 1654~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1655 1656:: 1657 1658 Argument : void 1659 Return : void 1660 1661This function executes with the MMU and data caches enabled. It is responsible 1662for performing any remaining platform-specific setup that can occur after the 1663MMU and data cache have been enabled. 1664 1665In Arm standard platforms, this function initializes the storage abstraction 1666layer used to load the next bootloader image. 1667 1668This function helps fulfill requirement 4 above. 1669 1670Function : bl1_plat_sec_mem_layout() [mandatory] 1671~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1672 1673:: 1674 1675 Argument : void 1676 Return : meminfo * 1677 1678This function should only be called on the cold boot path. It executes with the 1679MMU and data caches enabled. The pointer returned by this function must point to 1680a ``meminfo`` structure containing the extents and availability of secure RAM for 1681the BL1 stage. 1682 1683:: 1684 1685 meminfo.total_base = Base address of secure RAM visible to BL1 1686 meminfo.total_size = Size of secure RAM visible to BL1 1687 1688This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1689populates a similar structure to tell BL2 the extents of memory available for 1690its own use. 1691 1692This function helps fulfill requirements 4 and 5 above. 1693 1694Function : bl1_plat_prepare_exit() [optional] 1695~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1696 1697:: 1698 1699 Argument : entry_point_info_t * 1700 Return : void 1701 1702This function is called prior to exiting BL1 in response to the 1703``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1704platform specific clean up or bookkeeping operations before transferring 1705control to the next image. It receives the address of the ``entry_point_info_t`` 1706structure passed from BL2. This function runs with MMU disabled. 1707 1708Function : bl1_plat_set_ep_info() [optional] 1709~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1710 1711:: 1712 1713 Argument : unsigned int image_id, entry_point_info_t *ep_info 1714 Return : void 1715 1716This function allows platforms to override ``ep_info`` for the given ``image_id``. 1717 1718The default implementation just returns. 1719 1720Function : bl1_plat_get_next_image_id() [optional] 1721~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1722 1723:: 1724 1725 Argument : void 1726 Return : unsigned int 1727 1728This and the following function must be overridden to enable the FWU feature. 1729 1730BL1 calls this function after platform setup to identify the next image to be 1731loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1732with the normal boot sequence, which loads and executes BL2. If the platform 1733returns a different image id, BL1 assumes that Firmware Update is required. 1734 1735The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1736platforms override this function to detect if firmware update is required, and 1737if so, return the first image in the firmware update process. 1738 1739Function : bl1_plat_get_image_desc() [optional] 1740~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1741 1742:: 1743 1744 Argument : unsigned int image_id 1745 Return : image_desc_t * 1746 1747BL1 calls this function to get the image descriptor information ``image_desc_t`` 1748for the provided ``image_id`` from the platform. 1749 1750The default implementation always returns a common BL2 image descriptor. Arm 1751standard platforms return an image descriptor corresponding to BL2 or one of 1752the firmware update images defined in the Trusted Board Boot Requirements 1753specification. 1754 1755Function : bl1_plat_handle_pre_image_load() [optional] 1756~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1757 1758:: 1759 1760 Argument : unsigned int image_id 1761 Return : int 1762 1763This function can be used by the platforms to update/use image information 1764corresponding to ``image_id``. This function is invoked in BL1, both in cold 1765boot and FWU code path, before loading the image. 1766 1767Function : bl1_plat_calc_bl2_layout() [optional] 1768~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1769 1770:: 1771 1772 Argument : const meminfo_t *bl1_mem_layout, meminfo_t *bl2_mem_layout 1773 Return : void 1774 1775This utility function calculates the memory layout of BL2, representing it in a 1776`meminfo_t` structure. The default implementation derives this layout from the 1777positioning of BL1’s RW data at the top of the memory layout. 1778 1779Function : bl1_plat_handle_post_image_load() [optional] 1780~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1781 1782:: 1783 1784 Argument : unsigned int image_id 1785 Return : int 1786 1787This function can be used by the platforms to update/use image information 1788corresponding to ``image_id``. This function is invoked in BL1, both in cold 1789boot and FWU code path, after loading and authenticating the image. 1790 1791The default weak implementation of this function calculates the amount of 1792Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1793structure at the beginning of this free memory and populates it. The address 1794of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1795information to BL2. 1796 1797Function : bl1_plat_fwu_done() [optional] 1798~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1799 1800:: 1801 1802 Argument : unsigned int image_id, uintptr_t image_src, 1803 unsigned int image_size 1804 Return : void 1805 1806BL1 calls this function when the FWU process is complete. It must not return. 1807The platform may override this function to take platform specific action, for 1808example to initiate the normal boot flow. 1809 1810The default implementation spins forever. 1811 1812Function : bl1_plat_mem_check() [mandatory] 1813~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1814 1815:: 1816 1817 Argument : uintptr_t mem_base, unsigned int mem_size, 1818 unsigned int flags 1819 Return : int 1820 1821BL1 calls this function while handling FWU related SMCs, more specifically when 1822copying or authenticating an image. Its responsibility is to ensure that the 1823region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1824that this memory corresponds to either a secure or non-secure memory region as 1825indicated by the security state of the ``flags`` argument. 1826 1827This function can safely assume that the value resulting from the addition of 1828``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1829overflow. 1830 1831This function must return 0 on success, a non-null error code otherwise. 1832 1833The default implementation of this function asserts therefore platforms must 1834override it when using the FWU feature. 1835 1836Boot Loader Stage 2 (BL2) 1837------------------------- 1838 1839The BL2 stage is executed only by the primary CPU, which is determined in BL1 1840using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1841``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1842``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1843non-volatile storage to secure/non-secure RAM. After all the images are loaded 1844then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1845images to be passed to the next BL image. 1846 1847The following functions must be implemented by the platform port to enable BL2 1848to perform the above tasks. 1849 1850Function : bl2_early_platform_setup2() [mandatory] 1851~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1852 1853:: 1854 1855 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1856 Return : void 1857 1858This function executes with the MMU and data caches disabled. It is only called 1859by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1860are platform specific. 1861 1862On Arm standard platforms, the arguments received are : 1863 1864 arg0 - Points to load address of FW_CONFIG 1865 1866 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1867 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1868 1869On Arm standard platforms, this function also: 1870 1871- Initializes a UART (PL011 console), which enables access to the ``printf`` 1872 family of functions in BL2. 1873 1874- Initializes the storage abstraction layer used to load further bootloader 1875 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1876 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1877 1878Function : bl2_plat_arch_setup() [mandatory] 1879~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1880 1881:: 1882 1883 Argument : void 1884 Return : void 1885 1886This function executes with the MMU and data caches disabled. It is only called 1887by the primary CPU. 1888 1889The purpose of this function is to perform any architectural initialization 1890that varies across platforms. 1891 1892On Arm standard platforms, this function enables the MMU. 1893 1894Function : bl2_platform_setup() [mandatory] 1895~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1896 1897:: 1898 1899 Argument : void 1900 Return : void 1901 1902This function may execute with the MMU and data caches enabled if the platform 1903port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1904called by the primary CPU. 1905 1906The purpose of this function is to perform any platform initialization 1907specific to BL2. 1908 1909In Arm standard platforms, this function performs security setup, including 1910configuration of the TrustZone controller to allow non-secure masters access 1911to most of DRAM. Part of DRAM is reserved for secure world use. 1912 1913Function : bl2_plat_handle_pre_image_load() [optional] 1914~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1915 1916:: 1917 1918 Argument : unsigned int 1919 Return : int 1920 1921This function can be used by the platforms to update/use image information 1922for given ``image_id``. This function is currently invoked in BL2 before 1923loading each image. 1924 1925Function : bl2_plat_handle_post_image_load() [optional] 1926~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1927 1928:: 1929 1930 Argument : unsigned int 1931 Return : int 1932 1933This function can be used by the platforms to update/use image information 1934for given ``image_id``. This function is currently invoked in BL2 after 1935loading each image. 1936 1937Function : bl2_plat_preload_setup [optional] 1938~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1939 1940:: 1941 1942 Argument : void 1943 Return : void 1944 1945This optional function performs any BL2 platform initialization 1946required before image loading, that is not done later in 1947bl2_platform_setup(). 1948 1949Boot Loader Stage 2 (BL2) at EL3 1950-------------------------------- 1951 1952When the platform has a non-TF-A Boot ROM it is desirable to jump 1953directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1954execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` 1955document for more information. 1956 1957All mandatory functions of BL2 must be implemented, except the functions 1958bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 1959their work is done now by bl2_el3_early_platform_setup and 1960bl2_el3_plat_arch_setup. These functions should generally implement 1961the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 1962 1963 1964Function : bl2_el3_early_platform_setup() [mandatory] 1965~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1966 1967:: 1968 1969 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1970 Return : void 1971 1972This function executes with the MMU and data caches disabled. It is only called 1973by the primary CPU. This function receives four parameters which can be used 1974by the platform to pass any needed information from the Boot ROM to BL2. 1975 1976On Arm standard platforms, this function does the following: 1977 1978- Initializes a UART (PL011 console), which enables access to the ``printf`` 1979 family of functions in BL2. 1980 1981- Initializes the storage abstraction layer used to load further bootloader 1982 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1983 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1984 1985- Initializes the private variables that define the memory layout used. 1986 1987Function : bl2_el3_plat_arch_setup() [mandatory] 1988~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1989 1990:: 1991 1992 Argument : void 1993 Return : void 1994 1995This function executes with the MMU and data caches disabled. It is only called 1996by the primary CPU. 1997 1998The purpose of this function is to perform any architectural initialization 1999that varies across platforms. 2000 2001On Arm standard platforms, this function enables the MMU. 2002 2003Function : bl2_el3_plat_prepare_exit() [optional] 2004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2005 2006:: 2007 2008 Argument : void 2009 Return : void 2010 2011This function is called prior to exiting BL2 and run the next image. 2012It should be used to perform platform specific clean up or bookkeeping 2013operations before transferring control to the next image. This function 2014runs with MMU disabled. 2015 2016FWU Boot Loader Stage 2 (BL2U) 2017------------------------------ 2018 2019The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 2020process and is executed only by the primary CPU. BL1 passes control to BL2U at 2021``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 2022 2023#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 2024 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 2025 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 2026 should be copied from. Subsequent handling of the SCP_BL2U image is 2027 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 2028 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 2029 2030#. Any platform specific setup required to perform the FWU process. For 2031 example, Arm standard platforms initialize the TZC controller so that the 2032 normal world can access DDR memory. 2033 2034The following functions must be implemented by the platform port to enable 2035BL2U to perform the tasks mentioned above. 2036 2037Function : bl2u_early_platform_setup() [mandatory] 2038~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2039 2040:: 2041 2042 Argument : meminfo *mem_info, void *plat_info 2043 Return : void 2044 2045This function executes with the MMU and data caches disabled. It is only 2046called by the primary CPU. The arguments to this function is the address 2047of the ``meminfo`` structure and platform specific info provided by BL1. 2048 2049The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 2050private storage as the original memory may be subsequently overwritten by BL2U. 2051 2052On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 2053to extract SCP_BL2U image information, which is then copied into a private 2054variable. 2055 2056Function : bl2u_plat_arch_setup() [mandatory] 2057~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2058 2059:: 2060 2061 Argument : void 2062 Return : void 2063 2064This function executes with the MMU and data caches disabled. It is only 2065called by the primary CPU. 2066 2067The purpose of this function is to perform any architectural initialization 2068that varies across platforms, for example enabling the MMU (since the memory 2069map differs across platforms). 2070 2071Function : bl2u_platform_setup() [mandatory] 2072~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2073 2074:: 2075 2076 Argument : void 2077 Return : void 2078 2079This function may execute with the MMU and data caches enabled if the platform 2080port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 2081called by the primary CPU. 2082 2083The purpose of this function is to perform any platform initialization 2084specific to BL2U. 2085 2086In Arm standard platforms, this function performs security setup, including 2087configuration of the TrustZone controller to allow non-secure masters access 2088to most of DRAM. Part of DRAM is reserved for secure world use. 2089 2090Function : bl2u_plat_handle_scp_bl2u() [optional] 2091~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2092 2093:: 2094 2095 Argument : void 2096 Return : int 2097 2098This function is used to perform any platform-specific actions required to 2099handle the SCP firmware. Typically it transfers the image into SCP memory using 2100a platform-specific protocol and waits until SCP executes it and signals to the 2101Application Processor (AP) for BL2U execution to continue. 2102 2103This function returns 0 on success, a negative error code otherwise. 2104This function is included if SCP_BL2U_BASE is defined. 2105 2106Boot Loader Stage 3-1 (BL31) 2107---------------------------- 2108 2109During cold boot, the BL31 stage is executed only by the primary CPU. This is 2110determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 2111control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 2112CPUs. BL31 executes at EL3 and is responsible for: 2113 2114#. Re-initializing all architectural and platform state. Although BL1 performs 2115 some of this initialization, BL31 remains resident in EL3 and must ensure 2116 that EL3 architectural and platform state is completely initialized. It 2117 should make no assumptions about the system state when it receives control. 2118 2119#. Passing control to a normal world BL image, pre-loaded at a platform- 2120 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 2121 populated by BL2 in memory to do this. 2122 2123#. Providing runtime firmware services. Currently, BL31 only implements a 2124 subset of the Power State Coordination Interface (PSCI) API as a runtime 2125 service. See :ref:`psci_in_bl31` below for details of porting the PSCI 2126 implementation. 2127 2128#. Optionally passing control to the BL32 image, pre-loaded at a platform- 2129 specific address by BL2. BL31 exports a set of APIs that allow runtime 2130 services to specify the security state in which the next image should be 2131 executed and run the corresponding image. On ARM platforms, BL31 uses the 2132 ``bl_params`` list populated by BL2 in memory to do this. 2133 2134If BL31 is a reset vector, It also needs to handle the reset as specified in 2135section 2.2 before the tasks described above. 2136 2137The following functions must be implemented by the platform port to enable BL31 2138to perform the above tasks. 2139 2140Function : bl31_early_platform_setup2() [mandatory] 2141~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2142 2143:: 2144 2145 Argument : u_register_t, u_register_t, u_register_t, u_register_t 2146 Return : void 2147 2148This function executes with the MMU and data caches disabled. It is only called 2149by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 2150platform specific. 2151 2152In Arm standard platforms, the arguments received are : 2153 2154 arg0 - The pointer to the head of `bl_params_t` list 2155 which is list of executable images following BL31, 2156 2157 arg1 - Points to load address of SOC_FW_CONFIG if present 2158 except in case of Arm FVP and Juno platform. 2159 2160 In case of Arm FVP and Juno platform, points to load address 2161 of FW_CONFIG. 2162 2163 arg2 - Points to load address of HW_CONFIG if present 2164 2165 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 2166 used in release builds. 2167 2168The function runs through the `bl_param_t` list and extracts the entry point 2169information for BL32 and BL33. It also performs the following: 2170 2171- Initialize a UART (PL011 console), which enables access to the ``printf`` 2172 family of functions in BL31. 2173 2174- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 2175 CCI slave interface corresponding to the cluster that includes the primary 2176 CPU. 2177 2178Function : bl31_plat_arch_setup() [mandatory] 2179~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2180 2181:: 2182 2183 Argument : void 2184 Return : void 2185 2186This function executes with the MMU and data caches disabled. It is only called 2187by the primary CPU. 2188 2189The purpose of this function is to perform any architectural initialization 2190that varies across platforms. 2191 2192On Arm standard platforms, this function enables the MMU. 2193 2194Function : bl31_platform_setup() [mandatory] 2195~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2196 2197:: 2198 2199 Argument : void 2200 Return : void 2201 2202This function may execute with the MMU and data caches enabled if the platform 2203port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 2204called by the primary CPU. 2205 2206The purpose of this function is to complete platform initialization so that both 2207BL31 runtime services and normal world software can function correctly. 2208 2209On Arm standard platforms, this function does the following: 2210 2211- Initialize the generic interrupt controller. 2212 2213 Depending on the GIC driver selected by the platform, the appropriate GICv2 2214 or GICv3 initialization will be done, which mainly consists of: 2215 2216 - Enable secure interrupts in the GIC CPU interface. 2217 - Disable the legacy interrupt bypass mechanism. 2218 - Configure the priority mask register to allow interrupts of all priorities 2219 to be signaled to the CPU interface. 2220 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 2221 - Target all secure SPIs to CPU0. 2222 - Enable these secure interrupts in the GIC distributor. 2223 - Configure all other interrupts as non-secure. 2224 - Enable signaling of secure interrupts in the GIC distributor. 2225 2226- Enable system-level implementation of the generic timer counter through the 2227 memory mapped interface. 2228 2229- Grant access to the system counter timer module 2230 2231- Initialize the power controller device. 2232 2233 In particular, initialise the locks that prevent concurrent accesses to the 2234 power controller device. 2235 2236Function : bl31_plat_runtime_setup() [optional] 2237~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2238 2239:: 2240 2241 Argument : void 2242 Return : void 2243 2244The purpose of this function is to allow the platform to perform any BL31 runtime 2245setup just prior to BL31 exit during cold boot. The default weak implementation 2246of this function is empty. Any platform that needs to perform additional runtime 2247setup, before BL31 exits, will need to override this function. 2248 2249Function : bl31_plat_get_next_image_ep_info() [mandatory] 2250~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2251 2252:: 2253 2254 Argument : uint32_t 2255 Return : entry_point_info * 2256 2257This function may execute with the MMU and data caches enabled if the platform 2258port does the necessary initializations in ``bl31_plat_arch_setup()``. 2259 2260This function is called by ``bl31_main()`` to retrieve information provided by 2261BL2 for the next image in the security state specified by the argument. BL31 2262uses this information to pass control to that image in the specified security 2263state. This function must return a pointer to the ``entry_point_info`` structure 2264(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2265should return NULL otherwise. 2266 2267Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1] 2268~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2269 2270:: 2271 2272 Argument : uintptr_t, size_t *, uintptr_t, size_t, size_t * 2273 Return : int 2274 2275This function returns the Platform attestation token. If the full token does 2276not fit in the buffer, the function will return a hunk of the token and 2277indicate how many bytes were copied and how many are pending. Multiple calls 2278to this function may be needed to retrieve the entire token. 2279 2280The parameters of the function are: 2281 2282 arg0 - A pointer to the buffer where the Platform token should be copied by 2283 this function. If the platform token does not completely fit in the 2284 buffer, the function may return a piece of the token only. 2285 2286 arg1 - Contains the size (in bytes) of the buffer passed in arg0. In 2287 addition, this parameter is used by the function to return the size 2288 of the platform token length hunk copied to the buffer. 2289 2290 arg2 - A pointer to the buffer where the challenge object is stored. 2291 2292 arg3 - The length of the challenge object in bytes. Possible values are 32, 2293 48 and 64. This argument must be zero for subsequent calls to 2294 retrieve the remaining hunks of the token. 2295 2296 arg4 - Returns the remaining length of the token (in bytes) that is yet to 2297 be returned in further calls. 2298 2299The function returns 0 on success, -EINVAL on failure and -EAGAIN if the 2300resource associated with the platform token retrieval is busy. 2301 2302Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] 2303~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2304 2305:: 2306 2307 Argument : uintptr_t, size_t *, unsigned int 2308 Return : int 2309 2310This function returns the delegated realm attestation key which will be used to 2311sign Realm attestation token. The API currently only supports P-384 ECC curve 2312key. 2313 2314The parameters of the function are: 2315 2316 arg0 - A pointer to the buffer where the attestation key should be copied 2317 by this function. The buffer must be big enough to hold the 2318 attestation key. 2319 2320 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2321 function returns the attestation key length in this parameter. 2322 2323 arg2 - The type of the elliptic curve to which the requested attestation key 2324 belongs. 2325 2326The function returns 0 on success, -EINVAL on failure. 2327 2328Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1] 2329~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2330 2331:: 2332 2333 Argument : uintptr_t * 2334 Return : size_t 2335 2336This function returns the size of the shared area between EL3 and RMM (or 0 on 2337failure). A pointer to the shared area (or a NULL pointer on failure) is stored 2338in the pointer passed as argument. 2339 2340Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1] 2341~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2342 2343:: 2344 2345 Arguments : rmm_manifest_t *manifest 2346 Return : int 2347 2348When ENABLE_RME is enabled, this function populates a boot manifest for the 2349RMM image and stores it in the area specified by manifest. 2350 2351When ENABLE_RME is disabled, this function is not used. 2352 2353Function : plat_rmmd_el3_token_sign_push_req() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2354~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2355 2356:: 2357 2358 Arguments : const struct el3_token_sign_request *req 2359 Return : int 2360 2361Queue realm attestation token signing request from the RMM in EL3. The interface between 2362the RMM and EL3 is modeled as a queue but the underlying implementation may be different, 2363so long as the semantics of queuing and the error codes are used as defined below. 2364 2365See :ref:`el3_token_sign_request_struct` for definition of the request structure. 2366 2367Optional interface from the RMM-EL3 interface v0.4 onwards. 2368 2369The parameters of the functions are: 2370 arg0: Pointer to the token sign request to be pushed to EL3. 2371 The structure must be located in the RMM-EL3 shared 2372 memory buffer and must be locked before use. 2373 2374Return codes: 2375 - E_RMM_OK On Success. 2376 - E_RMM_INVAL If the arguments are invalid. 2377 - E_RMM_AGAIN Indicates that the request was not queued since the 2378 queue in EL3 is full. This may also be returned for any reason 2379 or situation in the system, that prevents accepting the request 2380 from the RMM. 2381 - E_RMM_UNK If the SMC is not implemented or if interface 2382 version is < 0.4. 2383 2384Function : plat_rmmd_el3_token_sign_pull_resp() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2385~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2386 2387:: 2388 2389 Arguments : struct el3_token_sign_response *resp 2390 Return : int 2391 2392Populate the attestation signing response in the ``resp`` parameter. The interface between 2393the RMM and EL3 is modeled as a queue for responses but the underlying implementation may 2394be different, so long as the semantics of queuing and the error codes are used as defined 2395below. 2396 2397See :ref:`el3_token_sign_response_struct` for definition of the response structure. 2398 2399Optional interface from the RMM-EL3 interface v0.4 onwards. 2400 2401The parameters of the functions are: 2402 resp: Pointer to the token sign response to get from EL3. 2403 The structure must be located in the RMM-EL3 shared 2404 memory buffer and must be locked before use. 2405 2406Return: 2407 - E_RMM_OK On Success. 2408 - E_RMM_INVAL If the arguments are invalid. 2409 - E_RMM_AGAIN Indicates that a response is not ready yet. 2410 - E_RMM_UNK If the SMC is not implemented or if interface 2411 version is < 0.4. 2412 2413Function : plat_rmmd_el3_token_sign_get_rak_pub() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2414~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2415 2416:: 2417 2418 Argument : uintptr_t, size_t *, unsigned int 2419 Return : int 2420 2421This function returns the public portion of the realm attestation key which will be used to 2422sign Realm attestation token. Typically, with delegated attestation, the private key is 2423returned, however, there may be platforms where the private key bits are better protected 2424in a platform specific manner such that the private key is not exposed. In such cases, 2425the RMM will only cache the public key and forward any requests such as signing, that 2426uses the private key to EL3. The API currently only supports P-384 ECC curve key. 2427 2428This is an optional interface from the RMM-EL3 interface v0.4 onwards. 2429 2430The parameters of the function are: 2431 2432 arg0 - A pointer to the buffer where the public key should be copied 2433 by this function. The buffer must be big enough to hold the 2434 attestation key. 2435 2436 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2437 function returns the attestation key length in this parameter. 2438 2439 arg2 - The type of the elliptic curve to which the requested attestation key 2440 belongs. 2441 2442The function returns E_RMM_OK on success, RMM_E_INVAL if arguments are invalid and 2443E_RMM_UNK if the SMC is not implemented or if interface version is < 0.4. 2444 2445Function : bl31_plat_enable_mmu [optional] 2446~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2447 2448:: 2449 2450 Argument : uint32_t 2451 Return : void 2452 2453This function enables the MMU. The boot code calls this function with MMU and 2454caches disabled. This function should program necessary registers to enable 2455translation, and upon return, the MMU on the calling PE must be enabled. 2456 2457The function must honor flags passed in the first argument. These flags are 2458defined by the translation library, and can be found in the file 2459``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2460 2461On DynamIQ systems, this function must not use stack while enabling MMU, which 2462is how the function in xlat table library version 2 is implemented. 2463 2464Function : plat_init_apkey [optional] 2465~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2466 2467:: 2468 2469 Argument : void 2470 Return : uint128_t 2471 2472This function returns the 128-bit value which can be used to program ARMv8.3 2473pointer authentication keys. 2474 2475The value should be obtained from a reliable source of randomness. 2476 2477This function is only needed if ARMv8.3 pointer authentication is used in the 2478Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to 1, 2 or 3. 2479 2480Function : plat_get_syscnt_freq2() [mandatory] 2481~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2482 2483:: 2484 2485 Argument : void 2486 Return : unsigned int 2487 2488This function is used by the architecture setup code to retrieve the counter 2489frequency for the CPU's generic timer. This value will be programmed into the 2490``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2491of the system counter, which is retrieved from the first entry in the frequency 2492modes table. 2493 2494#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 2495~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2496 2497When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2498bytes) aligned to the cache line boundary that should be allocated per-cpu to 2499accommodate all the bakery locks. 2500 2501If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2502calculates the size of the ``.bakery_lock`` input section, aligns it to the 2503nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2504and stores the result in a linker symbol. This constant prevents a platform 2505from relying on the linker and provide a more efficient mechanism for 2506accessing per-cpu bakery lock information. 2507 2508If this constant is defined and its value is not equal to the value 2509calculated by the linker then a link time assertion is raised. A compile time 2510assertion is raised if the value of the constant is not aligned to the cache 2511line boundary. 2512 2513.. _porting_guide_sdei_requirements: 2514 2515SDEI porting requirements 2516~~~~~~~~~~~~~~~~~~~~~~~~~ 2517 2518The |SDEI| dispatcher requires the platform to provide the following macros 2519and functions, of which some are optional, and some others mandatory. 2520 2521Macros 2522...... 2523 2524Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2525^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2526 2527This macro must be defined to the EL3 exception priority level associated with 2528Normal |SDEI| events on the platform. This must have a higher value 2529(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2530 2531Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2532^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2533 2534This macro must be defined to the EL3 exception priority level associated with 2535Critical |SDEI| events on the platform. This must have a lower value 2536(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2537 2538**Note**: |SDEI| exception priorities must be the lowest among Secure 2539priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must 2540be higher than Normal |SDEI| priority. 2541 2542Functions 2543......... 2544 2545Function: int plat_sdei_validate_entry_point() [optional] 2546^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2547 2548:: 2549 2550 Argument: uintptr_t ep, unsigned int client_mode 2551 Return: int 2552 2553This function validates the entry point address of the event handler provided by 2554the client for both event registration and *Complete and Resume* |SDEI| calls. 2555The function ensures that the address is valid in the client translation regime. 2556 2557The second argument is the exception level that the client is executing in. It 2558can be Non-Secure EL1 or Non-Secure EL2. 2559 2560The function must return ``0`` for successful validation, or ``-1`` upon failure. 2561 2562The default implementation always returns ``0``. On Arm platforms, this function 2563translates the entry point address within the client translation regime and 2564further ensures that the resulting physical address is located in Non-secure 2565DRAM. 2566 2567Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2568^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2569 2570:: 2571 2572 Argument: uint64_t 2573 Argument: unsigned int 2574 Return: void 2575 2576|SDEI| specification requires that a PE comes out of reset with the events 2577masked. The client therefore is expected to call ``PE_UNMASK`` to unmask 2578|SDEI| events on the PE. No |SDEI| events can be dispatched until such 2579time. 2580 2581Should a PE receive an interrupt that was bound to an |SDEI| event while the 2582events are masked on the PE, the dispatcher implementation invokes the function 2583``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2584interrupt and the interrupt ID are passed as parameters. 2585 2586The default implementation only prints out a warning message. 2587 2588.. _porting_guide_trng_requirements: 2589 2590TRNG porting requirements 2591~~~~~~~~~~~~~~~~~~~~~~~~~ 2592 2593The |TRNG| backend requires the platform to provide the following values 2594and mandatory functions. 2595 2596Values 2597...... 2598 2599value: uuid_t plat_trng_uuid [mandatory] 2600^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2601 2602This value must be defined to the UUID of the TRNG backend that is specific to 2603the hardware after ``plat_entropy_setup`` function is called. This value must 2604conform to the SMCCC calling convention; The most significant 32 bits of the 2605UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in 2606w0 indicates failure to get a TRNG source. 2607 2608Functions 2609......... 2610 2611Function: void plat_entropy_setup(void) [mandatory] 2612^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2613 2614:: 2615 2616 Argument: none 2617 Return: none 2618 2619This function is expected to do platform-specific initialization of any TRNG 2620hardware. This may include generating a UUID from a hardware-specific seed. 2621 2622Function: bool plat_get_entropy(uint64_t \*out) [mandatory] 2623^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2624 2625:: 2626 2627 Argument: uint64_t * 2628 Return: bool 2629 Out : when the return value is true, the entropy has been written into the 2630 storage pointed to 2631 2632This function writes entropy into storage provided by the caller. If no entropy 2633is available, it must return false and the storage must not be written. 2634 2635.. _psci_in_bl31: 2636 2637Power State Coordination Interface (in BL31) 2638-------------------------------------------- 2639 2640The TF-A implementation of the PSCI API is based around the concept of a 2641*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2642share some state on which power management operations can be performed as 2643specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2644a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2645*power domains* are arranged in a hierarchical tree structure and each 2646*power domain* can be identified in a system by the cpu index of any CPU that 2647is part of that domain and a *power domain level*. A processing element (for 2648example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2649logical grouping of CPUs that share some state, then level 1 is that group of 2650CPUs (for example, a cluster), and level 2 is a group of clusters (for 2651example, the system). More details on the power domain topology and its 2652organization can be found in :ref:`PSCI Power Domain Tree Structure`. 2653 2654BL31's platform initialization code exports a pointer to the platform-specific 2655power management operations required for the PSCI implementation to function 2656correctly. This information is populated in the ``plat_psci_ops`` structure. The 2657PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2658power management operations on the power domains. For example, the target 2659CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2660handler (if present) is called for the CPU power domain. 2661 2662The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2663describe composite power states specific to a platform. The PSCI implementation 2664defines a generic representation of the power-state parameter, which is an 2665array of local power states where each index corresponds to a power domain 2666level. Each entry contains the local power state the power domain at that power 2667level could enter. It depends on the ``validate_power_state()`` handler to 2668convert the power-state parameter (possibly encoding a composite power state) 2669passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2670 2671The following functions form part of platform port of PSCI functionality. 2672 2673Function : plat_psci_stat_accounting_start() [optional] 2674~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2675 2676:: 2677 2678 Argument : const psci_power_state_t * 2679 Return : void 2680 2681This is an optional hook that platforms can implement for residency statistics 2682accounting before entering a low power state. The ``pwr_domain_state`` field of 2683``state_info`` (first argument) can be inspected if stat accounting is done 2684differently at CPU level versus higher levels. As an example, if the element at 2685index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2686state, special hardware logic may be programmed in order to keep track of the 2687residency statistics. For higher levels (array indices > 0), the residency 2688statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2689default implementation will use PMF to capture timestamps. 2690 2691Function : plat_psci_stat_accounting_stop() [optional] 2692~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2693 2694:: 2695 2696 Argument : const psci_power_state_t * 2697 Return : void 2698 2699This is an optional hook that platforms can implement for residency statistics 2700accounting after exiting from a low power state. The ``pwr_domain_state`` field 2701of ``state_info`` (first argument) can be inspected if stat accounting is done 2702differently at CPU level versus higher levels. As an example, if the element at 2703index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2704state, special hardware logic may be programmed in order to keep track of the 2705residency statistics. For higher levels (array indices > 0), the residency 2706statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2707default implementation will use PMF to capture timestamps. 2708 2709Function : plat_psci_stat_get_residency() [optional] 2710~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2711 2712:: 2713 2714 Argument : unsigned int, const psci_power_state_t *, unsigned int 2715 Return : u_register_t 2716 2717This is an optional interface that is is invoked after resuming from a low power 2718state and provides the time spent resident in that low power state by the power 2719domain at a particular power domain level. When a CPU wakes up from suspend, 2720all its parent power domain levels are also woken up. The generic PSCI code 2721invokes this function for each parent power domain that is resumed and it 2722identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2723argument) describes the low power state that the power domain has resumed from. 2724The current CPU is the first CPU in the power domain to resume from the low 2725power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2726CPU in the power domain to suspend and may be needed to calculate the residency 2727for that power domain. 2728 2729Function : plat_get_target_pwr_state() [optional] 2730~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2731 2732:: 2733 2734 Argument : unsigned int, const plat_local_state_t *, unsigned int 2735 Return : plat_local_state_t 2736 2737The PSCI generic code uses this function to let the platform participate in 2738state coordination during a power management operation. The function is passed 2739a pointer to an array of platform specific local power state ``states`` (second 2740argument) which contains the requested power state for each CPU at a particular 2741power domain level ``lvl`` (first argument) within the power domain. The function 2742is expected to traverse this array of upto ``ncpus`` (third argument) and return 2743a coordinated target power state by the comparing all the requested power 2744states. The target power state should not be deeper than any of the requested 2745power states. 2746 2747A weak definition of this API is provided by default wherein it assumes 2748that the platform assigns a local state value in order of increasing depth 2749of the power state i.e. for two power states X & Y, if X < Y 2750then X represents a shallower power state than Y. As a result, the 2751coordinated target local power state for a power domain will be the minimum 2752of the requested local power state values. 2753 2754Function : plat_get_power_domain_tree_desc() [mandatory] 2755~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2756 2757:: 2758 2759 Argument : void 2760 Return : const unsigned char * 2761 2762This function returns a pointer to the byte array containing the power domain 2763topology tree description. The format and method to construct this array are 2764described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI 2765initialization code requires this array to be described by the platform, either 2766statically or dynamically, to initialize the power domain topology tree. In case 2767the array is populated dynamically, then plat_core_pos_by_mpidr() and 2768plat_my_core_pos() should also be implemented suitably so that the topology tree 2769description matches the CPU indices returned by these APIs. These APIs together 2770form the platform interface for the PSCI topology framework. 2771 2772Function : plat_setup_psci_ops() [mandatory] 2773~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2774 2775:: 2776 2777 Argument : uintptr_t, const plat_psci_ops ** 2778 Return : int 2779 2780This function may execute with the MMU and data caches enabled if the platform 2781port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2782called by the primary CPU. 2783 2784This function is called by PSCI initialization code. Its purpose is to let 2785the platform layer know about the warm boot entrypoint through the 2786``sec_entrypoint`` (first argument) and to export handler routines for 2787platform-specific psci power management actions by populating the passed 2788pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2789 2790A description of each member of this structure is given below. Please refer to 2791the Arm FVP specific implementation of these handlers in 2792``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the 2793platform wants to support, the associated operation or operations in this 2794structure must be provided and implemented (Refer section 4 of 2795:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI 2796function in a platform port, the operation should be removed from this 2797structure instead of providing an empty implementation. 2798 2799plat_psci_ops.cpu_standby() 2800........................... 2801 2802Perform the platform-specific actions to enter the standby state for a cpu 2803indicated by the passed argument. This provides a fast path for CPU standby 2804wherein overheads of PSCI state management and lock acquisition is avoided. 2805For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2806the suspend state type specified in the ``power-state`` parameter should be 2807STANDBY and the target power domain level specified should be the CPU. The 2808handler should put the CPU into a low power retention state (usually by 2809issuing a wfi instruction) and ensure that it can be woken up from that 2810state by a normal interrupt. The generic code expects the handler to succeed. 2811 2812plat_psci_ops.pwr_domain_on() 2813............................. 2814 2815Perform the platform specific actions to power on a CPU, specified 2816by the ``MPIDR`` (first argument). The generic code expects the platform to 2817return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 2818 2819plat_psci_ops.pwr_domain_off_early() [optional] 2820............................................... 2821 2822This optional function performs the platform specific actions to check if 2823powering off the calling CPU and its higher parent power domain levels as 2824indicated by the ``target_state`` (first argument) is possible or allowed. 2825 2826The ``target_state`` encodes the platform coordinated target local power states 2827for the CPU power domain and its parent power domain levels. 2828 2829For this handler, the local power state for the CPU power domain will be a 2830power down state where as it could be either power down, retention or run state 2831for the higher power domain levels depending on the result of state 2832coordination. The generic code expects PSCI_E_DENIED return code if the 2833platform thinks that CPU_OFF should not proceed on the calling CPU. 2834 2835plat_psci_ops.pwr_domain_off() 2836.............................. 2837 2838Perform the platform specific actions to prepare to power off the calling CPU 2839and its higher parent power domain levels as indicated by the ``target_state`` 2840(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2841 2842The ``target_state`` encodes the platform coordinated target local power states 2843for the CPU power domain and its parent power domain levels. The handler 2844needs to perform power management operation corresponding to the local state 2845at each power level. 2846 2847For this handler, the local power state for the CPU power domain will be a 2848power down state where as it could be either power down, retention or run state 2849for the higher power domain levels depending on the result of state 2850coordination. The generic code expects the handler to succeed. 2851 2852plat_psci_ops.pwr_domain_validate_suspend() [optional] 2853...................................................... 2854 2855This is an optional function that is only compiled into the build if the build 2856option ``PSCI_OS_INIT_MODE`` is enabled. 2857 2858If implemented, this function allows the platform to perform platform specific 2859validations based on hardware states. The generic code expects this function to 2860return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or 2861PSCI_E_INVALID_PARAMS as appropriate for any invalid requests. 2862 2863plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 2864........................................................... 2865 2866This optional function may be used as a performance optimization to replace 2867or complement pwr_domain_suspend() on some platforms. Its calling semantics 2868are identical to pwr_domain_suspend(), except the PSCI implementation only 2869calls this function when suspending to a power down state, and it guarantees 2870that data caches are enabled. 2871 2872When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2873before calling pwr_domain_suspend(). If the target_state corresponds to a 2874power down state and it is safe to perform some or all of the platform 2875specific actions in that function with data caches enabled, it may be more 2876efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2877= 1, data caches remain enabled throughout, and so there is no advantage to 2878moving platform specific actions to this function. 2879 2880plat_psci_ops.pwr_domain_suspend() 2881.................................. 2882 2883Perform the platform specific actions to prepare to suspend the calling 2884CPU and its higher parent power domain levels as indicated by the 2885``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2886API implementation. 2887 2888The ``target_state`` has a similar meaning as described in 2889the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2890target local power states for the CPU power domain and its parent 2891power domain levels. The handler needs to perform power management operation 2892corresponding to the local state at each power level. The generic code 2893expects the handler to succeed. 2894 2895The difference between turning a power domain off versus suspending it is that 2896in the former case, the power domain is expected to re-initialize its state 2897when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2898case, the power domain is expected to save enough state so that it can resume 2899execution by restoring this state when its powered on (see 2900``pwr_domain_suspend_finish()``). 2901 2902When suspending a core, the platform can also choose to power off the GICv3 2903Redistributor and ITS through an implementation-defined sequence. To achieve 2904this safely, the ITS context must be saved first. The architectural part is 2905implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2906sequence is implementation defined and it is therefore the responsibility of 2907the platform code to implement the necessary sequence. Then the GIC 2908Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2909Powering off the Redistributor requires the implementation to support it and it 2910is the responsibility of the platform code to execute the right implementation 2911defined sequence. 2912 2913When a system suspend is requested, the platform can also make use of the 2914``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2915it has saved the context of the Redistributors and ITS of all the cores in the 2916system. The context of the Distributor can be large and may require it to be 2917allocated in a special area if it cannot fit in the platform's global static 2918data, for example in DRAM. The Distributor can then be powered down using an 2919implementation-defined sequence. 2920 2921plat_psci_ops.pwr_domain_pwr_down() 2922....................................... 2923 2924This is an optional function and, if implemented, is expected to perform 2925platform specific actions before the CPU is powered down. Since this function is 2926invoked outside the PSCI locks, the actions performed in this hook must be local 2927to the CPU or the platform must ensure that races between multiple CPUs cannot 2928occur. 2929 2930The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2931operation and it encodes the platform coordinated target local power states for 2932the CPU power domain and its parent power domain levels. 2933 2934It is preferred that this function returns. The caller will invoke 2935``psci_power_down_wfi()`` to powerdown the CPU, mitigate any powerdown errata, 2936and handle any wakeups that may arise. Previously, this function did not return 2937and instead called ``wfi`` (in an infinite loop) directly. This is still 2938possible on platforms where this is guaranteed to be terminal, however, it is 2939strongly discouraged going forward. 2940 2941plat_psci_ops.pwr_domain_on_finish() 2942.................................... 2943 2944This function is called by the PSCI implementation after the calling CPU is 2945powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2946It performs the platform-specific setup required to initialize enough state for 2947this CPU to enter the normal world and also provide secure runtime firmware 2948services. 2949 2950The ``target_state`` (first argument) is the prior state of the power domains 2951immediately before the CPU was turned on. It indicates which power domains 2952above the CPU might require initialization due to having previously been in 2953low power states. The generic code expects the handler to succeed. 2954 2955plat_psci_ops.pwr_domain_on_finish_late() [optional] 2956........................................................... 2957 2958This optional function is called by the PSCI implementation after the calling 2959CPU is fully powered on with respective data caches enabled. The calling CPU and 2960the associated cluster are guaranteed to be participating in coherency. This 2961function gives the flexibility to perform any platform-specific actions safely, 2962such as initialization or modification of shared data structures, without the 2963overhead of explicit cache maintainace operations. 2964 2965The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` 2966operation. The generic code expects the handler to succeed. 2967 2968plat_psci_ops.pwr_domain_suspend_finish() 2969......................................... 2970 2971This function is called by the PSCI implementation after the calling CPU is 2972powered on and released from reset in response to an asynchronous wakeup 2973event, for example a timer interrupt that was programmed by the CPU during the 2974``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2975setup required to restore the saved state for this CPU to resume execution 2976in the normal world and also provide secure runtime firmware services. 2977 2978The ``target_state`` (first argument) has a similar meaning as described in 2979the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2980to succeed. 2981 2982If the Distributor, Redistributors or ITS have been powered off as part of a 2983suspend, their context must be restored in this function in the reverse order 2984to how they were saved during suspend sequence. 2985 2986plat_psci_ops.system_off() 2987.......................... 2988 2989This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2990call. It performs the platform-specific system poweroff sequence after 2991notifying the Secure Payload Dispatcher. The caller will call ``wfi`` if this 2992function returns, similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 2993 2994plat_psci_ops.system_reset() 2995............................ 2996 2997This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2998call. It performs the platform-specific system reset sequence after 2999notifying the Secure Payload Dispatcher. The caller will call ``wfi`` if this 3000function returns, similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 3001 3002plat_psci_ops.validate_power_state() 3003.................................... 3004 3005This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 3006call to validate the ``power_state`` parameter of the PSCI API and if valid, 3007populate it in ``req_state`` (second argument) array as power domain level 3008specific local states. If the ``power_state`` is invalid, the platform must 3009return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 3010normal world PSCI client. 3011 3012plat_psci_ops.validate_ns_entrypoint() 3013...................................... 3014 3015This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 3016``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 3017parameter passed by the normal world. If the ``entry_point`` is invalid, 3018the platform must return PSCI_E_INVALID_ADDRESS as error, which is 3019propagated back to the normal world PSCI client. 3020 3021plat_psci_ops.get_sys_suspend_power_state() 3022........................................... 3023 3024This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 3025call to get the ``req_state`` parameter from platform which encodes the power 3026domain level specific local states to suspend to system affinity level. The 3027``req_state`` will be utilized to do the PSCI state coordination and 3028``pwr_domain_suspend()`` will be invoked with the coordinated target state to 3029enter system suspend. 3030 3031plat_psci_ops.get_pwr_lvl_state_idx() 3032..................................... 3033 3034This is an optional function and, if implemented, is invoked by the PSCI 3035implementation to convert the ``local_state`` (first argument) at a specified 3036``pwr_lvl`` (second argument) to an index between 0 and 3037``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 3038supports more than two local power states at each power domain level, that is 3039``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 3040local power states. 3041 3042plat_psci_ops.translate_power_state_by_mpidr() 3043.............................................. 3044 3045This is an optional function and, if implemented, verifies the ``power_state`` 3046(second argument) parameter of the PSCI API corresponding to a target power 3047domain. The target power domain is identified by using both ``MPIDR`` (first 3048argument) and the power domain level encoded in ``power_state``. The power domain 3049level specific local states are to be extracted from ``power_state`` and be 3050populated in the ``output_state`` (third argument) array. The functionality 3051is similar to the ``validate_power_state`` function described above and is 3052envisaged to be used in case the validity of ``power_state`` depend on the 3053targeted power domain. If the ``power_state`` is invalid for the targeted power 3054domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 3055function is not implemented, then the generic implementation relies on 3056``validate_power_state`` function to translate the ``power_state``. 3057 3058This function can also be used in case the platform wants to support local 3059power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 3060APIs as described in Section 5.18 of `PSCI`_. 3061 3062plat_psci_ops.get_node_hw_state() 3063................................. 3064 3065This is an optional function. If implemented this function is intended to return 3066the power state of a node (identified by the first parameter, the ``MPIDR``) in 3067the power domain topology (identified by the second parameter, ``power_level``), 3068as retrieved from a power controller or equivalent component on the platform. 3069Upon successful completion, the implementation must map and return the final 3070status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 3071must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 3072appropriate. 3073 3074Implementations are not expected to handle ``power_levels`` greater than 3075``PLAT_MAX_PWR_LVL``. 3076 3077plat_psci_ops.system_reset2() 3078............................. 3079 3080This is an optional function. If implemented this function is 3081called during the ``SYSTEM_RESET2`` call to perform a reset 3082based on the first parameter ``reset_type`` as specified in 3083`PSCI`_. The parameter ``cookie`` can be used to pass additional 3084reset information. If the ``reset_type`` is not supported, the 3085function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 3086resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 3087and vendor reset can return other PSCI error codes as defined 3088in `PSCI`_. If this function returns success, the caller will call 3089``wfi`` similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 3090 3091plat_psci_ops.write_mem_protect() 3092................................. 3093 3094This is an optional function. If implemented it enables or disables the 3095``MEM_PROTECT`` functionality based on the value of ``val``. 3096A non-zero value enables ``MEM_PROTECT`` and a value of zero 3097disables it. Upon encountering failures it must return a negative value 3098and on success it must return 0. 3099 3100plat_psci_ops.read_mem_protect() 3101................................ 3102 3103This is an optional function. If implemented it returns the current 3104state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 3105failures it must return a negative value and on success it must 3106return 0. 3107 3108plat_psci_ops.mem_protect_chk() 3109............................... 3110 3111This is an optional function. If implemented it checks if a memory 3112region defined by a base address ``base`` and with a size of ``length`` 3113bytes is protected by ``MEM_PROTECT``. If the region is protected 3114then it must return 0, otherwise it must return a negative number. 3115 3116.. _porting_guide_imf_in_bl31: 3117 3118Interrupt Management framework (in BL31) 3119---------------------------------------- 3120 3121BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 3122generated in either security state and targeted to EL1 or EL2 in the non-secure 3123state or EL3/S-EL1 in the secure state. The design of this framework is 3124described in the :ref:`Interrupt Management Framework` 3125 3126A platform should export the following APIs to support the IMF. The following 3127text briefly describes each API and its implementation in Arm standard 3128platforms. The API implementation depends upon the type of interrupt controller 3129present in the platform. Arm standard platform layer supports both 3130`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 3131and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 3132FVP can be configured to use either GICv2 or GICv3 depending on the build flag 3133``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more 3134details). 3135 3136See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. 3137 3138Function : plat_interrupt_type_to_line() [mandatory] 3139~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3140 3141:: 3142 3143 Argument : uint32_t, uint32_t 3144 Return : uint32_t 3145 3146The Arm processor signals an interrupt exception either through the IRQ or FIQ 3147interrupt line. The specific line that is signaled depends on how the interrupt 3148controller (IC) reports different interrupt types from an execution context in 3149either security state. The IMF uses this API to determine which interrupt line 3150the platform IC uses to signal each type of interrupt supported by the framework 3151from a given security state. This API must be invoked at EL3. 3152 3153The first parameter will be one of the ``INTR_TYPE_*`` values (see 3154:ref:`Interrupt Management Framework`) indicating the target type of the 3155interrupt, the second parameter is the security state of the originating 3156execution context. The return result is the bit position in the ``SCR_EL3`` 3157register of the respective interrupt trap: IRQ=1, FIQ=2. 3158 3159In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 3160configured as FIQs and Non-secure interrupts as IRQs from either security 3161state. 3162 3163In the case of Arm standard platforms using GICv3, the interrupt line to be 3164configured depends on the security state of the execution context when the 3165interrupt is signalled and are as follows: 3166 3167- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 3168 NS-EL0/1/2 context. 3169- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 3170 in the NS-EL0/1/2 context. 3171- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 3172 context. 3173 3174Function : plat_ic_get_pending_interrupt_type() [mandatory] 3175~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3176 3177:: 3178 3179 Argument : void 3180 Return : uint32_t 3181 3182This API returns the type of the highest priority pending interrupt at the 3183platform IC. The IMF uses the interrupt type to retrieve the corresponding 3184handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 3185pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 3186``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 3187 3188In the case of Arm standard platforms using GICv2, the *Highest Priority 3189Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 3190the pending interrupt. The type of interrupt depends upon the id value as 3191follows. 3192 3193#. id < 1022 is reported as a S-EL1 interrupt 3194#. id = 1022 is reported as a Non-secure interrupt. 3195#. id = 1023 is reported as an invalid interrupt type. 3196 3197In the case of Arm standard platforms using GICv3, the system register 3198``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 3199is read to determine the id of the pending interrupt. The type of interrupt 3200depends upon the id value as follows. 3201 3202#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 3203#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 3204#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 3205#. All other interrupt id's are reported as EL3 interrupt. 3206 3207Function : plat_ic_get_pending_interrupt_id() [mandatory] 3208~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3209 3210:: 3211 3212 Argument : void 3213 Return : uint32_t 3214 3215This API returns the id of the highest priority pending interrupt at the 3216platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 3217pending. 3218 3219In the case of Arm standard platforms using GICv2, the *Highest Priority 3220Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 3221pending interrupt. The id that is returned by API depends upon the value of 3222the id read from the interrupt controller as follows. 3223 3224#. id < 1022. id is returned as is. 3225#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 3226 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 3227 This id is returned by the API. 3228#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 3229 3230In the case of Arm standard platforms using GICv3, if the API is invoked from 3231EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 3232group 0 Register*, is read to determine the id of the pending interrupt. The id 3233that is returned by API depends upon the value of the id read from the 3234interrupt controller as follows. 3235 3236#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 3237#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 3238 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 3239 Register* is read to determine the id of the group 1 interrupt. This id 3240 is returned by the API as long as it is a valid interrupt id 3241#. If the id is any of the special interrupt identifiers, 3242 ``INTR_ID_UNAVAILABLE`` is returned. 3243 3244When the API invoked from S-EL1 for GICv3 systems, the id read from system 3245register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 3246Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 3247``INTR_ID_UNAVAILABLE`` is returned. 3248 3249Function : plat_ic_acknowledge_interrupt() [mandatory] 3250~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3251 3252:: 3253 3254 Argument : void 3255 Return : uint32_t 3256 3257This API is used by the CPU to indicate to the platform IC that processing of 3258the highest pending interrupt has begun. It should return the raw, unmodified 3259value obtained from the interrupt controller when acknowledging an interrupt. 3260The actual interrupt number shall be extracted from this raw value using the API 3261`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. 3262 3263This function in Arm standard platforms using GICv2, reads the *Interrupt 3264Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 3265priority pending interrupt from pending to active in the interrupt controller. 3266It returns the value read from the ``GICC_IAR``, unmodified. 3267 3268In the case of Arm standard platforms using GICv3, if the API is invoked 3269from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 3270Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 3271reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 3272group 1*. The read changes the state of the highest pending interrupt from 3273pending to active in the interrupt controller. The value read is returned 3274unmodified. 3275 3276The TSP uses this API to start processing of the secure physical timer 3277interrupt. 3278 3279Function : plat_ic_end_of_interrupt() [mandatory] 3280~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3281 3282:: 3283 3284 Argument : uint32_t 3285 Return : void 3286 3287This API is used by the CPU to indicate to the platform IC that processing of 3288the interrupt corresponding to the id (passed as the parameter) has 3289finished. The id should be the same as the id returned by the 3290``plat_ic_acknowledge_interrupt()`` API. 3291 3292Arm standard platforms write the id to the *End of Interrupt Register* 3293(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 3294system register in case of GICv3 depending on where the API is invoked from, 3295EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 3296controller. 3297 3298The TSP uses this API to finish processing of the secure physical timer 3299interrupt. 3300 3301Function : plat_ic_get_interrupt_type() [mandatory] 3302~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3303 3304:: 3305 3306 Argument : uint32_t 3307 Return : uint32_t 3308 3309This API returns the type of the interrupt id passed as the parameter. 3310``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 3311interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 3312returned depending upon how the interrupt has been configured by the platform 3313IC. This API must be invoked at EL3. 3314 3315Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 3316and Non-secure interrupts as Group1 interrupts. It reads the group value 3317corresponding to the interrupt id from the relevant *Interrupt Group Register* 3318(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 3319 3320In the case of Arm standard platforms using GICv3, both the *Interrupt Group 3321Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 3322(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 3323as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 3324 3325Registering a console 3326--------------------- 3327 3328Platforms will need to implement the TF-A console framework to register and use 3329a console for visual data output in TF-A. These can be used for data output during 3330the different stages of the firmware boot process and also for debugging purposes. 3331 3332The console framework can be used to output data on to a console using a number of 3333TF-A supported UARTs. Multiple consoles can be registered at the same time with 3334different output scopes (BOOT, RUNTIME, CRASH) so that data can be displayed on 3335their respective consoles without unnecessary cluttering of a single console. 3336 3337Information for registering a console can be found in the :ref:`Console Framework` section 3338of the :ref:`System Design` documentation. 3339 3340Common helper functions 3341----------------------- 3342Function : elx_panic() 3343~~~~~~~~~~~~~~~~~~~~~~ 3344 3345:: 3346 3347 Argument : void 3348 Return : void 3349 3350This API is called from assembly files when reporting a critical failure 3351that has occured in lower EL and is been trapped in EL3. This call 3352**must not** return. 3353 3354Function : el3_panic() 3355~~~~~~~~~~~~~~~~~~~~~~ 3356 3357:: 3358 3359 Argument : void 3360 Return : void 3361 3362This API is called from assembly files when encountering a critical failure that 3363cannot be recovered from. This function assumes that it is invoked from a C 3364runtime environment i.e. valid stack exists. This call **must not** return. 3365 3366Function : panic() 3367~~~~~~~~~~~~~~~~~~ 3368 3369:: 3370 3371 Argument : void 3372 Return : void 3373 3374This API called from C files when encountering a critical failure that cannot 3375be recovered from. This function in turn prints backtrace (if enabled) and calls 3376el3_panic(). This call **must not** return. 3377 3378Crash Reporting mechanism (in BL31) 3379----------------------------------- 3380 3381BL31 implements a crash reporting mechanism which prints the various registers 3382of the CPU to enable quick crash analysis and debugging. This mechanism relies 3383on the platform implementing ``plat_crash_console_init``, 3384``plat_crash_console_putc`` and ``plat_crash_console_flush``. 3385 3386The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 3387implementation of all of them. Platforms may include this file to their 3388makefiles in order to benefit from them. By default, they will cause the crash 3389output to be routed over the normal console infrastructure and get printed on 3390consoles configured to output in crash state. ``console_set_scope()`` can be 3391used to control whether a console is used for crash output. 3392 3393.. note:: 3394 Platforms are responsible for making sure that they only mark consoles for 3395 use in the crash scope that are able to support this, i.e. that are written 3396 in assembly and conform with the register clobber rules for putc() 3397 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. 3398 3399In some cases (such as debugging very early crashes that happen before the 3400normal boot console can be set up), platforms may want to control crash output 3401more explicitly. These platforms may instead provide custom implementations for 3402these. They are executed outside of a C environment and without a stack. Many 3403console drivers provide functions named ``console_xxx_core_init/putc/flush`` 3404that are designed to be used by these functions. See Arm platforms (like juno) 3405for an example of this. 3406 3407Function : plat_crash_console_init [mandatory] 3408~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3409 3410:: 3411 3412 Argument : void 3413 Return : int 3414 3415This API is used by the crash reporting mechanism to initialize the crash 3416console. It must only use the general purpose registers x0 through x7 to do the 3417initialization and returns 1 on success. 3418 3419Function : plat_crash_console_putc [mandatory] 3420~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3421 3422:: 3423 3424 Argument : int 3425 Return : int 3426 3427This API is used by the crash reporting mechanism to print a character on the 3428designated crash console. It must only use general purpose registers x1 and 3429x2 to do its work. The parameter and the return value are in general purpose 3430register x0. 3431 3432Function : plat_crash_console_flush [mandatory] 3433~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3434 3435:: 3436 3437 Argument : void 3438 Return : void 3439 3440This API is used by the crash reporting mechanism to force write of all buffered 3441data on the designated crash console. It should only use general purpose 3442registers x0 through x5 to do its work. 3443 3444Function : plat_setup_early_console [optional] 3445~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3446 3447:: 3448 3449 Argument : void 3450 Return : void 3451 3452This API is used to setup the early console, it is required only if the flag 3453``EARLY_CONSOLE`` is enabled. 3454 3455.. _External Abort handling and RAS Support: 3456 3457External Abort handling and RAS Support 3458--------------------------------------- 3459 3460Function : plat_ea_handler 3461~~~~~~~~~~~~~~~~~~~~~~~~~~ 3462 3463:: 3464 3465 Argument : int 3466 Argument : uint64_t 3467 Argument : void * 3468 Argument : void * 3469 Argument : uint64_t 3470 Return : void 3471 3472This function is invoked by the runtime exception handling framework for the 3473platform to handle an External Abort received at EL3. The intention of the 3474function is to attempt to resolve the cause of External Abort and return; 3475if that's not possible then an orderly shutdown of the system is initiated. 3476 3477The first parameter (``int ea_reason``) indicates the reason for External Abort. 3478Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 3479 3480The second parameter (``uint64_t syndrome``) is the respective syndrome 3481presented to EL3 after having received the External Abort. Depending on the 3482nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 3483can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 3484 3485The third parameter (``void *cookie``) is unused for now. The fourth parameter 3486(``void *handle``) is a pointer to the preempted context. The fifth parameter 3487(``uint64_t flags``) indicates the preempted security state. These parameters 3488are received from the top-level exception handler. 3489 3490This function must be implemented if a platform expects Firmware First handling 3491of External Aborts. 3492 3493Function : plat_handle_uncontainable_ea 3494~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3495 3496:: 3497 3498 Argument : int 3499 Argument : uint64_t 3500 Return : void 3501 3502This function is invoked by the RAS framework when an External Abort of 3503Uncontainable type is received at EL3. Due to the critical nature of 3504Uncontainable errors, the intention of this function is to initiate orderly 3505shutdown of the system, and is not expected to return. 3506 3507This function must be implemented in assembly. 3508 3509The first and second parameters are the same as that of ``plat_ea_handler``. 3510 3511The default implementation of this function calls 3512``report_unhandled_exception``. 3513 3514Function : plat_handle_double_fault 3515~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3516 3517:: 3518 3519 Argument : int 3520 Argument : uint64_t 3521 Return : void 3522 3523This function is invoked by the RAS framework when another External Abort is 3524received at EL3 while one is already being handled. I.e., a call to 3525``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 3526this function is to initiate orderly shutdown of the system, and is not expected 3527recover or return. 3528 3529This function must be implemented in assembly. 3530 3531The first and second parameters are the same as that of ``plat_ea_handler``. 3532 3533The default implementation of this function calls 3534``report_unhandled_exception``. 3535 3536Function : plat_handle_el3_ea 3537~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3538 3539:: 3540 3541 Return : void 3542 3543This function is invoked when an External Abort is received while executing in 3544EL3. Due to its critical nature, the intention of this function is to initiate 3545orderly shutdown of the system, and is not expected recover or return. 3546 3547This function must be implemented in assembly. 3548 3549The default implementation of this function calls 3550``report_unhandled_exception``. 3551 3552Function : plat_handle_rng_trap 3553~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3554 3555:: 3556 3557 Argument : uint64_t 3558 Argument : cpu_context_t * 3559 Return : int 3560 3561This function is invoked by BL31's exception handler when there is a synchronous 3562system register trap caused by access to the RNDR or RNDRRS registers. It allows 3563platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to 3564emulate those system registers by returing back some entropy to the lower EL. 3565 3566The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3567syndrome register, which encodes the instruction that was trapped. The interesting 3568information in there is the target register (``get_sysreg_iss_rt()``). 3569 3570The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3571lower exception level, at the time when the execution of the ``mrs`` instruction 3572was trapped. Its content can be changed, to put the entropy into the target 3573register. 3574 3575The return value indicates how to proceed: 3576 3577- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3578- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3579 to the same instruction, so its execution will be repeated. 3580- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3581 to the next instruction. 3582 3583This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP. 3584 3585Function : plat_handle_impdef_trap 3586~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3587 3588:: 3589 3590 Argument : uint64_t 3591 Argument : cpu_context_t * 3592 Return : int 3593 3594This function is invoked by BL31's exception handler when there is a synchronous 3595system register trap caused by access to the implementation defined registers. 3596It allows platforms enabling ``IMPDEF_SYSREG_TRAP`` to emulate those system 3597registers choosing to program bits of their choice. If using in combination with 3598``ARCH_FEATURE_AVAILABILITY``, the macros 3599{SCR,MDCR,CPTR}_PLAT_{BITS,IGNORED,FLIPPED} should be defined to report correct 3600results. 3601 3602The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3603syndrome register, which encodes the instruction that was trapped. 3604 3605The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3606lower exception level, at the time when the execution of the ``mrs`` instruction 3607was trapped. 3608 3609The return value indicates how to proceed: 3610 3611- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3612- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3613 to the same instruction, so its execution will be repeated. 3614- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3615 to the next instruction. 3616 3617This function needs to be implemented by a platform if it enables 3618IMPDEF_SYSREG_TRAP. 3619 3620Build flags 3621----------- 3622 3623There are some build flags which can be defined by the platform to control 3624inclusion or exclusion of certain BL stages from the FIP image. These flags 3625need to be defined in the platform makefile which will get included by the 3626build system. 3627 3628- **NEED_BL33** 3629 By default, this flag is defined ``yes`` by the build system and ``BL33`` 3630 build option should be supplied as a build option. The platform has the 3631 option of excluding the BL33 image in the ``fip`` image by defining this flag 3632 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 3633 are used, this flag will be set to ``no`` automatically. 3634 3635- **ARM_ARCH_MAJOR and ARM_ARCH_MINOR** 3636 By default, ARM_ARCH_MAJOR.ARM_ARCH_MINOR is set to 8.0 in ``defaults.mk``, 3637 if the platform makefile/build defines or uses the correct ARM_ARCH_MAJOR and 3638 ARM_ARCH_MINOR then mandatory Architectural features available for that Arch 3639 version will be enabled by default and any optional Arch feature supported by 3640 the Architecture and available in TF-A can be enabled from platform specific 3641 makefile. Look up to ``arch_features.mk`` for details pertaining to mandatory 3642 and optional Arch specific features. 3643 3644Platform include paths 3645---------------------- 3646 3647Platforms are allowed to add more include paths to be passed to the compiler. 3648The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in 3649particular for the file ``platform_def.h``. 3650 3651Example: 3652 3653.. code:: c 3654 3655 PLAT_INCLUDES += -Iinclude/plat/myplat/include 3656 3657C Library 3658--------- 3659 3660To avoid subtle toolchain behavioral dependencies, the header files provided 3661by the compiler are not used. The software is built with the ``-nostdinc`` flag 3662to ensure no headers are included from the toolchain inadvertently. Instead the 3663required headers are included in the TF-A source tree. The library only 3664contains those C library definitions required by the local implementation. If 3665more functionality is required, the needed library functions will need to be 3666added to the local implementation. 3667 3668Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3669been written specifically for TF-A. Some implementation files have been obtained 3670from `FreeBSD`_, others have been written specifically for TF-A as well. The 3671files can be found in ``include/lib/libc`` and ``lib/libc``. 3672 3673SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 3674can be obtained from http://github.com/freebsd/freebsd. 3675 3676Storage abstraction layer 3677------------------------- 3678 3679In order to improve platform independence and portability a storage abstraction 3680layer is used to load data from non-volatile platform storage. Currently 3681storage access is only required by BL1 and BL2 phases and performed inside the 3682``load_image()`` function in ``bl_common.c``. 3683 3684.. uml:: resources/diagrams/plantuml/io_framework_usage_overview.puml 3685 3686It is mandatory to implement at least one storage driver. For the Arm 3687development platforms the Firmware Image Package (FIP) driver is provided as 3688the default means to load data from storage (see :ref:`firmware_design_fip`). 3689The storage layer is described in the header file 3690``include/drivers/io/io_storage.h``. The implementation of the common library is 3691in ``drivers/io/io_storage.c`` and the driver files are located in 3692``drivers/io/``. 3693 3694.. uml:: resources/diagrams/plantuml/io_arm_class_diagram.puml 3695 3696Each IO driver must provide ``io_dev_*`` structures, as described in 3697``drivers/io/io_driver.h``. These are returned via a mandatory registration 3698function that is called on platform initialization. The semi-hosting driver 3699implementation in ``io_semihosting.c`` can be used as an example. 3700 3701Each platform should register devices and their drivers via the storage 3702abstraction layer. These drivers then need to be initialized by bootloader 3703phases as required in their respective ``blx_platform_setup()`` functions. 3704 3705.. uml:: resources/diagrams/plantuml/io_dev_registration.puml 3706 3707The storage abstraction layer provides mechanisms (``io_dev_init()``) to 3708initialize storage devices before IO operations are called. 3709 3710.. uml:: resources/diagrams/plantuml/io_dev_init_and_check.puml 3711 3712The basic operations supported by the layer 3713include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3714Drivers do not have to implement all operations, but each platform must 3715provide at least one driver for a device capable of supporting generic 3716operations such as loading a bootloader image. 3717 3718The current implementation only allows for known images to be loaded by the 3719firmware. These images are specified by using their identifiers, as defined in 3720``include/plat/common/common_def.h`` (or a separate header file included from 3721there). The platform layer (``plat_get_image_source()``) then returns a reference 3722to a device and a driver-specific ``spec`` which will be understood by the driver 3723to allow access to the image data. 3724 3725The layer is designed in such a way that is it possible to chain drivers with 3726other drivers. For example, file-system drivers may be implemented on top of 3727physical block devices, both represented by IO devices with corresponding 3728drivers. In such a case, the file-system "binding" with the block device may 3729be deferred until the file-system device is initialised. 3730 3731The abstraction currently depends on structures being statically allocated 3732by the drivers and callers, as the system does not yet provide a means of 3733dynamically allocating memory. This may also have the affect of limiting the 3734amount of open resources per driver. 3735 3736Measured Boot Platform Interface 3737-------------------------------- 3738 3739Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer 3740to :ref:`Measured Boot Design` for more details. 3741 3742-------------- 3743 3744*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.* 3745 3746.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 3747.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 3748.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 3749.. _FreeBSD: https://www.freebsd.org 3750.. _SCC: http://www.simple-cc.org/ 3751.. _DRTM: https://developer.arm.com/documentation/den0113/a 3752