1Porting Guide 2============= 3 4Introduction 5------------ 6 7Porting Trusted Firmware-A (TF-A) to a new platform involves making some 8mandatory and optional modifications for both the cold and warm boot paths. 9Modifications consist of: 10 11- Implementing a platform-specific function or variable, 12- Setting up the execution context in a certain way, or 13- Defining certain constants (for example #defines). 14 15The platform-specific functions and variables are declared in 16``include/plat/common/platform.h``. The firmware provides a default 17implementation of variables and functions to fulfill the optional requirements 18in order to ease the porting effort. Each platform port can use them as is or 19provide their own implementation if the default implementation is inadequate. 20 21 .. note:: 22 23 TF-A historically provided default implementations of platform interfaces 24 as *weak* functions. This practice is now discouraged and new platform 25 interfaces as they get introduced in the code base should be *strongly* 26 defined. We intend to convert existing weak functions over time. Until 27 then, you will find references to *weak* functions in this document. 28 29Please review the :ref:`Threat Model` documents as part of the porting 30effort. Some platform interfaces play a key role in mitigating against some of 31the threats. Failing to fulfill these expectations could undermine the security 32guarantees offered by TF-A. These platform responsibilities are highlighted in 33the threat assessment section, under the "`Mitigations implemented?`" box for 34each threat. 35 36Some modifications are common to all Boot Loader (BL) stages. Section 2 37discusses these in detail. The subsequent sections discuss the remaining 38modifications for each BL stage in detail. 39 40Please refer to the :ref:`Platform Ports Policy` for the policy regarding 41compatibility and deprecation of these porting interfaces. 42 43Only Arm development platforms (such as FVP and Juno) may use the 44functions/definitions in ``include/plat/arm/common/`` and the corresponding 45source files in ``plat/arm/common/``. This is done so that there are no 46dependencies between platforms maintained by different people/companies. If you 47want to use any of the functionality present in ``plat/arm`` files, please 48propose a patch that moves the code to ``plat/common`` so that it can be 49discussed. 50 51Common modifications 52-------------------- 53 54This section covers the modifications that should be made by the platform for 55each BL stage to correctly port the firmware stack. They are categorized as 56either mandatory or optional. 57 58Common mandatory modifications 59------------------------------ 60 61A platform port must enable the Memory Management Unit (MMU) as well as the 62instruction and data caches for each BL stage. Setting up the translation 63tables is the responsibility of the platform port because memory maps differ 64across platforms. A memory translation library (see ``lib/xlat_tables_v2/``) is 65provided to help in this setup. 66 67Note that although this library supports non-identity mappings, this is intended 68only for re-mapping peripheral physical addresses and allows platforms with high 69I/O addresses to reduce their virtual address space. All other addresses 70corresponding to code and data must currently use an identity mapping. 71 72Also, the only translation granule size supported in TF-A is 4KB, as various 73parts of the code assume that is the case. It is not possible to switch to 7416 KB or 64 KB granule sizes at the moment. 75 76In Arm standard platforms, each BL stage configures the MMU in the 77platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 78an identity mapping for all addresses. 79 80If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 81block of identity mapped secure memory with Device-nGnRE attributes aligned to 82page boundary (4K) for each BL stage. All sections which allocate coherent 83memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a 84section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its 85possible for the firmware to place variables in it using the following C code 86directive: 87 88:: 89 90 __section(".bakery_lock") 91 92Or alternatively the following assembler code directive: 93 94:: 95 96 .section .bakery_lock 97 98The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are 99used to allocate any data structures that are accessed both when a CPU is 100executing with its MMU and caches enabled, and when it's running with its MMU 101and caches disabled. Examples are given below. 102 103The following variables, functions and constants must be defined by the platform 104for the firmware to work correctly. 105 106.. _platform_def_mandatory: 107 108File : platform_def.h [mandatory] 109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 110 111Each platform must ensure that a header file of this name is in the system 112include path with the following constants defined. This will require updating 113the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 114 115Platform ports may optionally use the file ``include/plat/common/common_def.h``, 116which provides typical values for some of the constants below. These values are 117likely to be suitable for all platform ports. 118 119- **#define : PLATFORM_LINKER_FORMAT** 120 121 Defines the linker format used by the platform, for example 122 ``elf64-littleaarch64``. 123 124- **#define : PLATFORM_LINKER_ARCH** 125 126 Defines the processor architecture for the linker by the platform, for 127 example ``aarch64``. 128 129- **#define : PLATFORM_STACK_SIZE** 130 131 Defines the normal stack memory available to each CPU. This constant is used 132 by ``plat/common/aarch64/platform_mp_stack.S`` and 133 ``plat/common/aarch64/platform_up_stack.S``. 134 135- **#define : CACHE_WRITEBACK_GRANULE** 136 137 Defines the size in bytes of the largest cache line across all the cache 138 levels in the platform. 139 140- **#define : FIRMWARE_WELCOME_STR** 141 142 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 143 function. 144 145- **#define : PLATFORM_CORE_COUNT** 146 147 Defines the total number of CPUs implemented by the platform across all 148 clusters in the system. 149 150- **#define : PLAT_NUM_PWR_DOMAINS** 151 152 Defines the total number of nodes in the power domain topology 153 tree at all the power domain levels used by the platform. 154 This macro is used by the PSCI implementation to allocate 155 data structures to represent power domain topology. 156 157- **#define : PLAT_MAX_PWR_LVL** 158 159 Defines the maximum power domain level that the power management operations 160 should apply to. More often, but not always, the power domain level 161 corresponds to affinity level. This macro allows the PSCI implementation 162 to know the highest power domain level that it should consider for power 163 management operations in the system that the platform implements. For 164 example, the Base AEM FVP implements two clusters with a configurable 165 number of CPUs and it reports the maximum power domain level as 1. 166 167- **#define : PLAT_MAX_OFF_STATE** 168 169 Defines the local power state corresponding to the deepest power down 170 possible at every power domain level in the platform. The local power 171 states for each level may be sparsely allocated between 0 and this value 172 with 0 being reserved for the RUN state. The PSCI implementation uses this 173 value to initialize the local power states of the power domain nodes and 174 to specify the requested power state for a PSCI_CPU_OFF call. 175 176- **#define : PLAT_MAX_RET_STATE** 177 178 Defines the local power state corresponding to the deepest retention state 179 possible at every power domain level in the platform. This macro should be 180 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 181 PSCI implementation to distinguish between retention and power down local 182 power states within PSCI_CPU_SUSPEND call. 183 184- **#define : PLAT_MAX_PWR_LVL_STATES** 185 186 Defines the maximum number of local power states per power domain level 187 that the platform supports. The default value of this macro is 2 since 188 most platforms just support a maximum of two local power states at each 189 power domain level (power-down and retention). If the platform needs to 190 account for more local power states, then it must redefine this macro. 191 192 Currently, this macro is used by the Generic PSCI implementation to size 193 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 194 195- **#define : BL1_RO_BASE** 196 197 Defines the base address in secure ROM where BL1 originally lives. Must be 198 aligned on a page-size boundary. 199 200- **#define : BL1_RO_LIMIT** 201 202 Defines the maximum address in secure ROM that BL1's actual content (i.e. 203 excluding any data section allocated at runtime) can occupy. 204 205- **#define : BL1_RW_BASE** 206 207 Defines the base address in secure RAM where BL1's read-write data will live 208 at runtime. Must be aligned on a page-size boundary. 209 210- **#define : BL1_RW_LIMIT** 211 212 Defines the maximum address in secure RAM that BL1's read-write data can 213 occupy at runtime. 214 215- **#define : BL2_BASE** 216 217 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 218 Must be aligned on a page-size boundary. This constant is not applicable 219 when BL2_IN_XIP_MEM is set to '1'. 220 221- **#define : BL2_LIMIT** 222 223 Defines the maximum address in secure RAM that the BL2 image can occupy. 224 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2_RO_BASE** 227 228 Defines the base address in secure XIP memory where BL2 RO section originally 229 lives. Must be aligned on a page-size boundary. This constant is only needed 230 when BL2_IN_XIP_MEM is set to '1'. 231 232- **#define : BL2_RO_LIMIT** 233 234 Defines the maximum address in secure XIP memory that BL2's actual content 235 (i.e. excluding any data section allocated at runtime) can occupy. This 236 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 237 238- **#define : BL2_RW_BASE** 239 240 Defines the base address in secure RAM where BL2's read-write data will live 241 at runtime. Must be aligned on a page-size boundary. This constant is only 242 needed when BL2_IN_XIP_MEM is set to '1'. 243 244- **#define : BL2_RW_LIMIT** 245 246 Defines the maximum address in secure RAM that BL2's read-write data can 247 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 248 to '1'. 249 250- **#define : BL31_BASE** 251 252 Defines the base address in secure RAM where BL2 loads the BL31 binary 253 image. Must be aligned on a page-size boundary. 254 255- **#define : BL31_LIMIT** 256 257 Defines the maximum address in secure RAM that the BL31 image can occupy. 258 259- **#define : PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE** 260 261 Defines the maximum message size between AP and RSE. Need to define if 262 platform supports RSE. 263 264For every image, the platform must define individual identifiers that will be 265used by BL1 or BL2 to load the corresponding image into memory from non-volatile 266storage. For the sake of performance, integer numbers will be used as 267identifiers. The platform will use those identifiers to return the relevant 268information about the image to be loaded (file handler, load address, 269authentication information, etc.). The following image identifiers are 270mandatory: 271 272- **#define : BL2_IMAGE_ID** 273 274 BL2 image identifier, used by BL1 to load BL2. 275 276- **#define : BL31_IMAGE_ID** 277 278 BL31 image identifier, used by BL2 to load BL31. 279 280- **#define : BL33_IMAGE_ID** 281 282 BL33 image identifier, used by BL2 to load BL33. 283 284If Trusted Board Boot is enabled, the following certificate identifiers must 285also be defined: 286 287- **#define : TRUSTED_BOOT_FW_CERT_ID** 288 289 BL2 content certificate identifier, used by BL1 to load the BL2 content 290 certificate. 291 292- **#define : TRUSTED_KEY_CERT_ID** 293 294 Trusted key certificate identifier, used by BL2 to load the trusted key 295 certificate. 296 297- **#define : SOC_FW_KEY_CERT_ID** 298 299 BL31 key certificate identifier, used by BL2 to load the BL31 key 300 certificate. 301 302- **#define : SOC_FW_CONTENT_CERT_ID** 303 304 BL31 content certificate identifier, used by BL2 to load the BL31 content 305 certificate. 306 307- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 308 309 BL33 key certificate identifier, used by BL2 to load the BL33 key 310 certificate. 311 312- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 313 314 BL33 content certificate identifier, used by BL2 to load the BL33 content 315 certificate. 316 317- **#define : FWU_CERT_ID** 318 319 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 320 FWU content certificate. 321 322If the AP Firmware Updater Configuration image, BL2U is used, the following 323must also be defined: 324 325- **#define : BL2U_BASE** 326 327 Defines the base address in secure memory where BL1 copies the BL2U binary 328 image. Must be aligned on a page-size boundary. 329 330- **#define : BL2U_LIMIT** 331 332 Defines the maximum address in secure memory that the BL2U image can occupy. 333 334- **#define : BL2U_IMAGE_ID** 335 336 BL2U image identifier, used by BL1 to fetch an image descriptor 337 corresponding to BL2U. 338 339If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 340must also be defined: 341 342- **#define : SCP_BL2U_IMAGE_ID** 343 344 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 345 corresponding to SCP_BL2U. 346 347 .. note:: 348 TF-A does not provide source code for this image. 349 350If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 351also be defined: 352 353- **#define : NS_BL1U_BASE** 354 355 Defines the base address in non-secure ROM where NS_BL1U executes. 356 Must be aligned on a page-size boundary. 357 358 .. note:: 359 TF-A does not provide source code for this image. 360 361- **#define : NS_BL1U_IMAGE_ID** 362 363 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 364 corresponding to NS_BL1U. 365 366If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 367be defined: 368 369- **#define : NS_BL2U_BASE** 370 371 Defines the base address in non-secure memory where NS_BL2U executes. 372 Must be aligned on a page-size boundary. 373 374 .. note:: 375 TF-A does not provide source code for this image. 376 377- **#define : NS_BL2U_IMAGE_ID** 378 379 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 380 corresponding to NS_BL2U. 381 382For the the Firmware update capability of TRUSTED BOARD BOOT, the following 383macros may also be defined: 384 385- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 386 387 Total number of images that can be loaded simultaneously. If the platform 388 doesn't specify any value, it defaults to 10. 389 390If a SCP_BL2 image is supported by the platform, the following constants must 391also be defined: 392 393- **#define : SCP_BL2_IMAGE_ID** 394 395 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 396 from platform storage before being transferred to the SCP. 397 398- **#define : SCP_FW_KEY_CERT_ID** 399 400 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 401 certificate (mandatory when Trusted Board Boot is enabled). 402 403- **#define : SCP_FW_CONTENT_CERT_ID** 404 405 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 406 content certificate (mandatory when Trusted Board Boot is enabled). 407 408If a BL32 image is supported by the platform, the following constants must 409also be defined: 410 411- **#define : BL32_IMAGE_ID** 412 413 BL32 image identifier, used by BL2 to load BL32. 414 415- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 416 417 BL32 key certificate identifier, used by BL2 to load the BL32 key 418 certificate (mandatory when Trusted Board Boot is enabled). 419 420- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 421 422 BL32 content certificate identifier, used by BL2 to load the BL32 content 423 certificate (mandatory when Trusted Board Boot is enabled). 424 425- **#define : BL32_BASE** 426 427 Defines the base address in secure memory where BL2 loads the BL32 binary 428 image. Must be aligned on a page-size boundary. 429 430- **#define : BL32_LIMIT** 431 432 Defines the maximum address that the BL32 image can occupy. 433 434If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 435platform, the following constants must also be defined: 436 437- **#define : TSP_SEC_MEM_BASE** 438 439 Defines the base address of the secure memory used by the TSP image on the 440 platform. This must be at the same address or below ``BL32_BASE``. 441 442- **#define : TSP_SEC_MEM_SIZE** 443 444 Defines the size of the secure memory used by the BL32 image on the 445 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 446 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 447 and ``BL32_LIMIT``. 448 449- **#define : TSP_IRQ_SEC_PHY_TIMER** 450 451 Defines the ID of the secure physical generic timer interrupt used by the 452 TSP's interrupt handling code. 453 454If the platform port uses the translation table library code, the following 455constants must also be defined: 456 457- **#define : PLAT_XLAT_TABLES_DYNAMIC** 458 459 Optional flag that can be set per-image to enable the dynamic allocation of 460 regions even when the MMU is enabled. If not defined, only static 461 functionality will be available, if defined and set to 1 it will also 462 include the dynamic functionality. 463 464- **#define : MAX_XLAT_TABLES** 465 466 Defines the maximum number of translation tables that are allocated by the 467 translation table library code. To minimize the amount of runtime memory 468 used, choose the smallest value needed to map the required virtual addresses 469 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 470 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 471 as well. 472 473- **#define : MAX_MMAP_REGIONS** 474 475 Defines the maximum number of regions that are allocated by the translation 476 table library code. A region consists of physical base address, virtual base 477 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 478 defined in the ``mmap_region_t`` structure. The platform defines the regions 479 that should be mapped. Then, the translation table library will create the 480 corresponding tables and descriptors at runtime. To minimize the amount of 481 runtime memory used, choose the smallest value needed to register the 482 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 483 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 484 the dynamic regions as well. 485 486- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 487 488 Defines the total size of the virtual address space in bytes. For example, 489 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 490 491- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 492 493 Defines the total size of the physical address space in bytes. For example, 494 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 495 496If the platform port uses the IO storage framework, the following constants 497must also be defined: 498 499- **#define : MAX_IO_DEVICES** 500 501 Defines the maximum number of registered IO devices. Attempting to register 502 more devices than this value using ``io_register_device()`` will fail with 503 -ENOMEM. 504 505- **#define : MAX_IO_HANDLES** 506 507 Defines the maximum number of open IO handles. Attempting to open more IO 508 entities than this value using ``io_open()`` will fail with -ENOMEM. 509 510- **#define : MAX_IO_BLOCK_DEVICES** 511 512 Defines the maximum number of registered IO block devices. Attempting to 513 register more devices this value using ``io_dev_open()`` will fail 514 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 515 With this macro, multiple block devices could be supported at the same 516 time. 517 518If the platform needs to allocate data within the per-cpu data framework in 519BL31, it should define the following macro. Currently this is only required if 520the platform decides not to use the coherent memory section by undefining the 521``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 522required memory within the the per-cpu data to minimize wastage. 523 524- **#define : PLAT_PCPU_DATA_SIZE** 525 526 Defines the memory (in bytes) to be reserved within the per-cpu data 527 structure for use by the platform layer. 528 529The following constants are optional. They should be defined when the platform 530memory layout implies some image overlaying like in Arm standard platforms. 531 532- **#define : BL31_PROGBITS_LIMIT** 533 534 Defines the maximum address in secure RAM that the BL31's progbits sections 535 can occupy. 536 537- **#define : TSP_PROGBITS_LIMIT** 538 539 Defines the maximum address that the TSP's progbits sections can occupy. 540 541If the platform supports OS-initiated mode, i.e. the build option 542``PSCI_OS_INIT_MODE`` is enabled, and if the platform's maximum power domain 543level for PSCI_CPU_SUSPEND differs from ``PLAT_MAX_PWR_LVL``, the following 544constant must be defined. 545 546- **#define : PLAT_MAX_CPU_SUSPEND_PWR_LVL** 547 548 Defines the maximum power domain level that PSCI_CPU_SUSPEND should apply to. 549 550If the platform port uses the PL061 GPIO driver, the following constant may 551optionally be defined: 552 553- **PLAT_PL061_MAX_GPIOS** 554 Maximum number of GPIOs required by the platform. This allows control how 555 much memory is allocated for PL061 GPIO controllers. The default value is 556 557 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 558 559If the platform port uses the partition driver, the following constant may 560optionally be defined: 561 562- **PLAT_PARTITION_MAX_ENTRIES** 563 Maximum number of partition entries required by the platform. This allows 564 control how much memory is allocated for partition entries. The default 565 value is 128. 566 For example, define the build flag in ``platform.mk``: 567 PLAT_PARTITION_MAX_ENTRIES := 12 568 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 569 570- **PLAT_PARTITION_BLOCK_SIZE** 571 The size of partition block. It could be either 512 bytes or 4096 bytes. 572 The default value is 512. 573 For example, define the build flag in ``platform.mk``: 574 PLAT_PARTITION_BLOCK_SIZE := 4096 575 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) 576 577If the platform port uses the Arm® Ethos™-N NPU driver, the following 578configuration must be performed: 579 580- The NPU SiP service handler must be hooked up. This consists of both the 581 initial setup (``ethosn_smc_setup``) and the handler itself 582 (``ethosn_smc_handler``) 583 584If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support 585enabled, the following constants and configuration must also be defined: 586 587- **ETHOSN_NPU_PROT_FW_NSAID** 588 589 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to 590 access the protected memory that contains the NPU's firmware. 591 592- **ETHOSN_NPU_PROT_DATA_RW_NSAID** 593 594 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 595 read/write access to the protected memory that contains inference data. 596 597- **ETHOSN_NPU_PROT_DATA_RO_NSAID** 598 599 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 600 read-only access to the protected memory that contains inference data. 601 602- **ETHOSN_NPU_NS_RW_DATA_NSAID** 603 604 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 605 read/write access to the non-protected memory. 606 607- **ETHOSN_NPU_NS_RO_DATA_NSAID** 608 609 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 610 read-only access to the non-protected memory. 611 612- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT** 613 614 Defines the physical address range that the NPU's firmware will be loaded 615 into and executed from. 616 617- Configure the platforms TrustZone Controller (TZC) with appropriate regions 618 of protected memory. At minimum this must include a region for the NPU's 619 firmware code and a region for protected inference data, and these must be 620 accessible using the NSAIDs defined above. 621 622- Include the NPU firmware and certificates in the FIP. 623 624- Provide FCONF entries to configure the image source for the NPU firmware 625 and certificates. 626 627- Add MMU mappings such that: 628 629 - BL2 can write the NPU firmware into the region defined by 630 ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT`` 631 - BL31 (SiP service) can read the NPU firmware from the same region 632 633- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images 634 loaded by BL2. 635 636Please see the reference implementation code for the Juno platform as an example. 637 638 639The following constant is optional. It should be defined to override the default 640behaviour of the ``assert()`` function (for example, to save memory). 641 642- **PLAT_LOG_LEVEL_ASSERT** 643 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 644 ``assert()`` prints the name of the file, the line number and the asserted 645 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 646 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 647 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 648 defined, it defaults to ``LOG_LEVEL``. 649 650If the platform port uses the DRTM feature, the following constants must be 651defined: 652 653- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE** 654 655 Maximum Event Log size used by the platform. Platform can decide the maximum 656 size of the Event Log buffer, depending upon the highest hash algorithm 657 chosen and the number of components selected to measure during the DRTM 658 execution flow. 659 660- **#define : PLAT_DRTM_MMAP_ENTRIES** 661 662 Number of the MMAP entries used by the DRTM implementation to calculate the 663 size of address map region of the platform. 664 665File : plat_macros.S [mandatory] 666~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 667 668Each platform must ensure a file of this name is in the system include path with 669the following macro defined. In the Arm development platforms, this file is 670found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 671 672- **Macro : plat_crash_print_regs** 673 674 This macro allows the crash reporting routine to print relevant platform 675 registers in case of an unhandled exception in BL31. This aids in debugging 676 and this macro can be defined to be empty in case register reporting is not 677 desired. 678 679 For instance, GIC or interconnect registers may be helpful for 680 troubleshooting. 681 682Handling Reset 683-------------- 684 685BL1 by default implements the reset vector where execution starts from a cold 686or warm boot. BL31 can be optionally set as a reset vector using the 687``RESET_TO_BL31`` make variable. 688 689For each CPU, the reset vector code is responsible for the following tasks: 690 691#. Distinguishing between a cold boot and a warm boot. 692 693#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 694 the CPU is placed in a platform-specific state until the primary CPU 695 performs the necessary steps to remove it from this state. 696 697#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 698 specific address in the BL31 image in the same processor mode as it was 699 when released from reset. 700 701The following functions need to be implemented by the platform port to enable 702reset vector code to perform the above tasks. 703 704Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 705~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 706 707:: 708 709 Argument : void 710 Return : uintptr_t 711 712This function is called with the MMU and caches disabled 713(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 714distinguishing between a warm and cold reset for the current CPU using 715platform-specific means. If it's a warm reset, then it returns the warm 716reset entrypoint point provided to ``plat_setup_psci_ops()`` during 717BL31 initialization. If it's a cold reset then this function must return zero. 718 719This function does not follow the Procedure Call Standard used by the 720Application Binary Interface for the Arm 64-bit architecture. The caller should 721not assume that callee saved registers are preserved across a call to this 722function. 723 724This function fulfills requirement 1 and 3 listed above. 725 726Note that for platforms that support programming the reset address, it is 727expected that a CPU will start executing code directly at the right address, 728both on a cold and warm reset. In this case, there is no need to identify the 729type of reset nor to query the warm reset entrypoint. Therefore, implementing 730this function is not required on such platforms. 731 732Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 734 735:: 736 737 Argument : void 738 739This function is called with the MMU and data caches disabled. It is responsible 740for placing the executing secondary CPU in a platform-specific state until the 741primary CPU performs the necessary actions to bring it out of that state and 742allow entry into the OS. This function must not return. 743 744In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 745itself off. The primary CPU is responsible for powering up the secondary CPUs 746when normal world software requires them. When booting an EL3 payload instead, 747they stay powered on and are put in a holding pen until their mailbox gets 748populated. 749 750This function fulfills requirement 2 above. 751 752Note that for platforms that can't release secondary CPUs out of reset, only the 753primary CPU will execute the cold boot code. Therefore, implementing this 754function is not required on such platforms. 755 756Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 758 759:: 760 761 Argument : void 762 Return : unsigned int 763 764This function identifies whether the current CPU is the primary CPU or a 765secondary CPU. A return value of zero indicates that the CPU is not the 766primary CPU, while a non-zero return value indicates that the CPU is the 767primary CPU. 768 769Note that for platforms that can't release secondary CPUs out of reset, only the 770primary CPU will execute the cold boot code. Therefore, there is no need to 771distinguish between primary and secondary CPUs and implementing this function is 772not required. 773 774Function : platform_mem_init() [mandatory] 775~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 776 777:: 778 779 Argument : void 780 Return : void 781 782This function is called before any access to data is made by the firmware, in 783order to carry out any essential memory initialization. 784 785Function: plat_get_rotpk_info() 786~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 787 788:: 789 790 Argument : void *, void **, unsigned int *, unsigned int * 791 Return : int 792 793This function is mandatory when Trusted Board Boot is enabled. It returns a 794pointer to the ROTPK stored in the platform (or a hash of it) and its length. 795The ROTPK must be encoded in DER format according to the following ASN.1 796structure: 797 798:: 799 800 AlgorithmIdentifier ::= SEQUENCE { 801 algorithm OBJECT IDENTIFIER, 802 parameters ANY DEFINED BY algorithm OPTIONAL 803 } 804 805 SubjectPublicKeyInfo ::= SEQUENCE { 806 algorithm AlgorithmIdentifier, 807 subjectPublicKey BIT STRING 808 } 809 810In case the function returns a hash of the key: 811 812:: 813 814 DigestInfo ::= SEQUENCE { 815 digestAlgorithm AlgorithmIdentifier, 816 digest OCTET STRING 817 } 818 819The function returns 0 on success. Any other value is treated as error by the 820Trusted Board Boot. The function also reports extra information related 821to the ROTPK in the flags parameter: 822 823:: 824 825 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 826 hash. 827 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 828 verification while the platform ROTPK is not deployed. 829 When this flag is set, the function does not need to 830 return a platform ROTPK, and the authentication 831 framework uses the ROTPK in the certificate without 832 verifying it against the platform value. This flag 833 must not be used in a deployed production environment. 834 835Function: plat_get_nv_ctr() 836~~~~~~~~~~~~~~~~~~~~~~~~~~~ 837 838:: 839 840 Argument : void *, unsigned int * 841 Return : int 842 843This function is mandatory when Trusted Board Boot is enabled. It returns the 844non-volatile counter value stored in the platform in the second argument. The 845cookie in the first argument may be used to select the counter in case the 846platform provides more than one (for example, on platforms that use the default 847TBBR CoT, the cookie will correspond to the OID values defined in 848TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 849 850The function returns 0 on success. Any other value means the counter value could 851not be retrieved from the platform. 852 853Function: plat_set_nv_ctr() 854~~~~~~~~~~~~~~~~~~~~~~~~~~~ 855 856:: 857 858 Argument : void *, unsigned int 859 Return : int 860 861This function is mandatory when Trusted Board Boot is enabled. It sets a new 862counter value in the platform. The cookie in the first argument may be used to 863select the counter (as explained in plat_get_nv_ctr()). The second argument is 864the updated counter value to be written to the NV counter. 865 866The function returns 0 on success. Any other value means the counter value could 867not be updated. 868 869Function: plat_set_nv_ctr2() 870~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 871 872:: 873 874 Argument : void *, const auth_img_desc_t *, unsigned int 875 Return : int 876 877This function is optional when Trusted Board Boot is enabled. If this 878interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 879first argument passed is a cookie and is typically used to 880differentiate between a Non Trusted NV Counter and a Trusted NV 881Counter. The second argument is a pointer to an authentication image 882descriptor and may be used to decide if the counter is allowed to be 883updated or not. The third argument is the updated counter value to 884be written to the NV counter. 885 886The function returns 0 on success. Any other value means the counter value 887either could not be updated or the authentication image descriptor indicates 888that it is not allowed to be updated. 889 890Dynamic Root of Trust for Measurement support (in BL31) 891------------------------------------------------------- 892 893The functions mentioned in this section are mandatory, when platform enables 894DRTM_SUPPORT build flag. 895 896Function : plat_get_addr_mmap() 897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 898 899:: 900 901 Argument : void 902 Return : const mmap_region_t * 903 904This function is used to return the address of the platform *address-map* table, 905which describes the regions of normal memory, memory mapped I/O 906and non-volatile memory. 907 908Function : plat_has_non_host_platforms() 909~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 910 911:: 912 913 Argument : void 914 Return : bool 915 916This function returns *true* if the platform has any trusted devices capable of 917DMA, otherwise returns *false*. 918 919Function : plat_has_unmanaged_dma_peripherals() 920~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 921 922:: 923 924 Argument : void 925 Return : bool 926 927This function returns *true* if platform uses peripherals whose DMA is not 928managed by an SMMU, otherwise returns *false*. 929 930Note - 931If the platform has peripherals that are not managed by the SMMU, then the 932platform should investigate such peripherals to determine whether they can 933be trusted, and such peripherals should be moved under "Non-host platforms" 934if they can be trusted. 935 936Function : plat_get_total_num_smmus() 937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 938 939:: 940 941 Argument : void 942 Return : unsigned int 943 944This function returns the total number of SMMUs in the platform. 945 946Function : plat_enumerate_smmus() 947~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 948:: 949 950 951 Argument : void 952 Return : const uintptr_t *, size_t 953 954This function returns an array of SMMU addresses and the actual number of SMMUs 955reported by the platform. 956 957Function : plat_drtm_get_dma_prot_features() 958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 959 960:: 961 962 Argument : void 963 Return : const plat_drtm_dma_prot_features_t* 964 965This function returns the address of plat_drtm_dma_prot_features_t structure 966containing the maximum number of protected regions and bitmap with the types 967of DMA protection supported by the platform. 968For more details see section 3.3 Table 6 of `DRTM`_ specification. 969 970Function : plat_drtm_dma_prot_get_max_table_bytes() 971~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 972 973:: 974 975 Argument : void 976 Return : uint64_t 977 978This function returns the maximum size of DMA protected regions table in 979bytes. 980 981Function : plat_drtm_get_tpm_features() 982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 983 984:: 985 986 Argument : void 987 Return : const plat_drtm_tpm_features_t* 988 989This function returns the address of *plat_drtm_tpm_features_t* structure 990containing PCR usage schema, TPM-based hash, and firmware hash algorithm 991supported by the platform. 992 993Function : plat_drtm_get_min_size_normal_world_dce() 994~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 995 996:: 997 998 Argument : void 999 Return : uint64_t 1000 1001This function returns the size normal-world DCE of the platform. 1002 1003Function : plat_drtm_get_imp_def_dlme_region_size() 1004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1005 1006:: 1007 1008 Argument : void 1009 Return : uint64_t 1010 1011This function returns the size of implementation defined DLME region 1012of the platform. 1013 1014Function : plat_drtm_get_tcb_hash_table_size() 1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1016 1017:: 1018 1019 Argument : void 1020 Return : uint64_t 1021 1022This function returns the size of TCB hash table of the platform. 1023 1024Function : plat_drtm_get_acpi_tables_region_size() 1025~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1026 1027:: 1028 1029 Argument : void 1030 Return : uint64_t 1031 1032This function returns the size of ACPI tables region of the platform. 1033 1034Function : plat_drtm_get_tcb_hash_features() 1035~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1036 1037:: 1038 1039 Argument : void 1040 Return : uint64_t 1041 1042This function returns the Maximum number of TCB hashes recorded by the 1043platform. 1044For more details see section 3.3 Table 6 of `DRTM`_ specification. 1045 1046Function : plat_drtm_get_dlme_img_auth_features() 1047~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1048 1049:: 1050 1051 Argument : void 1052 Return : uint64_t 1053 1054This function returns the DLME image authentication features. 1055For more details see section 3.3 Table 6 of `DRTM`_ specification. 1056 1057Function : plat_drtm_validate_ns_region() 1058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1059 1060:: 1061 1062 Argument : uintptr_t, uintptr_t 1063 Return : int 1064 1065This function validates that given region is within the Non-Secure region 1066of DRAM. This function takes a region start address and size an input 1067arguments, and returns 0 on success and -1 on failure. 1068 1069Function : plat_set_drtm_error() 1070~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1071 1072:: 1073 1074 Argument : uint64_t 1075 Return : int 1076 1077This function writes a 64 bit error code received as input into 1078non-volatile storage and returns 0 on success and -1 on failure. 1079 1080Function : plat_get_drtm_error() 1081~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1082 1083:: 1084 1085 Argument : uint64_t* 1086 Return : int 1087 1088This function reads a 64 bit error code from the non-volatile storage 1089into the received address, and returns 0 on success and -1 on failure. 1090 1091Common mandatory function modifications 1092--------------------------------------- 1093 1094The following functions are mandatory functions which need to be implemented 1095by the platform port. 1096 1097Function : plat_my_core_pos() 1098~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1099 1100:: 1101 1102 Argument : void 1103 Return : unsigned int 1104 1105This function returns the index of the calling CPU which is used as a 1106CPU-specific linear index into blocks of memory (for example while allocating 1107per-CPU stacks). This function will be invoked very early in the 1108initialization sequence which mandates that this function should be 1109implemented in assembly and should not rely on the availability of a C 1110runtime environment. This function can clobber x0 - x8 and must preserve 1111x9 - x29. 1112 1113This function plays a crucial role in the power domain topology framework in 1114PSCI and details of this can be found in 1115:ref:`PSCI Power Domain Tree Structure`. 1116 1117Function : plat_core_pos_by_mpidr() 1118~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1119 1120:: 1121 1122 Argument : u_register_t 1123 Return : int 1124 1125This function validates the ``MPIDR`` of a CPU and converts it to an index, 1126which can be used as a CPU-specific linear index into blocks of memory. In 1127case the ``MPIDR`` is invalid, this function returns -1. This function will only 1128be invoked by BL31 after the power domain topology is initialized and can 1129utilize the C runtime environment. For further details about how TF-A 1130represents the power domain topology and how this relates to the linear CPU 1131index, please refer :ref:`PSCI Power Domain Tree Structure`. 1132 1133Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 1134~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1135 1136:: 1137 1138 Arguments : void **heap_addr, size_t *heap_size 1139 Return : int 1140 1141This function is invoked during Mbed TLS library initialisation to get a heap, 1142by means of a starting address and a size. This heap will then be used 1143internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 1144must be able to provide a heap to it. 1145 1146A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 1147which a heap is statically reserved during compile time inside every image 1148(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 1149the function simply returns the address and size of this "pre-allocated" heap. 1150For a platform to use this default implementation, only a call to the helper 1151from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 1152 1153However, by writting their own implementation, platforms have the potential to 1154optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 1155shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 1156twice. 1157 1158On success the function should return 0 and a negative error code otherwise. 1159 1160Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] 1161~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1162 1163:: 1164 1165 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, 1166 size_t *key_len, unsigned int *flags, const uint8_t *img_id, 1167 size_t img_id_len 1168 Return : int 1169 1170This function provides a symmetric key (either SSK or BSSK depending on 1171fw_enc_status) which is invoked during runtime decryption of encrypted 1172firmware images. `plat/common/plat_bl_common.c` provides a dummy weak 1173implementation for testing purposes which must be overridden by the platform 1174trying to implement a real world firmware encryption use-case. 1175 1176It also allows the platform to pass symmetric key identifier rather than 1177actual symmetric key which is useful in cases where the crypto backend provides 1178secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` 1179flag must be set in ``flags``. 1180 1181In addition to above a platform may also choose to provide an image specific 1182symmetric key/identifier using img_id. 1183 1184On success the function should return 0 and a negative error code otherwise. 1185 1186Note that this API depends on ``DECRYPTION_SUPPORT`` build flag. 1187 1188Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1] 1189~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1190 1191:: 1192 1193 Argument : const struct fwu_metadata *metadata 1194 Return : void 1195 1196This function is mandatory when PSA_FWU_SUPPORT is enabled. 1197It provides a means to retrieve image specification (offset in 1198non-volatile storage and length) of active/updated images using the passed 1199FWU metadata, and update I/O policies of active/updated images using retrieved 1200image specification information. 1201Further I/O layer operations such as I/O open, I/O read, etc. on these 1202images rely on this function call. 1203 1204In Arm platforms, this function is used to set an I/O policy of the FIP image, 1205container of all active/updated secure and non-secure images. 1206 1207Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1] 1208~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1209 1210:: 1211 1212 Argument : unsigned int image_id, uintptr_t *dev_handle, 1213 uintptr_t *image_spec 1214 Return : int 1215 1216This function is mandatory when PSA_FWU_SUPPORT is enabled. It is 1217responsible for setting up the platform I/O policy of the requested metadata 1218image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will 1219be used to load this image from the platform's non-volatile storage. 1220 1221FWU metadata can not be always stored as a raw image in non-volatile storage 1222to define its image specification (offset in non-volatile storage and length) 1223statically in I/O policy. 1224For example, the FWU metadata image is stored as a partition inside the GUID 1225partition table image. Its specification is defined in the partition table 1226that needs to be parsed dynamically. 1227This function provides a means to retrieve such dynamic information to set 1228the I/O policy of the FWU metadata image. 1229Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata 1230image relies on this function call. 1231 1232It returns '0' on success, otherwise a negative error value on error. 1233Alongside, returns device handle and image specification from the I/O policy 1234of the requested FWU metadata image. 1235 1236Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1] 1237~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1238 1239:: 1240 1241 Argument : void 1242 Return : uint32_t 1243 1244This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the 1245means to retrieve the boot index value from the platform. The boot index is the 1246bank from which the platform has booted the firmware images. 1247 1248By default, the platform will read the metadata structure and try to boot from 1249the active bank. If the platform fails to boot from the active bank due to 1250reasons like an Authentication failure, or on crossing a set number of watchdog 1251resets while booting from the active bank, the platform can then switch to boot 1252from a different bank. This function then returns the bank that the platform 1253should boot its images from. 1254 1255Common optional modifications 1256----------------------------- 1257 1258The following are helper functions implemented by the firmware that perform 1259common platform-specific tasks. A platform may choose to override these 1260definitions. 1261 1262Function : plat_set_my_stack() 1263~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1264 1265:: 1266 1267 Argument : void 1268 Return : void 1269 1270This function sets the current stack pointer to the normal memory stack that 1271has been allocated for the current CPU. For BL images that only require a 1272stack for the primary CPU, the UP version of the function is used. The size 1273of the stack allocated to each CPU is specified by the platform defined 1274constant ``PLATFORM_STACK_SIZE``. 1275 1276Common implementations of this function for the UP and MP BL images are 1277provided in ``plat/common/aarch64/platform_up_stack.S`` and 1278``plat/common/aarch64/platform_mp_stack.S`` 1279 1280Function : plat_get_my_stack() 1281~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1282 1283:: 1284 1285 Argument : void 1286 Return : uintptr_t 1287 1288This function returns the base address of the normal memory stack that 1289has been allocated for the current CPU. For BL images that only require a 1290stack for the primary CPU, the UP version of the function is used. The size 1291of the stack allocated to each CPU is specified by the platform defined 1292constant ``PLATFORM_STACK_SIZE``. 1293 1294Common implementations of this function for the UP and MP BL images are 1295provided in ``plat/common/aarch64/platform_up_stack.S`` and 1296``plat/common/aarch64/platform_mp_stack.S`` 1297 1298Function : plat_report_exception() 1299~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1300 1301:: 1302 1303 Argument : unsigned int 1304 Return : void 1305 1306A platform may need to report various information about its status when an 1307exception is taken, for example the current exception level, the CPU security 1308state (secure/non-secure), the exception type, and so on. This function is 1309called in the following circumstances: 1310 1311- In BL1, whenever an exception is taken. 1312- In BL2, whenever an exception is taken. 1313 1314The default implementation doesn't do anything, to avoid making assumptions 1315about the way the platform displays its status information. 1316 1317For AArch64, this function receives the exception type as its argument. 1318Possible values for exceptions types are listed in the 1319``include/common/bl_common.h`` header file. Note that these constants are not 1320related to any architectural exception code; they are just a TF-A convention. 1321 1322For AArch32, this function receives the exception mode as its argument. 1323Possible values for exception modes are listed in the 1324``include/lib/aarch32/arch.h`` header file. 1325 1326Function : plat_reset_handler() 1327~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1328 1329:: 1330 1331 Argument : void 1332 Return : void 1333 1334A platform may need to do additional initialization after reset. This function 1335allows the platform to do the platform specific initializations. Platform 1336specific errata workarounds could also be implemented here. The API should 1337preserve the values of callee saved registers x19 to x29. 1338 1339The default implementation doesn't do anything. If a platform needs to override 1340the default implementation, refer to the :ref:`Firmware Design` for general 1341guidelines. 1342 1343Function : plat_disable_acp() 1344~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1345 1346:: 1347 1348 Argument : void 1349 Return : void 1350 1351This API allows a platform to disable the Accelerator Coherency Port (if 1352present) during a cluster power down sequence. The default weak implementation 1353doesn't do anything. Since this API is called during the power down sequence, 1354it has restrictions for stack usage and it can use the registers x0 - x17 as 1355scratch registers. It should preserve the value in x18 register as it is used 1356by the caller to store the return address. 1357 1358Function : plat_error_handler() 1359~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1360 1361:: 1362 1363 Argument : int 1364 Return : void 1365 1366This API is called when the generic code encounters an error situation from 1367which it cannot continue. It allows the platform to perform error reporting or 1368recovery actions (for example, reset the system). This function must not return. 1369 1370The parameter indicates the type of error using standard codes from ``errno.h``. 1371Possible errors reported by the generic code are: 1372 1373- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 1374 Board Boot is enabled) 1375- ``-ENOENT``: the requested image or certificate could not be found or an IO 1376 error was detected 1377- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 1378 error is usually an indication of an incorrect array size 1379 1380The default implementation simply spins. 1381 1382Function : plat_panic_handler() 1383~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1384 1385:: 1386 1387 Argument : void 1388 Return : void 1389 1390This API is called when the generic code encounters an unexpected error 1391situation from which it cannot recover. This function must not return, 1392and must be implemented in assembly because it may be called before the C 1393environment is initialized. 1394 1395.. note:: 1396 The address from where it was called is stored in x30 (Link Register). 1397 The default implementation simply spins. 1398 1399Function : plat_get_bl_image_load_info() 1400~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1401 1402:: 1403 1404 Argument : void 1405 Return : bl_load_info_t * 1406 1407This function returns pointer to the list of images that the platform has 1408populated to load. This function is invoked in BL2 to load the 1409BL3xx images. 1410 1411Function : plat_get_next_bl_params() 1412~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1413 1414:: 1415 1416 Argument : void 1417 Return : bl_params_t * 1418 1419This function returns a pointer to the shared memory that the platform has 1420kept aside to pass TF-A related information that next BL image needs. This 1421function is invoked in BL2 to pass this information to the next BL 1422image. 1423 1424Function : plat_get_stack_protector_canary() 1425~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1426 1427:: 1428 1429 Argument : void 1430 Return : u_register_t 1431 1432This function returns a random value that is used to initialize the canary used 1433when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1434value will weaken the protection as the attacker could easily write the right 1435value as part of the attack most of the time. Therefore, it should return a 1436true random number. 1437 1438.. warning:: 1439 For the protection to be effective, the global data need to be placed at 1440 a lower address than the stack bases. Failure to do so would allow an 1441 attacker to overwrite the canary as part of the stack buffer overflow attack. 1442 1443Function : plat_flush_next_bl_params() 1444~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1445 1446:: 1447 1448 Argument : void 1449 Return : void 1450 1451This function flushes to main memory all the image params that are passed to 1452next image. This function is invoked in BL2 to flush this information 1453to the next BL image. 1454 1455Function : plat_log_get_prefix() 1456~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1457 1458:: 1459 1460 Argument : unsigned int 1461 Return : const char * 1462 1463This function defines the prefix string corresponding to the `log_level` to be 1464prepended to all the log output from TF-A. The `log_level` (argument) will 1465correspond to one of the standard log levels defined in debug.h. The platform 1466can override the common implementation to define a different prefix string for 1467the log output. The implementation should be robust to future changes that 1468increase the number of log levels. 1469 1470Function : plat_get_soc_version() 1471~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1472 1473:: 1474 1475 Argument : void 1476 Return : int32_t 1477 1478This function returns soc version which mainly consist of below fields 1479 1480:: 1481 1482 soc_version[30:24] = JEP-106 continuation code for the SiP 1483 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 1484 soc_version[15:0] = Implementation defined SoC ID 1485 1486Function : plat_get_soc_revision() 1487~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1488 1489:: 1490 1491 Argument : void 1492 Return : int32_t 1493 1494This function returns soc revision in below format 1495 1496:: 1497 1498 soc_revision[0:30] = SOC revision of specific SOC 1499 1500Function : plat_get_soc_name() 1501~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1502 1503:: 1504 1505 Argument : char ** 1506 Return : int32_t 1507 1508The plat_get_soc_name() function allows a platform to expose the SoC name to 1509the firmware. It takes a pointer to a character pointer as an argument, which 1510must be set to point to a static, null-terminated SoC name string. The string 1511must be encoded in UTF-8 and should use only printable ASCII characters for 1512compatibility. It must not exceed 136 bytes, including the null terminator. On 1513success, the function returns SMC_ARCH_CALL_SUCCESS. If the platform does not 1514support SoC name retrieval, it returns SMC_ARCH_CALL_NOT_SUPPORTED. This API 1515allows platforms to support SoC name queries via SMCCC_ARCH_SOC_ID. 1516 1517Function : plat_is_smccc_feature_available() 1518~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1519 1520:: 1521 1522 Argument : u_register_t 1523 Return : int32_t 1524 1525This function returns SMC_ARCH_CALL_SUCCESS if the platform supports 1526the SMCCC function specified in the argument; otherwise returns 1527SMC_ARCH_CALL_NOT_SUPPORTED. 1528 1529Function : plat_can_cmo() 1530~~~~~~~~~~~~~~~~~~~~~~~~~ 1531 1532:: 1533 1534 Argument : void 1535 Return : uint64_t 1536 1537When CONDITIONAL_CMO flag is enabled: 1538 1539- This function indicates whether cache management operations should be 1540 performed. It returns 0 if CMOs should be skipped and non-zero 1541 otherwise. 1542- The function must not clobber x1, x2 and x3. It's also not safe to rely on 1543 stack. Otherwise obey AAPCS. 1544 1545Struct: plat_try_images_ops [optional] 1546~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1547 1548This optional structure holds platform hooks for alternative images load. 1549It has to be defined in platform code and registered by calling 1550plat_setup_try_img_ops() function, passing it the address of the 1551plat_try_images_ops struct. 1552 1553Function : plat_setup_try_img_ops [optional] 1554............................................ 1555 1556:: 1557 1558 Argument : const struct plat_try_images_ops * 1559 Return : void 1560 1561This optional function is called to register platform try images ops, given 1562as argument. 1563 1564Function : plat_try_images_ops.next_instance [optional] 1565....................................................... 1566 1567:: 1568 1569 Argument : unsigned int image_id 1570 Return : int 1571 1572This optional function tries to load images from alternative places. 1573In case PSA FWU is not used, it can be any instance or media. If PSA FWU is 1574used, it is mandatory that the backup image is on the same media. 1575This is required for MTD devices like NAND. 1576The argument is the ID of the image for which we are looking for an alternative 1577place. It returns 0 in case of success and a negative errno value otherwise. 1578 1579Function : plat_setup_log_gpt_corrupted [optional] 1580.................................................. 1581 1582:: 1583 1584 Argument : const struct plat_log_gpt_corrupted * 1585 Return : void 1586 1587This optional function is called to register platform log GPT corrupted functions, 1588given as argument. 1589 1590Function : plat_setup_log_gpt_corrupted.plat_set_gpt_corruption [optional] 1591.......................................................................... 1592 1593:: 1594 1595 Argument : uintptr_t gpt_corrupted_info_ptr, uint8_t flags 1596 Return : void 1597 1598This optional function will log error information if the GPT is corrupted, by 1599setting the address passed by gpt_corrupted_info_ptr to flags value, currently 1600bit[0] is used for logging primary GPT corruption, bit[7:1] are reserved. 1601The data type passed by reference is uint8_t. 1602 1603Function : plat_setup_log_gpt_corrupted.plat_log_gpt_corruption [optional] 1604.......................................................................... 1605 1606:: 1607 1608 Argument : uintptr_t log_address, uint8_t gpt_corrupted_info 1609 Return : void 1610 1611This optional function will log if the primary GPT is corrupted, by writing 1612the value of gpt_corrupted_info to the address passed by log_address. 1613 1614Modifications specific to a Boot Loader stage 1615--------------------------------------------- 1616 1617Boot Loader Stage 1 (BL1) 1618------------------------- 1619 1620BL1 implements the reset vector where execution starts from after a cold or 1621warm boot. For each CPU, BL1 is responsible for the following tasks: 1622 1623#. Handling the reset as described in section 2.2 1624 1625#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1626 only this CPU executes the remaining BL1 code, including loading and passing 1627 control to the BL2 stage. 1628 1629#. Identifying and starting the Firmware Update process (if required). 1630 1631#. Loading the BL2 image from non-volatile storage into secure memory at the 1632 address specified by the platform defined constant ``BL2_BASE``. 1633 1634#. Populating a ``meminfo`` structure with the following information in memory, 1635 accessible by BL2 immediately upon entry. 1636 1637 :: 1638 1639 meminfo.total_base = Base address of secure RAM visible to BL2 1640 meminfo.total_size = Size of secure RAM visible to BL2 1641 1642 By default, BL1 places this ``meminfo`` structure at the end of secure 1643 memory visible to BL2. 1644 1645 It is possible for the platform to decide where it wants to place the 1646 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1647 BL2 by overriding the weak default implementation of 1648 ``bl1_plat_handle_post_image_load`` API. 1649 1650The following functions need to be implemented by the platform port to enable 1651BL1 to perform the above tasks. 1652 1653Function : bl1_early_platform_setup() [mandatory] 1654~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1655 1656:: 1657 1658 Argument : void 1659 Return : void 1660 1661This function executes with the MMU and data caches disabled. It is only called 1662by the primary CPU. 1663 1664On Arm standard platforms, this function: 1665 1666- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1667 1668- Initializes a UART (PL011 console), which enables access to the ``printf`` 1669 family of functions in BL1. 1670 1671- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1672 the CCI slave interface corresponding to the cluster that includes the 1673 primary CPU. 1674 1675Function : bl1_plat_arch_setup() [mandatory] 1676~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1677 1678:: 1679 1680 Argument : void 1681 Return : void 1682 1683This function performs any platform-specific and architectural setup that the 1684platform requires. Platform-specific setup might include configuration of 1685memory controllers and the interconnect. 1686 1687In Arm standard platforms, this function enables the MMU. 1688 1689This function helps fulfill requirement 2 above. 1690 1691Function : bl1_platform_setup() [mandatory] 1692~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1693 1694:: 1695 1696 Argument : void 1697 Return : void 1698 1699This function executes with the MMU and data caches enabled. It is responsible 1700for performing any remaining platform-specific setup that can occur after the 1701MMU and data cache have been enabled. 1702 1703In Arm standard platforms, this function initializes the storage abstraction 1704layer used to load the next bootloader image. 1705 1706This function helps fulfill requirement 4 above. 1707 1708Function : bl1_plat_sec_mem_layout() [mandatory] 1709~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1710 1711:: 1712 1713 Argument : void 1714 Return : meminfo * 1715 1716This function should only be called on the cold boot path. It executes with the 1717MMU and data caches enabled. The pointer returned by this function must point to 1718a ``meminfo`` structure containing the extents and availability of secure RAM for 1719the BL1 stage. 1720 1721:: 1722 1723 meminfo.total_base = Base address of secure RAM visible to BL1 1724 meminfo.total_size = Size of secure RAM visible to BL1 1725 1726This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1727populates a similar structure to tell BL2 the extents of memory available for 1728its own use. 1729 1730This function helps fulfill requirements 4 and 5 above. 1731 1732Function : bl1_plat_prepare_exit() [optional] 1733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1734 1735:: 1736 1737 Argument : entry_point_info_t * 1738 Return : void 1739 1740This function is called prior to exiting BL1 in response to the 1741``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1742platform specific clean up or bookkeeping operations before transferring 1743control to the next image. It receives the address of the ``entry_point_info_t`` 1744structure passed from BL2. This function runs with MMU disabled. 1745 1746Function : bl1_plat_set_ep_info() [optional] 1747~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1748 1749:: 1750 1751 Argument : unsigned int image_id, entry_point_info_t *ep_info 1752 Return : void 1753 1754This function allows platforms to override ``ep_info`` for the given ``image_id``. 1755 1756The default implementation just returns. 1757 1758Function : bl1_plat_get_next_image_id() [optional] 1759~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1760 1761:: 1762 1763 Argument : void 1764 Return : unsigned int 1765 1766This and the following function must be overridden to enable the FWU feature. 1767 1768BL1 calls this function after platform setup to identify the next image to be 1769loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1770with the normal boot sequence, which loads and executes BL2. If the platform 1771returns a different image id, BL1 assumes that Firmware Update is required. 1772 1773The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1774platforms override this function to detect if firmware update is required, and 1775if so, return the first image in the firmware update process. 1776 1777Function : bl1_plat_get_image_desc() [optional] 1778~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1779 1780:: 1781 1782 Argument : unsigned int image_id 1783 Return : image_desc_t * 1784 1785BL1 calls this function to get the image descriptor information ``image_desc_t`` 1786for the provided ``image_id`` from the platform. 1787 1788The default implementation always returns a common BL2 image descriptor. Arm 1789standard platforms return an image descriptor corresponding to BL2 or one of 1790the firmware update images defined in the Trusted Board Boot Requirements 1791specification. 1792 1793Function : bl1_plat_handle_pre_image_load() [optional] 1794~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1795 1796:: 1797 1798 Argument : unsigned int image_id 1799 Return : int 1800 1801This function can be used by the platforms to update/use image information 1802corresponding to ``image_id``. This function is invoked in BL1, both in cold 1803boot and FWU code path, before loading the image. 1804 1805Function : bl1_plat_calc_bl2_layout() [optional] 1806~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1807 1808:: 1809 1810 Argument : const meminfo_t *bl1_mem_layout, meminfo_t *bl2_mem_layout 1811 Return : void 1812 1813This utility function calculates the memory layout of BL2, representing it in a 1814`meminfo_t` structure. The default implementation derives this layout from the 1815positioning of BL1’s RW data at the top of the memory layout. 1816 1817Function : bl1_plat_handle_post_image_load() [optional] 1818~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1819 1820:: 1821 1822 Argument : unsigned int image_id 1823 Return : int 1824 1825This function can be used by the platforms to update/use image information 1826corresponding to ``image_id``. This function is invoked in BL1, both in cold 1827boot and FWU code path, after loading and authenticating the image. 1828 1829The default weak implementation of this function calculates the amount of 1830Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1831structure at the beginning of this free memory and populates it. The address 1832of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1833information to BL2. 1834 1835Function : bl1_plat_fwu_done() [optional] 1836~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1837 1838:: 1839 1840 Argument : unsigned int image_id, uintptr_t image_src, 1841 unsigned int image_size 1842 Return : void 1843 1844BL1 calls this function when the FWU process is complete. It must not return. 1845The platform may override this function to take platform specific action, for 1846example to initiate the normal boot flow. 1847 1848The default implementation spins forever. 1849 1850Function : bl1_plat_mem_check() [mandatory] 1851~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1852 1853:: 1854 1855 Argument : uintptr_t mem_base, unsigned int mem_size, 1856 unsigned int flags 1857 Return : int 1858 1859BL1 calls this function while handling FWU related SMCs, more specifically when 1860copying or authenticating an image. Its responsibility is to ensure that the 1861region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1862that this memory corresponds to either a secure or non-secure memory region as 1863indicated by the security state of the ``flags`` argument. 1864 1865This function can safely assume that the value resulting from the addition of 1866``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1867overflow. 1868 1869This function must return 0 on success, a non-null error code otherwise. 1870 1871The default implementation of this function asserts therefore platforms must 1872override it when using the FWU feature. 1873 1874Boot Loader Stage 2 (BL2) 1875------------------------- 1876 1877The BL2 stage is executed only by the primary CPU, which is determined in BL1 1878using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1879``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1880``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1881non-volatile storage to secure/non-secure RAM. After all the images are loaded 1882then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1883images to be passed to the next BL image. 1884 1885The following functions must be implemented by the platform port to enable BL2 1886to perform the above tasks. 1887 1888Function : bl2_early_platform_setup2() [mandatory] 1889~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1890 1891:: 1892 1893 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1894 Return : void 1895 1896This function executes with the MMU and data caches disabled. It is only called 1897by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1898are platform specific. 1899 1900On Arm standard platforms, the arguments received are : 1901 1902 arg0 - Points to load address of FW_CONFIG 1903 1904 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1905 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1906 1907On Arm standard platforms, this function also: 1908 1909- Initializes a UART (PL011 console), which enables access to the ``printf`` 1910 family of functions in BL2. 1911 1912- Initializes the storage abstraction layer used to load further bootloader 1913 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1914 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1915 1916Function : bl2_plat_arch_setup() [mandatory] 1917~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1918 1919:: 1920 1921 Argument : void 1922 Return : void 1923 1924This function executes with the MMU and data caches disabled. It is only called 1925by the primary CPU. 1926 1927The purpose of this function is to perform any architectural initialization 1928that varies across platforms. 1929 1930On Arm standard platforms, this function enables the MMU. 1931 1932Function : bl2_platform_setup() [mandatory] 1933~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1934 1935:: 1936 1937 Argument : void 1938 Return : void 1939 1940This function may execute with the MMU and data caches enabled if the platform 1941port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1942called by the primary CPU. 1943 1944The purpose of this function is to perform any platform initialization 1945specific to BL2. 1946 1947In Arm standard platforms, this function performs security setup, including 1948configuration of the TrustZone controller to allow non-secure masters access 1949to most of DRAM. Part of DRAM is reserved for secure world use. 1950 1951Function : bl2_plat_handle_pre_image_load() [optional] 1952~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1953 1954:: 1955 1956 Argument : unsigned int 1957 Return : int 1958 1959This function can be used by the platforms to update/use image information 1960for given ``image_id``. This function is currently invoked in BL2 before 1961loading each image. 1962 1963Function : bl2_plat_handle_post_image_load() [optional] 1964~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1965 1966:: 1967 1968 Argument : unsigned int 1969 Return : int 1970 1971This function can be used by the platforms to update/use image information 1972for given ``image_id``. This function is currently invoked in BL2 after 1973loading each image. 1974 1975Function : bl2_plat_preload_setup [optional] 1976~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1977 1978:: 1979 1980 Argument : void 1981 Return : void 1982 1983This optional function performs any BL2 platform initialization 1984required before image loading, that is not done later in 1985bl2_platform_setup(). 1986 1987Boot Loader Stage 2 (BL2) at EL3 1988-------------------------------- 1989 1990When the platform has a non-TF-A Boot ROM it is desirable to jump 1991directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1992execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` 1993document for more information. 1994 1995All mandatory functions of BL2 must be implemented, except the functions 1996bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 1997their work is done now by bl2_el3_early_platform_setup and 1998bl2_el3_plat_arch_setup. These functions should generally implement 1999the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 2000 2001 2002Function : bl2_el3_early_platform_setup() [mandatory] 2003~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2004 2005:: 2006 2007 Argument : u_register_t, u_register_t, u_register_t, u_register_t 2008 Return : void 2009 2010This function executes with the MMU and data caches disabled. It is only called 2011by the primary CPU. This function receives four parameters which can be used 2012by the platform to pass any needed information from the Boot ROM to BL2. 2013 2014On Arm standard platforms, this function does the following: 2015 2016- Initializes a UART (PL011 console), which enables access to the ``printf`` 2017 family of functions in BL2. 2018 2019- Initializes the storage abstraction layer used to load further bootloader 2020 images. It is necessary to do this early on platforms with a SCP_BL2 image, 2021 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 2022 2023- Initializes the private variables that define the memory layout used. 2024 2025Function : bl2_el3_plat_arch_setup() [mandatory] 2026~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2027 2028:: 2029 2030 Argument : void 2031 Return : void 2032 2033This function executes with the MMU and data caches disabled. It is only called 2034by the primary CPU. 2035 2036The purpose of this function is to perform any architectural initialization 2037that varies across platforms. 2038 2039On Arm standard platforms, this function enables the MMU. 2040 2041Function : bl2_el3_plat_prepare_exit() [optional] 2042~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2043 2044:: 2045 2046 Argument : void 2047 Return : void 2048 2049This function is called prior to exiting BL2 and run the next image. 2050It should be used to perform platform specific clean up or bookkeeping 2051operations before transferring control to the next image. This function 2052runs with MMU disabled. 2053 2054FWU Boot Loader Stage 2 (BL2U) 2055------------------------------ 2056 2057The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 2058process and is executed only by the primary CPU. BL1 passes control to BL2U at 2059``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 2060 2061#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 2062 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 2063 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 2064 should be copied from. Subsequent handling of the SCP_BL2U image is 2065 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 2066 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 2067 2068#. Any platform specific setup required to perform the FWU process. For 2069 example, Arm standard platforms initialize the TZC controller so that the 2070 normal world can access DDR memory. 2071 2072The following functions must be implemented by the platform port to enable 2073BL2U to perform the tasks mentioned above. 2074 2075Function : bl2u_early_platform_setup() [mandatory] 2076~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2077 2078:: 2079 2080 Argument : meminfo *mem_info, void *plat_info 2081 Return : void 2082 2083This function executes with the MMU and data caches disabled. It is only 2084called by the primary CPU. The arguments to this function is the address 2085of the ``meminfo`` structure and platform specific info provided by BL1. 2086 2087The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 2088private storage as the original memory may be subsequently overwritten by BL2U. 2089 2090On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 2091to extract SCP_BL2U image information, which is then copied into a private 2092variable. 2093 2094Function : bl2u_plat_arch_setup() [mandatory] 2095~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2096 2097:: 2098 2099 Argument : void 2100 Return : void 2101 2102This function executes with the MMU and data caches disabled. It is only 2103called by the primary CPU. 2104 2105The purpose of this function is to perform any architectural initialization 2106that varies across platforms, for example enabling the MMU (since the memory 2107map differs across platforms). 2108 2109Function : bl2u_platform_setup() [mandatory] 2110~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2111 2112:: 2113 2114 Argument : void 2115 Return : void 2116 2117This function may execute with the MMU and data caches enabled if the platform 2118port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 2119called by the primary CPU. 2120 2121The purpose of this function is to perform any platform initialization 2122specific to BL2U. 2123 2124In Arm standard platforms, this function performs security setup, including 2125configuration of the TrustZone controller to allow non-secure masters access 2126to most of DRAM. Part of DRAM is reserved for secure world use. 2127 2128Function : bl2u_plat_handle_scp_bl2u() [optional] 2129~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2130 2131:: 2132 2133 Argument : void 2134 Return : int 2135 2136This function is used to perform any platform-specific actions required to 2137handle the SCP firmware. Typically it transfers the image into SCP memory using 2138a platform-specific protocol and waits until SCP executes it and signals to the 2139Application Processor (AP) for BL2U execution to continue. 2140 2141This function returns 0 on success, a negative error code otherwise. 2142This function is included if SCP_BL2U_BASE is defined. 2143 2144Boot Loader Stage 3-1 (BL31) 2145---------------------------- 2146 2147During cold boot, the BL31 stage is executed only by the primary CPU. This is 2148determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 2149control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 2150CPUs. BL31 executes at EL3 and is responsible for: 2151 2152#. Re-initializing all architectural and platform state. Although BL1 performs 2153 some of this initialization, BL31 remains resident in EL3 and must ensure 2154 that EL3 architectural and platform state is completely initialized. It 2155 should make no assumptions about the system state when it receives control. 2156 2157#. Passing control to a normal world BL image, pre-loaded at a platform- 2158 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 2159 populated by BL2 in memory to do this. 2160 2161#. Providing runtime firmware services. Currently, BL31 only implements a 2162 subset of the Power State Coordination Interface (PSCI) API as a runtime 2163 service. See :ref:`psci_in_bl31` below for details of porting the PSCI 2164 implementation. 2165 2166#. Optionally passing control to the BL32 image, pre-loaded at a platform- 2167 specific address by BL2. BL31 exports a set of APIs that allow runtime 2168 services to specify the security state in which the next image should be 2169 executed and run the corresponding image. On ARM platforms, BL31 uses the 2170 ``bl_params`` list populated by BL2 in memory to do this. 2171 2172If BL31 is a reset vector, It also needs to handle the reset as specified in 2173section 2.2 before the tasks described above. 2174 2175The following functions must be implemented by the platform port to enable BL31 2176to perform the above tasks. 2177 2178Function : bl31_early_platform_setup2() [mandatory] 2179~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2180 2181:: 2182 2183 Argument : u_register_t, u_register_t, u_register_t, u_register_t 2184 Return : void 2185 2186This function executes with the MMU and data caches disabled. It is only called 2187by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 2188platform specific. 2189 2190In Arm standard platforms, the arguments received are : 2191 2192 arg0 - The pointer to the head of `bl_params_t` list 2193 which is list of executable images following BL31, 2194 2195 arg1 - Points to load address of SOC_FW_CONFIG if present 2196 except in case of Arm FVP and Juno platform. 2197 2198 In case of Arm FVP and Juno platform, points to load address 2199 of FW_CONFIG. 2200 2201 arg2 - Points to load address of HW_CONFIG if present 2202 2203 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 2204 used in release builds. 2205 2206The function runs through the `bl_param_t` list and extracts the entry point 2207information for BL32 and BL33. It also performs the following: 2208 2209- Initialize a UART (PL011 console), which enables access to the ``printf`` 2210 family of functions in BL31. 2211 2212- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 2213 CCI slave interface corresponding to the cluster that includes the primary 2214 CPU. 2215 2216Function : bl31_plat_arch_setup() [mandatory] 2217~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2218 2219:: 2220 2221 Argument : void 2222 Return : void 2223 2224This function executes with the MMU and data caches disabled. It is only called 2225by the primary CPU. 2226 2227The purpose of this function is to perform any architectural initialization 2228that varies across platforms. 2229 2230On Arm standard platforms, this function enables the MMU. 2231 2232Function : bl31_platform_setup() [mandatory] 2233~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2234 2235:: 2236 2237 Argument : void 2238 Return : void 2239 2240This function may execute with the MMU and data caches enabled if the platform 2241port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 2242called by the primary CPU. 2243 2244The purpose of this function is to complete platform initialization so that both 2245BL31 runtime services and normal world software can function correctly. 2246 2247On Arm standard platforms, this function does the following: 2248 2249- Initialize the generic interrupt controller. 2250 2251 Depending on the GIC driver selected by the platform, the appropriate GICv2 2252 or GICv3 initialization will be done, which mainly consists of: 2253 2254 - Enable secure interrupts in the GIC CPU interface. 2255 - Disable the legacy interrupt bypass mechanism. 2256 - Configure the priority mask register to allow interrupts of all priorities 2257 to be signaled to the CPU interface. 2258 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 2259 - Target all secure SPIs to CPU0. 2260 - Enable these secure interrupts in the GIC distributor. 2261 - Configure all other interrupts as non-secure. 2262 - Enable signaling of secure interrupts in the GIC distributor. 2263 2264- Enable system-level implementation of the generic timer counter through the 2265 memory mapped interface. 2266 2267- Grant access to the system counter timer module 2268 2269- Initialize the power controller device. 2270 2271 In particular, initialise the locks that prevent concurrent accesses to the 2272 power controller device. 2273 2274Function : bl31_plat_runtime_setup() [optional] 2275~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2276 2277:: 2278 2279 Argument : void 2280 Return : void 2281 2282The purpose of this function is to allow the platform to perform any BL31 runtime 2283setup just prior to BL31 exit during cold boot. The default weak implementation 2284of this function is empty. Any platform that needs to perform additional runtime 2285setup, before BL31 exits, will need to override this function. 2286 2287Function : bl31_plat_get_next_image_ep_info() [mandatory] 2288~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2289 2290:: 2291 2292 Argument : uint32_t 2293 Return : entry_point_info * 2294 2295This function may execute with the MMU and data caches enabled if the platform 2296port does the necessary initializations in ``bl31_plat_arch_setup()``. 2297 2298This function is called by ``bl31_main()`` to retrieve information provided by 2299BL2 for the next image in the security state specified by the argument. BL31 2300uses this information to pass control to that image in the specified security 2301state. This function must return a pointer to the ``entry_point_info`` structure 2302(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2303should return NULL otherwise. 2304 2305Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1] 2306~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2307 2308:: 2309 2310 Argument : uintptr_t, size_t *, uintptr_t, size_t, size_t * 2311 Return : int 2312 2313This function returns the Platform attestation token. If the full token does 2314not fit in the buffer, the function will return a hunk of the token and 2315indicate how many bytes were copied and how many are pending. Multiple calls 2316to this function may be needed to retrieve the entire token. 2317 2318The parameters of the function are: 2319 2320 arg0 - A pointer to the buffer where the Platform token should be copied by 2321 this function. If the platform token does not completely fit in the 2322 buffer, the function may return a piece of the token only. 2323 2324 arg1 - Contains the size (in bytes) of the buffer passed in arg0. In 2325 addition, this parameter is used by the function to return the size 2326 of the platform token length hunk copied to the buffer. 2327 2328 arg2 - A pointer to the buffer where the challenge object is stored. 2329 2330 arg3 - The length of the challenge object in bytes. Possible values are 32, 2331 48 and 64. This argument must be zero for subsequent calls to 2332 retrieve the remaining hunks of the token. 2333 2334 arg4 - Returns the remaining length of the token (in bytes) that is yet to 2335 be returned in further calls. 2336 2337The function returns 0 on success, -EINVAL on failure and -EAGAIN if the 2338resource associated with the platform token retrieval is busy. 2339 2340Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] 2341~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2342 2343:: 2344 2345 Argument : uintptr_t, size_t *, unsigned int 2346 Return : int 2347 2348This function returns the delegated realm attestation key which will be used to 2349sign Realm attestation token. The API currently only supports P-384 ECC curve 2350key. 2351 2352The parameters of the function are: 2353 2354 arg0 - A pointer to the buffer where the attestation key should be copied 2355 by this function. The buffer must be big enough to hold the 2356 attestation key. 2357 2358 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2359 function returns the attestation key length in this parameter. 2360 2361 arg2 - The type of the elliptic curve to which the requested attestation key 2362 belongs. 2363 2364The function returns 0 on success, -EINVAL on failure. 2365 2366Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1] 2367~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2368 2369:: 2370 2371 Argument : uintptr_t * 2372 Return : size_t 2373 2374This function returns the size of the shared area between EL3 and RMM (or 0 on 2375failure). A pointer to the shared area (or a NULL pointer on failure) is stored 2376in the pointer passed as argument. 2377 2378Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1] 2379~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2380 2381:: 2382 2383 Arguments : rmm_manifest_t *manifest 2384 Return : int 2385 2386When ENABLE_RME is enabled, this function populates a boot manifest for the 2387RMM image and stores it in the area specified by manifest. 2388 2389When ENABLE_RME is disabled, this function is not used. 2390 2391Function : plat_rmmd_mecid_key_update() [when ENABLE_RME == 1] 2392~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2393 2394:: 2395 2396 Argument : uint16_t, unsigned int 2397 Return : int 2398 2399This function is invoked by BL31's RMMD when there is a request from the RMM 2400monitor to update the tweak for the encryption key associated to a MECID. 2401 2402The first parameter (``uint16_t mecid``) contains the MECID for which the 2403encryption key is to be updated. The second argument specifies the reason 2404for key update. Possible values are: 0 - Realm creation, 1 - Realm destruction. 2405 2406Return value is 0 upon success and -EFAULT otherwise. 2407 2408This function needs to be implemented by a platform if it enables RME. 2409 2410Function : plat_rmmd_reserve_memory() [when ENABLE_RME == 1] 2411~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2412 2413:: 2414 2415 Arguments : size_t size, unsigned long alignment 2416 Return : uintptr_t 2417 2418Reserve memory to be used by the RMM. This could be memory simply taken from a pool of reserved 2419memory, for instance from a carveout dedicated to RMM. 2420 2421Return value is the physical address of a memory region of at least ``size`` bytes, which needs 2422to be aligned to ``alignment`` bytes. 2423 2424This function needs to be implemented if a platform enables RME and the RMM requires the memory 2425reservation feature. 2426 2427Function : plat_rmmd_el3_token_sign_push_req() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2428~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2429 2430:: 2431 2432 Arguments : const struct el3_token_sign_request *req 2433 Return : int 2434 2435Queue realm attestation token signing request from the RMM in EL3. The interface between 2436the RMM and EL3 is modeled as a queue but the underlying implementation may be different, 2437so long as the semantics of queuing and the error codes are used as defined below. 2438 2439See :ref:`el3_token_sign_request_struct` for definition of the request structure. 2440 2441Optional interface from the RMM-EL3 interface v0.4 onwards. 2442 2443The parameters of the functions are: 2444 arg0: Pointer to the token sign request to be pushed to EL3. 2445 The structure must be located in the RMM-EL3 shared 2446 memory buffer and must be locked before use. 2447 2448Return codes: 2449 - E_RMM_OK On Success. 2450 - E_RMM_INVAL If the arguments are invalid. 2451 - E_RMM_AGAIN Indicates that the request was not queued since the 2452 queue in EL3 is full. This may also be returned for any reason 2453 or situation in the system, that prevents accepting the request 2454 from the RMM. 2455 - E_RMM_UNK If the SMC is not implemented or if interface 2456 version is < 0.4. 2457 2458Function : plat_rmmd_el3_token_sign_pull_resp() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2459~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2460 2461:: 2462 2463 Arguments : struct el3_token_sign_response *resp 2464 Return : int 2465 2466Populate the attestation signing response in the ``resp`` parameter. The interface between 2467the RMM and EL3 is modeled as a queue for responses but the underlying implementation may 2468be different, so long as the semantics of queuing and the error codes are used as defined 2469below. 2470 2471See :ref:`el3_token_sign_response_struct` for definition of the response structure. 2472 2473Optional interface from the RMM-EL3 interface v0.4 onwards. 2474 2475The parameters of the functions are: 2476 resp: Pointer to the token sign response to get from EL3. 2477 The structure must be located in the RMM-EL3 shared 2478 memory buffer and must be locked before use. 2479 2480Return: 2481 - E_RMM_OK On Success. 2482 - E_RMM_INVAL If the arguments are invalid. 2483 - E_RMM_AGAIN Indicates that a response is not ready yet. 2484 - E_RMM_UNK If the SMC is not implemented or if interface 2485 version is < 0.4. 2486 2487Function : plat_rmmd_el3_token_sign_get_rak_pub() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2488~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2489 2490:: 2491 2492 Argument : uintptr_t, size_t *, unsigned int 2493 Return : int 2494 2495This function returns the public portion of the realm attestation key which will be used to 2496sign Realm attestation token. Typically, with delegated attestation, the private key is 2497returned, however, there may be platforms where the private key bits are better protected 2498in a platform specific manner such that the private key is not exposed. In such cases, 2499the RMM will only cache the public key and forward any requests such as signing, that 2500uses the private key to EL3. The API currently only supports P-384 ECC curve key. 2501 2502This is an optional interface from the RMM-EL3 interface v0.4 onwards. 2503 2504The parameters of the function are: 2505 2506 arg0 - A pointer to the buffer where the public key should be copied 2507 by this function. The buffer must be big enough to hold the 2508 attestation key. 2509 2510 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2511 function returns the attestation key length in this parameter. 2512 2513 arg2 - The type of the elliptic curve to which the requested attestation key 2514 belongs. 2515 2516The function returns E_RMM_OK on success, RMM_E_INVAL if arguments are invalid and 2517E_RMM_UNK if the SMC is not implemented or if interface version is < 0.4. 2518 2519Function : plat_rmmd_el3_ide_key_program() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1] 2520~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2521 2522:: 2523 2524 Argument : uint64_t, uint64_t, uint64_t, struct rp_ide_key_info_t *, uint64_t, uint64_t 2525 Return : int 2526 2527This function sets the key/IV info for an IDE stream at the Root port. The key is 256 bits 2528and IV is 96 bits. The caller calls this SMC to program this key to the Rx and Tx ports 2529and for each substream corresponding to a single keyset. The platform should validate 2530the arguments `Ecam address` and `Rootport ID` before acting on it. The arguments `request ID` 2531and `cookie` are to be ignored for blocking mode and are pass-through to the response for 2532non-blocking mode. 2533 2534The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs. 2535Depending on the expected latency for IDE-KM interface, the platform should choose blocking 2536or non-blocking semantics. More details about IDE Setup flow can be found 2537in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_. 2538 2539The parameters of the function are: 2540 2541 arg0 - The ecam address, to access and configure PCI devices in a system. 2542 2543 arg1 - The rootport ID used to identify the PCIe rootport of a connected device. 2544 2545 arg2 - The IDE stream info associated with a physical device, this parameter packs the 2546 the keyset, direction, substream and stream ID info. 2547 2548 arg3 - Structure with key and IV info. 2549 2550 arg4 - The request ID, is used in non-blocking mode only and can be ignored in blocking mode. 2551 2552 arg5 - The cookie variable, is used in non-blocking mode only and can be ignored in blocking 2553 mode. 2554 2555The function returns E_RMM_OK on success, E_RMM_INVAL if arguments are invalid, E_RMM_FAULT 2556if the key programming is unsuccesful, E_RMM_UNK for an unknown error, E_RMM_AGAIN returned 2557only for non-blocking mode if the IDE-KM interface is busy or the request queue is full. 2558E_RMM_INPROGRESS returned if the request is queued successfully and used only in non-blocking 2559mode. 2560 2561Function : plat_rmmd_el3_ide_key_set_go() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1] 2562~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2563 2564:: 2565 2566 Argument : uint64_t, uint64_t, uint64_t, uint64_t, uint64_t 2567 Return : int 2568 2569This function activates the IDE stream at the Root Port once all the keys have been 2570programmed. The platform should validate the arguments `Ecam address` and `Rootport ID` 2571before acting on it. The arguments `request ID` and `cookie` are to be ignored for blocking 2572mode and are pass-through to the response for non-blocking mode. 2573 2574The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs. 2575Depending on the expected latency for IDE-KM interface, the platform should choose blocking 2576or non-blocking semantics. More details about IDE Setup flow can be found 2577in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_. 2578 2579The parameters of the function are: 2580 2581 arg0 - The ecam address, to access and configure PCI devices in a system. 2582 2583 arg1 - The rootport ID used to identify the PCIe rootport of a connected device. 2584 2585 arg2 - The IDE stream info associated with a physical device, this parameter packs the 2586 the keyset, direction, substream and stream ID info. 2587 2588 arg3 - The request ID, is used in non-blocking mode only and can be ignored in blocking mode. 2589 2590 arg4 - The cookie variable, is used in non-blocking mode only and can be ignored in blocking 2591 mode. 2592 2593The function returns E_RMM_OK on success, E_RMM_INVAL if arguments are invalid, E_RMM_FAULT 2594if the key programming is unsuccesful, E_RMM_UNK for an unknown error, E_RMM_AGAIN returned 2595only for non-blocking mode if the IDE-KM interface is busy or the request queue is full. 2596E_RMM_INPROGRESS returned if the request is queued successfully and used only in non-blocking 2597mode. 2598 2599Function : plat_rmmd_el3_ide_key_set_stop() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1] 2600~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2601 2602:: 2603 2604 Argument : uint64_t, uint64_t, uint64_t, uint64_t, uint64_t 2605 Return : int 2606 2607This function stops the IDE stream and is used to tear down the IDE stream at Root Port. 2608The platform should validate the arguments `Ecam address` and `Rootport ID` before acting 2609on it. The arguments `request ID` and `cookie` are to be ignored for blocking 2610mode and are pass-through to the response for non-blocking mode. 2611 2612The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs. 2613Depending on the expected latency for IDE-KM interface, the platform should choose blocking 2614or non-blocking semantics. More details about IDE Setup flow can be found 2615in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_. 2616 2617The parameters of the function are: 2618 2619 arg0 - The ecam address, to access and configure PCI devices in a system. 2620 2621 arg1 - The rootport ID used to identify the PCIe rootport of a connected device. 2622 2623 arg2 - The IDE stream info associated with a physical device, this parameter packs the 2624 the keyset, direction, substream and stream ID info. 2625 2626 arg3 - The request ID, is used in non-blocking mode only and can be ignored in blocking mode. 2627 2628 arg4 - The cookie variable, is used in non-blocking mode only and can be ignored in blocking 2629 mode. 2630 2631The function returns E_RMM_OK on success, E_RMM_INVAL if arguments are invalid, E_RMM_FAULT 2632if the key programming is unsuccesful, E_RMM_UNK for an unknown error, E_RMM_AGAIN returned 2633only for non-blocking mode if the IDE-KM interface is busy or the request queue is full. 2634E_RMM_INPROGRESS returned if the request is queued successfully and used only in non-blocking 2635mode. 2636 2637Function : plat_rmmd_el3_ide_km_pull_response() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1] 2638~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2639 2640:: 2641 2642 Argument : uint64_t, uint64_t, uint64_t *, uint64_t *, uint64_t * 2643 Return : int 2644 2645This function retrieves a reponse for any of the prior non-blocking IDE-KM requests. The 2646caller has to identify the request and populate the accurate response. For blocking calls, 2647this function always returns E_RMM_UNK. 2648 2649The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs. 2650Depending on the expected latency for IDE-KM interface, the platform should choose blocking 2651or non-blocking semantics. More details about IDE Setup flow can be found 2652in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_. 2653 2654The parameters of the function are: 2655 2656 arg0 - The ecam address, to access and configure PCI devices in a system. 2657 2658 arg1 - The rootport ID used to identify the PCIe rootport of a connected device. 2659 2660 arg2 - Retrieved response corresponding to the previous IDE_KM request. 2661 2662 arg3 - returns the passthrough request ID of the retrieved response. 2663 2664 arg4 - returns the passthrough cookie of the retrieved response. 2665 2666The function returns E_RMM_OK if response is retrieved successfully, E_RMM_INVAL if arguments 2667to this function are invalid, E_RMM_UNK if response retrieval failed for an unknown error or 2668IDE-KM interface is having blocking semantics, E_RMM_AGAIN if the response queue is empty. 2669 2670The `arg2` return parameter can return the following values: 2671E_RMM_OK - The previous request was successful. 2672E_RMM_FAULT - The previous request was not successful. 2673E_RMM_INVAL - Arguments to previous request were incorrect. 2674E_RMM_UNK - Previous request returned Unknown error. 2675 2676Function : bl31_plat_enable_mmu [optional] 2677~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2678 2679:: 2680 2681 Argument : uint32_t 2682 Return : void 2683 2684This function enables the MMU. The boot code calls this function with MMU and 2685caches disabled. This function should program necessary registers to enable 2686translation, and upon return, the MMU on the calling PE must be enabled. 2687 2688The function must honor flags passed in the first argument. These flags are 2689defined by the translation library, and can be found in the file 2690``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2691 2692On DynamIQ systems, this function must not use stack while enabling MMU, which 2693is how the function in xlat table library version 2 is implemented. 2694 2695Function : plat_init_apkey [optional] 2696~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2697 2698:: 2699 2700 Argument : void 2701 Return : uint128_t 2702 2703This function returns the 128-bit value which can be used to program ARMv8.3 2704pointer authentication keys. 2705 2706The value should be obtained from a reliable source of randomness. 2707 2708This function is only needed if ARMv8.3 pointer authentication is used in the 2709Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to 1, 2 or 3. 2710 2711Function : plat_get_syscnt_freq2() [mandatory] 2712~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2713 2714:: 2715 2716 Argument : void 2717 Return : unsigned int 2718 2719This function is used by the architecture setup code to retrieve the counter 2720frequency for the CPU's generic timer. This value will be programmed into the 2721``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2722of the system counter, which is retrieved from the first entry in the frequency 2723modes table. 2724 2725#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 2726~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2727 2728When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2729bytes) aligned to the cache line boundary that should be allocated per-cpu to 2730accommodate all the bakery locks. 2731 2732If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2733calculates the size of the ``.bakery_lock`` input section, aligns it to the 2734nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2735and stores the result in a linker symbol. This constant prevents a platform 2736from relying on the linker and provide a more efficient mechanism for 2737accessing per-cpu bakery lock information. 2738 2739If this constant is defined and its value is not equal to the value 2740calculated by the linker then a link time assertion is raised. A compile time 2741assertion is raised if the value of the constant is not aligned to the cache 2742line boundary. 2743 2744.. _porting_guide_sdei_requirements: 2745 2746SDEI porting requirements 2747~~~~~~~~~~~~~~~~~~~~~~~~~ 2748 2749The |SDEI| dispatcher requires the platform to provide the following macros 2750and functions, of which some are optional, and some others mandatory. 2751 2752Macros 2753...... 2754 2755Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2756^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2757 2758This macro must be defined to the EL3 exception priority level associated with 2759Normal |SDEI| events on the platform. This must have a higher value 2760(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2761 2762Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2763^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2764 2765This macro must be defined to the EL3 exception priority level associated with 2766Critical |SDEI| events on the platform. This must have a lower value 2767(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2768 2769**Note**: |SDEI| exception priorities must be the lowest among Secure 2770priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must 2771be higher than Normal |SDEI| priority. 2772 2773Functions 2774......... 2775 2776Function: int plat_sdei_validate_entry_point() [optional] 2777^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2778 2779:: 2780 2781 Argument: uintptr_t ep, unsigned int client_mode 2782 Return: int 2783 2784This function validates the entry point address of the event handler provided by 2785the client for both event registration and *Complete and Resume* |SDEI| calls. 2786The function ensures that the address is valid in the client translation regime. 2787 2788The second argument is the exception level that the client is executing in. It 2789can be Non-Secure EL1 or Non-Secure EL2. 2790 2791The function must return ``0`` for successful validation, or ``-1`` upon failure. 2792 2793The default implementation always returns ``0``. On Arm platforms, this function 2794translates the entry point address within the client translation regime and 2795further ensures that the resulting physical address is located in Non-secure 2796DRAM. 2797 2798Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2799^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2800 2801:: 2802 2803 Argument: uint64_t 2804 Argument: unsigned int 2805 Return: void 2806 2807|SDEI| specification requires that a PE comes out of reset with the events 2808masked. The client therefore is expected to call ``PE_UNMASK`` to unmask 2809|SDEI| events on the PE. No |SDEI| events can be dispatched until such 2810time. 2811 2812Should a PE receive an interrupt that was bound to an |SDEI| event while the 2813events are masked on the PE, the dispatcher implementation invokes the function 2814``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2815interrupt and the interrupt ID are passed as parameters. 2816 2817The default implementation only prints out a warning message. 2818 2819.. _porting_guide_trng_requirements: 2820 2821TRNG porting requirements 2822~~~~~~~~~~~~~~~~~~~~~~~~~ 2823 2824The |TRNG| backend requires the platform to provide the following values 2825and mandatory functions. 2826 2827Values 2828...... 2829 2830value: uuid_t plat_trng_uuid [mandatory] 2831^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2832 2833This value must be defined to the UUID of the TRNG backend that is specific to 2834the hardware after ``plat_entropy_setup`` function is called. This value must 2835conform to the SMCCC calling convention; The most significant 32 bits of the 2836UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in 2837w0 indicates failure to get a TRNG source. 2838 2839Functions 2840......... 2841 2842Function: void plat_entropy_setup(void) [mandatory] 2843^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2844 2845:: 2846 2847 Argument: none 2848 Return: none 2849 2850This function is expected to do platform-specific initialization of any TRNG 2851hardware. This may include generating a UUID from a hardware-specific seed. 2852 2853Function: bool plat_get_entropy(uint64_t \*out) [mandatory] 2854^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2855 2856:: 2857 2858 Argument: uint64_t * 2859 Return: bool 2860 Out : when the return value is true, the entropy has been written into the 2861 storage pointed to 2862 2863This function writes entropy into storage provided by the caller. If no entropy 2864is available, it must return false and the storage must not be written. 2865 2866.. _psci_in_bl31: 2867 2868Power State Coordination Interface (in BL31) 2869-------------------------------------------- 2870 2871The TF-A implementation of the PSCI API is based around the concept of a 2872*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2873share some state on which power management operations can be performed as 2874specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2875a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2876*power domains* are arranged in a hierarchical tree structure and each 2877*power domain* can be identified in a system by the cpu index of any CPU that 2878is part of that domain and a *power domain level*. A processing element (for 2879example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2880logical grouping of CPUs that share some state, then level 1 is that group of 2881CPUs (for example, a cluster), and level 2 is a group of clusters (for 2882example, the system). More details on the power domain topology and its 2883organization can be found in :ref:`PSCI Power Domain Tree Structure`. 2884 2885BL31's platform initialization code exports a pointer to the platform-specific 2886power management operations required for the PSCI implementation to function 2887correctly. This information is populated in the ``plat_psci_ops`` structure. The 2888PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2889power management operations on the power domains. For example, the target 2890CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2891handler (if present) is called for the CPU power domain. 2892 2893The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2894describe composite power states specific to a platform. The PSCI implementation 2895defines a generic representation of the power-state parameter, which is an 2896array of local power states where each index corresponds to a power domain 2897level. Each entry contains the local power state the power domain at that power 2898level could enter. It depends on the ``validate_power_state()`` handler to 2899convert the power-state parameter (possibly encoding a composite power state) 2900passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2901 2902The following functions form part of platform port of PSCI functionality. 2903 2904Function : plat_psci_stat_accounting_start() [optional] 2905~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2906 2907:: 2908 2909 Argument : const psci_power_state_t * 2910 Return : void 2911 2912This is an optional hook that platforms can implement for residency statistics 2913accounting before entering a low power state. The ``pwr_domain_state`` field of 2914``state_info`` (first argument) can be inspected if stat accounting is done 2915differently at CPU level versus higher levels. As an example, if the element at 2916index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2917state, special hardware logic may be programmed in order to keep track of the 2918residency statistics. For higher levels (array indices > 0), the residency 2919statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2920default implementation will use PMF to capture timestamps. 2921 2922Function : plat_psci_stat_accounting_stop() [optional] 2923~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2924 2925:: 2926 2927 Argument : const psci_power_state_t * 2928 Return : void 2929 2930This is an optional hook that platforms can implement for residency statistics 2931accounting after exiting from a low power state. The ``pwr_domain_state`` field 2932of ``state_info`` (first argument) can be inspected if stat accounting is done 2933differently at CPU level versus higher levels. As an example, if the element at 2934index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2935state, special hardware logic may be programmed in order to keep track of the 2936residency statistics. For higher levels (array indices > 0), the residency 2937statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2938default implementation will use PMF to capture timestamps. 2939 2940Function : plat_psci_stat_get_residency() [optional] 2941~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2942 2943:: 2944 2945 Argument : unsigned int, const psci_power_state_t *, unsigned int 2946 Return : u_register_t 2947 2948This is an optional interface that is is invoked after resuming from a low power 2949state and provides the time spent resident in that low power state by the power 2950domain at a particular power domain level. When a CPU wakes up from suspend, 2951all its parent power domain levels are also woken up. The generic PSCI code 2952invokes this function for each parent power domain that is resumed and it 2953identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2954argument) describes the low power state that the power domain has resumed from. 2955The current CPU is the first CPU in the power domain to resume from the low 2956power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2957CPU in the power domain to suspend and may be needed to calculate the residency 2958for that power domain. 2959 2960Function : plat_get_target_pwr_state() [optional] 2961~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2962 2963:: 2964 2965 Argument : unsigned int, const plat_local_state_t *, unsigned int 2966 Return : plat_local_state_t 2967 2968The PSCI generic code uses this function to let the platform participate in 2969state coordination during a power management operation. The function is passed 2970a pointer to an array of platform specific local power state ``states`` (second 2971argument) which contains the requested power state for each CPU at a particular 2972power domain level ``lvl`` (first argument) within the power domain. The function 2973is expected to traverse this array of upto ``ncpus`` (third argument) and return 2974a coordinated target power state by the comparing all the requested power 2975states. The target power state should not be deeper than any of the requested 2976power states. 2977 2978A weak definition of this API is provided by default wherein it assumes 2979that the platform assigns a local state value in order of increasing depth 2980of the power state i.e. for two power states X & Y, if X < Y 2981then X represents a shallower power state than Y. As a result, the 2982coordinated target local power state for a power domain will be the minimum 2983of the requested local power state values. 2984 2985Function : plat_get_power_domain_tree_desc() [mandatory] 2986~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2987 2988:: 2989 2990 Argument : void 2991 Return : const unsigned char * 2992 2993This function returns a pointer to the byte array containing the power domain 2994topology tree description. The format and method to construct this array are 2995described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI 2996initialization code requires this array to be described by the platform, either 2997statically or dynamically, to initialize the power domain topology tree. In case 2998the array is populated dynamically, then plat_core_pos_by_mpidr() and 2999plat_my_core_pos() should also be implemented suitably so that the topology tree 3000description matches the CPU indices returned by these APIs. These APIs together 3001form the platform interface for the PSCI topology framework. 3002 3003Function : plat_setup_psci_ops() [mandatory] 3004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3005 3006:: 3007 3008 Argument : uintptr_t, const plat_psci_ops ** 3009 Return : int 3010 3011This function may execute with the MMU and data caches enabled if the platform 3012port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 3013called by the primary CPU. 3014 3015This function is called by PSCI initialization code. Its purpose is to let 3016the platform layer know about the warm boot entrypoint through the 3017``sec_entrypoint`` (first argument) and to export handler routines for 3018platform-specific psci power management actions by populating the passed 3019pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 3020 3021A description of each member of this structure is given below. Please refer to 3022the Arm FVP specific implementation of these handlers in 3023``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the 3024platform wants to support, the associated operation or operations in this 3025structure must be provided and implemented (Refer section 4 of 3026:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI 3027function in a platform port, the operation should be removed from this 3028structure instead of providing an empty implementation. 3029 3030plat_psci_ops.cpu_standby() 3031........................... 3032 3033Perform the platform-specific actions to enter the standby state for a cpu 3034indicated by the passed argument. This provides a fast path for CPU standby 3035wherein overheads of PSCI state management and lock acquisition is avoided. 3036For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 3037the suspend state type specified in the ``power-state`` parameter should be 3038STANDBY and the target power domain level specified should be the CPU. The 3039handler should put the CPU into a low power retention state (usually by 3040issuing a wfi instruction) and ensure that it can be woken up from that 3041state by a normal interrupt. The generic code expects the handler to succeed. 3042 3043plat_psci_ops.pwr_domain_on() 3044............................. 3045 3046Perform the platform specific actions to power on a CPU, specified 3047by the ``MPIDR`` (first argument). The generic code expects the platform to 3048return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 3049 3050plat_psci_ops.pwr_domain_off_early() [optional] 3051............................................... 3052 3053This optional function performs the platform specific actions to check if 3054powering off the calling CPU and its higher parent power domain levels as 3055indicated by the ``target_state`` (first argument) is possible or allowed. 3056 3057The ``target_state`` encodes the platform coordinated target local power states 3058for the CPU power domain and its parent power domain levels. 3059 3060For this handler, the local power state for the CPU power domain will be a 3061power down state where as it could be either power down, retention or run state 3062for the higher power domain levels depending on the result of state 3063coordination. The generic code expects PSCI_E_DENIED return code if the 3064platform thinks that CPU_OFF should not proceed on the calling CPU. 3065 3066plat_psci_ops.pwr_domain_off() 3067.............................. 3068 3069Perform the platform specific actions to prepare to power off the calling CPU 3070and its higher parent power domain levels as indicated by the ``target_state`` 3071(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 3072 3073The ``target_state`` encodes the platform coordinated target local power states 3074for the CPU power domain and its parent power domain levels. The handler 3075needs to perform power management operation corresponding to the local state 3076at each power level. 3077 3078For this handler, the local power state for the CPU power domain will be a 3079power down state where as it could be either power down, retention or run state 3080for the higher power domain levels depending on the result of state 3081coordination. The generic code expects the handler to succeed. 3082 3083plat_psci_ops.pwr_domain_validate_suspend() [optional] 3084...................................................... 3085 3086This is an optional function that is only compiled into the build if the build 3087option ``PSCI_OS_INIT_MODE`` is enabled. 3088 3089If implemented, this function allows the platform to perform platform specific 3090validations based on hardware states. The generic code expects this function to 3091return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or 3092PSCI_E_INVALID_PARAMS as appropriate for any invalid requests. 3093 3094plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 3095........................................................... 3096 3097This optional function may be used as a performance optimization to replace 3098or complement pwr_domain_suspend() on some platforms. Its calling semantics 3099are identical to pwr_domain_suspend(), except the PSCI implementation only 3100calls this function when suspending to a power down state, and it guarantees 3101that data caches are enabled. 3102 3103When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 3104before calling pwr_domain_suspend(). If the target_state corresponds to a 3105power down state and it is safe to perform some or all of the platform 3106specific actions in that function with data caches enabled, it may be more 3107efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 3108= 1, data caches remain enabled throughout, and so there is no advantage to 3109moving platform specific actions to this function. 3110 3111plat_psci_ops.pwr_domain_suspend() 3112.................................. 3113 3114Perform the platform specific actions to prepare to suspend the calling 3115CPU and its higher parent power domain levels as indicated by the 3116``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 3117API implementation. 3118 3119The ``target_state`` has a similar meaning as described in 3120the ``pwr_domain_off()`` operation. It encodes the platform coordinated 3121target local power states for the CPU power domain and its parent 3122power domain levels. The handler needs to perform power management operation 3123corresponding to the local state at each power level. The generic code 3124expects the handler to succeed. 3125 3126The difference between turning a power domain off versus suspending it is that 3127in the former case, the power domain is expected to re-initialize its state 3128when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 3129case, the power domain is expected to save enough state so that it can resume 3130execution by restoring this state when its powered on (see 3131``pwr_domain_suspend_finish()``). 3132 3133When suspending a core, the platform can also choose to power off the GICv3 3134Redistributor and ITS through an implementation-defined sequence. To achieve 3135this safely, the ITS context must be saved first. The architectural part is 3136implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 3137sequence is implementation defined and it is therefore the responsibility of 3138the platform code to implement the necessary sequence. Then the GIC 3139Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 3140Powering off the Redistributor requires the implementation to support it and it 3141is the responsibility of the platform code to execute the right implementation 3142defined sequence. 3143 3144When a system suspend is requested, the platform can also make use of the 3145``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 3146it has saved the context of the Redistributors and ITS of all the cores in the 3147system. The context of the Distributor can be large and may require it to be 3148allocated in a special area if it cannot fit in the platform's global static 3149data, for example in DRAM. The Distributor can then be powered down using an 3150implementation-defined sequence. 3151 3152plat_psci_ops.pwr_domain_pwr_down() 3153....................................... 3154 3155This is an optional function and, if implemented, is expected to perform 3156platform specific actions before the CPU is powered down. Since this function is 3157invoked outside the PSCI locks, the actions performed in this hook must be local 3158to the CPU or the platform must ensure that races between multiple CPUs cannot 3159occur. 3160 3161The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 3162operation and it encodes the platform coordinated target local power states for 3163the CPU power domain and its parent power domain levels. 3164 3165It is preferred that this function returns. The caller will invoke 3166``wfi()`` to powerdown the CPU, mitigate any powerdown errata, 3167and handle any wakeups that may arise. Previously, this function did not return 3168and instead called ``wfi`` (in an infinite loop) directly. This is still 3169possible on platforms where this is guaranteed to be terminal, however, it is 3170strongly discouraged going forward. 3171 3172Previously this function was called ``pwr_domain_pwr_down_wfi()`` and invoked 3173``psci_power_down_wfi()`` (now removed). 3174 3175plat_psci_ops.pwr_domain_on_finish() 3176.................................... 3177 3178This function is called by the PSCI implementation after the calling CPU is 3179powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 3180It performs the platform-specific setup required to initialize enough state for 3181this CPU to enter the normal world and also provide secure runtime firmware 3182services. 3183 3184The ``target_state`` (first argument) is the prior state of the power domains 3185immediately before the CPU was turned on. It indicates which power domains 3186above the CPU might require initialization due to having previously been in 3187low power states. The generic code expects the handler to succeed. 3188 3189plat_psci_ops.pwr_domain_on_finish_late() [optional] 3190........................................................... 3191 3192This optional function is called by the PSCI implementation after the calling 3193CPU is fully powered on with respective data caches enabled. The calling CPU and 3194the associated cluster are guaranteed to be participating in coherency. This 3195function gives the flexibility to perform any platform-specific actions safely, 3196such as initialization or modification of shared data structures, without the 3197overhead of explicit cache maintainace operations. 3198 3199The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` 3200operation. The generic code expects the handler to succeed. 3201 3202plat_psci_ops.pwr_domain_suspend_finish() 3203......................................... 3204 3205This function is called by the PSCI implementation after the calling CPU is 3206powered on and released from reset in response to an asynchronous wakeup 3207event, for example a timer interrupt that was programmed by the CPU during the 3208``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 3209setup required to restore the saved state for this CPU to resume execution 3210in the normal world and also provide secure runtime firmware services. 3211 3212The ``target_state`` (first argument) has a similar meaning as described in 3213the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 3214to succeed. 3215 3216If the Distributor, Redistributors or ITS have been powered off as part of a 3217suspend, their context must be restored in this function in the reverse order 3218to how they were saved during suspend sequence. 3219 3220plat_psci_ops.system_off() 3221.......................... 3222 3223This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 3224call. It performs the platform-specific system poweroff sequence after 3225notifying the Secure Payload Dispatcher. The caller will call ``wfi`` if this 3226function returns, similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 3227 3228plat_psci_ops.system_reset() 3229............................ 3230 3231This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 3232call. It performs the platform-specific system reset sequence after 3233notifying the Secure Payload Dispatcher. The caller will call ``wfi`` if this 3234function returns, similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 3235 3236plat_psci_ops.validate_power_state() 3237.................................... 3238 3239This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 3240call to validate the ``power_state`` parameter of the PSCI API and if valid, 3241populate it in ``req_state`` (second argument) array as power domain level 3242specific local states. If the ``power_state`` is invalid, the platform must 3243return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 3244normal world PSCI client. 3245 3246plat_psci_ops.validate_ns_entrypoint() 3247...................................... 3248 3249This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 3250``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 3251parameter passed by the normal world. If the ``entry_point`` is invalid, 3252the platform must return PSCI_E_INVALID_ADDRESS as error, which is 3253propagated back to the normal world PSCI client. 3254 3255plat_psci_ops.get_sys_suspend_power_state() 3256........................................... 3257 3258This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 3259call to get the ``req_state`` parameter from platform which encodes the power 3260domain level specific local states to suspend to system affinity level. The 3261``req_state`` will be utilized to do the PSCI state coordination and 3262``pwr_domain_suspend()`` will be invoked with the coordinated target state to 3263enter system suspend. 3264 3265plat_psci_ops.get_pwr_lvl_state_idx() 3266..................................... 3267 3268This is an optional function and, if implemented, is invoked by the PSCI 3269implementation to convert the ``local_state`` (first argument) at a specified 3270``pwr_lvl`` (second argument) to an index between 0 and 3271``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 3272supports more than two local power states at each power domain level, that is 3273``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 3274local power states. 3275 3276plat_psci_ops.translate_power_state_by_mpidr() 3277.............................................. 3278 3279This is an optional function and, if implemented, verifies the ``power_state`` 3280(second argument) parameter of the PSCI API corresponding to a target power 3281domain. The target power domain is identified by using both ``MPIDR`` (first 3282argument) and the power domain level encoded in ``power_state``. The power domain 3283level specific local states are to be extracted from ``power_state`` and be 3284populated in the ``output_state`` (third argument) array. The functionality 3285is similar to the ``validate_power_state`` function described above and is 3286envisaged to be used in case the validity of ``power_state`` depend on the 3287targeted power domain. If the ``power_state`` is invalid for the targeted power 3288domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 3289function is not implemented, then the generic implementation relies on 3290``validate_power_state`` function to translate the ``power_state``. 3291 3292This function can also be used in case the platform wants to support local 3293power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 3294APIs as described in Section 5.18 of `PSCI`_. 3295 3296plat_psci_ops.get_node_hw_state() 3297................................. 3298 3299This is an optional function. If implemented this function is intended to return 3300the power state of a node (identified by the first parameter, the ``MPIDR``) in 3301the power domain topology (identified by the second parameter, ``power_level``), 3302as retrieved from a power controller or equivalent component on the platform. 3303Upon successful completion, the implementation must map and return the final 3304status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 3305must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 3306appropriate. 3307 3308Implementations are not expected to handle ``power_levels`` greater than 3309``PLAT_MAX_PWR_LVL``. 3310 3311plat_psci_ops.system_reset2() 3312............................. 3313 3314This is an optional function. If implemented this function is 3315called during the ``SYSTEM_RESET2`` call to perform a reset 3316based on the first parameter ``reset_type`` as specified in 3317`PSCI`_. The parameter ``cookie`` can be used to pass additional 3318reset information. If the ``reset_type`` is not supported, the 3319function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 3320resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 3321and vendor reset can return other PSCI error codes as defined 3322in `PSCI`_. If this function returns success, the caller will call 3323``wfi`` similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 3324 3325plat_psci_ops.write_mem_protect() 3326................................. 3327 3328This is an optional function. If implemented it enables or disables the 3329``MEM_PROTECT`` functionality based on the value of ``val``. 3330A non-zero value enables ``MEM_PROTECT`` and a value of zero 3331disables it. Upon encountering failures it must return a negative value 3332and on success it must return 0. 3333 3334plat_psci_ops.read_mem_protect() 3335................................ 3336 3337This is an optional function. If implemented it returns the current 3338state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 3339failures it must return a negative value and on success it must 3340return 0. 3341 3342plat_psci_ops.mem_protect_chk() 3343............................... 3344 3345This is an optional function. If implemented it checks if a memory 3346region defined by a base address ``base`` and with a size of ``length`` 3347bytes is protected by ``MEM_PROTECT``. If the region is protected 3348then it must return 0, otherwise it must return a negative number. 3349 3350.. _porting_guide_imf_in_bl31: 3351 3352Interrupt Management framework (in BL31) 3353---------------------------------------- 3354 3355BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 3356generated in either security state and targeted to EL1 or EL2 in the non-secure 3357state or EL3/S-EL1 in the secure state. The design of this framework is 3358described in the :ref:`Interrupt Management Framework` 3359 3360A platform should export the following APIs to support the IMF. The following 3361text briefly describes each API and its implementation in Arm standard 3362platforms. The API implementation depends upon the type of interrupt controller 3363present in the platform. Arm standard platform layer supports both 3364`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 3365and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 3366FVP can be configured to use either GICv2 or GICv3 depending on the build flag 3367``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more 3368details). 3369 3370See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. 3371 3372Function : plat_interrupt_type_to_line() [mandatory] 3373~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3374 3375:: 3376 3377 Argument : uint32_t, uint32_t 3378 Return : uint32_t 3379 3380The Arm processor signals an interrupt exception either through the IRQ or FIQ 3381interrupt line. The specific line that is signaled depends on how the interrupt 3382controller (IC) reports different interrupt types from an execution context in 3383either security state. The IMF uses this API to determine which interrupt line 3384the platform IC uses to signal each type of interrupt supported by the framework 3385from a given security state. This API must be invoked at EL3. 3386 3387The first parameter will be one of the ``INTR_TYPE_*`` values (see 3388:ref:`Interrupt Management Framework`) indicating the target type of the 3389interrupt, the second parameter is the security state of the originating 3390execution context. The return result is the bit position in the ``SCR_EL3`` 3391register of the respective interrupt trap: IRQ=1, FIQ=2. 3392 3393In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 3394configured as FIQs and Non-secure interrupts as IRQs from either security 3395state. 3396 3397In the case of Arm standard platforms using GICv3, the interrupt line to be 3398configured depends on the security state of the execution context when the 3399interrupt is signalled and are as follows: 3400 3401- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 3402 NS-EL0/1/2 context. 3403- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 3404 in the NS-EL0/1/2 context. 3405- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 3406 context. 3407 3408Function : plat_ic_get_pending_interrupt_type() [mandatory] 3409~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3410 3411:: 3412 3413 Argument : void 3414 Return : uint32_t 3415 3416This API returns the type of the highest priority pending interrupt at the 3417platform IC. The IMF uses the interrupt type to retrieve the corresponding 3418handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 3419pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 3420``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 3421 3422In the case of Arm standard platforms using GICv2, the *Highest Priority 3423Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 3424the pending interrupt. The type of interrupt depends upon the id value as 3425follows. 3426 3427#. id < 1022 is reported as a S-EL1 interrupt 3428#. id = 1022 is reported as a Non-secure interrupt. 3429#. id = 1023 is reported as an invalid interrupt type. 3430 3431In the case of Arm standard platforms using GICv3, the system register 3432``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 3433is read to determine the id of the pending interrupt. The type of interrupt 3434depends upon the id value as follows. 3435 3436#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 3437#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 3438#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 3439#. All other interrupt id's are reported as EL3 interrupt. 3440 3441Function : plat_ic_get_pending_interrupt_id() [mandatory] 3442~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3443 3444:: 3445 3446 Argument : void 3447 Return : uint32_t 3448 3449This API returns the id of the highest priority pending interrupt at the 3450platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 3451pending. 3452 3453In the case of Arm standard platforms using GICv2, the *Highest Priority 3454Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 3455pending interrupt. The id that is returned by API depends upon the value of 3456the id read from the interrupt controller as follows. 3457 3458#. id < 1022. id is returned as is. 3459#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 3460 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 3461 This id is returned by the API. 3462#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 3463 3464In the case of Arm standard platforms using GICv3, if the API is invoked from 3465EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 3466group 0 Register*, is read to determine the id of the pending interrupt. The id 3467that is returned by API depends upon the value of the id read from the 3468interrupt controller as follows. 3469 3470#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 3471#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 3472 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 3473 Register* is read to determine the id of the group 1 interrupt. This id 3474 is returned by the API as long as it is a valid interrupt id 3475#. If the id is any of the special interrupt identifiers, 3476 ``INTR_ID_UNAVAILABLE`` is returned. 3477 3478When the API invoked from S-EL1 for GICv3 systems, the id read from system 3479register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 3480Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 3481``INTR_ID_UNAVAILABLE`` is returned. 3482 3483Function : plat_ic_acknowledge_interrupt() [mandatory] 3484~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3485 3486:: 3487 3488 Argument : void 3489 Return : uint32_t 3490 3491This API is used by the CPU to indicate to the platform IC that processing of 3492the highest pending interrupt has begun. It should return the raw, unmodified 3493value obtained from the interrupt controller when acknowledging an interrupt. 3494The actual interrupt number shall be extracted from this raw value using the API 3495`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. 3496 3497This function in Arm standard platforms using GICv2, reads the *Interrupt 3498Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 3499priority pending interrupt from pending to active in the interrupt controller. 3500It returns the value read from the ``GICC_IAR``, unmodified. 3501 3502In the case of Arm standard platforms using GICv3, if the API is invoked 3503from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 3504Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 3505reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 3506group 1*. The read changes the state of the highest pending interrupt from 3507pending to active in the interrupt controller. The value read is returned 3508unmodified. 3509 3510The TSP uses this API to start processing of the secure physical timer 3511interrupt. 3512 3513Function : plat_ic_end_of_interrupt() [mandatory] 3514~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3515 3516:: 3517 3518 Argument : uint32_t 3519 Return : void 3520 3521This API is used by the CPU to indicate to the platform IC that processing of 3522the interrupt corresponding to the id (passed as the parameter) has 3523finished. The id should be the same as the id returned by the 3524``plat_ic_acknowledge_interrupt()`` API. 3525 3526Arm standard platforms write the id to the *End of Interrupt Register* 3527(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 3528system register in case of GICv3 depending on where the API is invoked from, 3529EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 3530controller. 3531 3532The TSP uses this API to finish processing of the secure physical timer 3533interrupt. 3534 3535Function : plat_ic_get_interrupt_type() [mandatory] 3536~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3537 3538:: 3539 3540 Argument : uint32_t 3541 Return : uint32_t 3542 3543This API returns the type of the interrupt id passed as the parameter. 3544``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 3545interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 3546returned depending upon how the interrupt has been configured by the platform 3547IC. This API must be invoked at EL3. 3548 3549Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 3550and Non-secure interrupts as Group1 interrupts. It reads the group value 3551corresponding to the interrupt id from the relevant *Interrupt Group Register* 3552(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 3553 3554In the case of Arm standard platforms using GICv3, both the *Interrupt Group 3555Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 3556(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 3557as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 3558 3559Registering a console 3560--------------------- 3561 3562Platforms will need to implement the TF-A console framework to register and use 3563a console for visual data output in TF-A. These can be used for data output during 3564the different stages of the firmware boot process and also for debugging purposes. 3565 3566The console framework can be used to output data on to a console using a number of 3567TF-A supported UARTs. Multiple consoles can be registered at the same time with 3568different output scopes (BOOT, RUNTIME, CRASH) so that data can be displayed on 3569their respective consoles without unnecessary cluttering of a single console. 3570 3571Information for registering a console can be found in the :ref:`Console Framework` section 3572of the :ref:`System Design` documentation. 3573 3574Common helper functions 3575----------------------- 3576Function : elx_panic() 3577~~~~~~~~~~~~~~~~~~~~~~ 3578 3579:: 3580 3581 Argument : void 3582 Return : void 3583 3584This API is called from assembly files when reporting a critical failure 3585that has occured in lower EL and is been trapped in EL3. This call 3586**must not** return. 3587 3588Function : el3_panic() 3589~~~~~~~~~~~~~~~~~~~~~~ 3590 3591:: 3592 3593 Argument : void 3594 Return : void 3595 3596This API is called from assembly files when encountering a critical failure that 3597cannot be recovered from. This function assumes that it is invoked from a C 3598runtime environment i.e. valid stack exists. This call **must not** return. 3599 3600Function : panic() 3601~~~~~~~~~~~~~~~~~~ 3602 3603:: 3604 3605 Argument : void 3606 Return : void 3607 3608This API called from C files when encountering a critical failure that cannot 3609be recovered from. This function in turn prints backtrace (if enabled) and calls 3610el3_panic(). This call **must not** return. 3611 3612Crash Reporting mechanism (in BL31) 3613----------------------------------- 3614 3615BL31 implements a crash reporting mechanism which prints the various registers 3616of the CPU to enable quick crash analysis and debugging. This mechanism relies 3617on the platform implementing ``plat_crash_console_init``, 3618``plat_crash_console_putc`` and ``plat_crash_console_flush``. 3619 3620The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 3621implementation of all of them. Platforms may include this file to their 3622makefiles in order to benefit from them. By default, they will cause the crash 3623output to be routed over the normal console infrastructure and get printed on 3624consoles configured to output in crash state. ``console_set_scope()`` can be 3625used to control whether a console is used for crash output. 3626 3627.. note:: 3628 Platforms are responsible for making sure that they only mark consoles for 3629 use in the crash scope that are able to support this, i.e. that are written 3630 in assembly and conform with the register clobber rules for putc() 3631 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. 3632 3633In some cases (such as debugging very early crashes that happen before the 3634normal boot console can be set up), platforms may want to control crash output 3635more explicitly. These platforms may instead provide custom implementations for 3636these. They are executed outside of a C environment and without a stack. Many 3637console drivers provide functions named ``console_xxx_core_init/putc/flush`` 3638that are designed to be used by these functions. See Arm platforms (like juno) 3639for an example of this. 3640 3641Function : plat_crash_console_init [mandatory] 3642~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3643 3644:: 3645 3646 Argument : void 3647 Return : int 3648 3649This API is used by the crash reporting mechanism to initialize the crash 3650console. It must only use the general purpose registers x0 through x7 to do the 3651initialization and returns 1 on success. 3652 3653Function : plat_crash_console_putc [mandatory] 3654~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3655 3656:: 3657 3658 Argument : int 3659 Return : int 3660 3661This API is used by the crash reporting mechanism to print a character on the 3662designated crash console. It must only use general purpose registers x1 and 3663x2 to do its work. The parameter and the return value are in general purpose 3664register x0. 3665 3666Function : plat_crash_console_flush [mandatory] 3667~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3668 3669:: 3670 3671 Argument : void 3672 Return : void 3673 3674This API is used by the crash reporting mechanism to force write of all buffered 3675data on the designated crash console. It should only use general purpose 3676registers x0 through x5 to do its work. 3677 3678Function : plat_setup_early_console [optional] 3679~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3680 3681:: 3682 3683 Argument : void 3684 Return : void 3685 3686This API is used to setup the early console, it is required only if the flag 3687``EARLY_CONSOLE`` is enabled. 3688 3689.. _External Abort handling and RAS Support: 3690 3691External Abort handling and RAS Support 3692--------------------------------------- 3693 3694If any cores on the platform support powerdown abandon (check the "Core powerup 3695and powerdown sequence" in their TRMs), then 3696these functions should be able to handle being called with power domains off and 3697after the powerdown ``wfi``. In other words it may run after a call to 3698``pwr_domain_suspend()`` and before a call to ``pwr_domain_suspend_finish()`` 3699(and their power off counterparts). 3700 3701Should this not be desirable, or if there is no powerdown abandon support, then 3702RAS errors should be masked by writing any relevant error records in any 3703powerdown hooks to prevent deadlocks due to a RAS error after the point of no 3704return. See the core's TRM for further information. 3705 3706Function : plat_ea_handler 3707~~~~~~~~~~~~~~~~~~~~~~~~~~ 3708 3709:: 3710 3711 Argument : int 3712 Argument : uint64_t 3713 Argument : void * 3714 Argument : void * 3715 Argument : uint64_t 3716 Return : void 3717 3718This function is invoked by the runtime exception handling framework for the 3719platform to handle an External Abort received at EL3. The intention of the 3720function is to attempt to resolve the cause of External Abort and return; 3721if that's not possible then an orderly shutdown of the system is initiated. 3722 3723The first parameter (``int ea_reason``) indicates the reason for External Abort. 3724Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 3725 3726The second parameter (``uint64_t syndrome``) is the respective syndrome 3727presented to EL3 after having received the External Abort. Depending on the 3728nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 3729can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 3730 3731The third parameter (``void *cookie``) is unused for now. The fourth parameter 3732(``void *handle``) is a pointer to the preempted context. The fifth parameter 3733(``uint64_t flags``) indicates the preempted security state. These parameters 3734are received from the top-level exception handler. 3735 3736This function must be implemented if a platform expects Firmware First handling 3737of External Aborts. 3738 3739Function : plat_handle_uncontainable_ea 3740~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3741 3742:: 3743 3744 Argument : int 3745 Argument : uint64_t 3746 Return : void 3747 3748This function is invoked by the RAS framework when an External Abort of 3749Uncontainable type is received at EL3. Due to the critical nature of 3750Uncontainable errors, the intention of this function is to initiate orderly 3751shutdown of the system, and is not expected to return. 3752 3753This function must be implemented in assembly. 3754 3755The first and second parameters are the same as that of ``plat_ea_handler``. 3756 3757The default implementation of this function calls 3758``report_unhandled_exception``. 3759 3760Function : plat_handle_double_fault 3761~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3762 3763:: 3764 3765 Argument : int 3766 Argument : uint64_t 3767 Return : void 3768 3769This function is invoked by the RAS framework when another External Abort is 3770received at EL3 while one is already being handled. I.e., a call to 3771``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 3772this function is to initiate orderly shutdown of the system, and is not expected 3773recover or return. 3774 3775This function must be implemented in assembly. 3776 3777The first and second parameters are the same as that of ``plat_ea_handler``. 3778 3779The default implementation of this function calls 3780``report_unhandled_exception``. 3781 3782Function : plat_handle_el3_ea 3783~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3784 3785:: 3786 3787 Return : void 3788 3789This function is invoked when an External Abort is received while executing in 3790EL3. Due to its critical nature, the intention of this function is to initiate 3791orderly shutdown of the system, and is not expected recover or return. 3792 3793This function must be implemented in assembly. 3794 3795The default implementation of this function calls 3796``report_unhandled_exception``. 3797 3798Function : plat_handle_rng_trap 3799~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3800 3801:: 3802 3803 Argument : uint64_t 3804 Argument : cpu_context_t * 3805 Return : int 3806 3807This function is invoked by BL31's exception handler when there is a synchronous 3808system register trap caused by access to the RNDR or RNDRRS registers. It allows 3809platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to 3810emulate those system registers by returing back some entropy to the lower EL. 3811 3812The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3813syndrome register, which encodes the instruction that was trapped. The interesting 3814information in there is the target register (``get_sysreg_iss_rt()``). 3815 3816The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3817lower exception level, at the time when the execution of the ``mrs`` instruction 3818was trapped. Its content can be changed, to put the entropy into the target 3819register. 3820 3821The return value indicates how to proceed: 3822 3823- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3824- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3825 to the same instruction, so its execution will be repeated. 3826- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3827 to the next instruction. 3828 3829This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP. 3830 3831Function : plat_handle_impdef_trap 3832~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3833 3834:: 3835 3836 Argument : uint64_t 3837 Argument : cpu_context_t * 3838 Return : int 3839 3840This function is invoked by BL31's exception handler when there is a synchronous 3841system register trap caused by access to the implementation defined registers. 3842It allows platforms enabling ``IMPDEF_SYSREG_TRAP`` to emulate those system 3843registers choosing to program bits of their choice. If using in combination with 3844``ARCH_FEATURE_AVAILABILITY``, the macros 3845{SCR,MDCR,CPTR}_PLAT_{BITS,IGNORED,FLIPPED} should be defined to report correct 3846results. 3847 3848The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3849syndrome register, which encodes the instruction that was trapped. 3850 3851The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3852lower exception level, at the time when the execution of the ``mrs`` instruction 3853was trapped. 3854 3855The return value indicates how to proceed: 3856 3857- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3858- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3859 to the same instruction, so its execution will be repeated. 3860- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3861 to the next instruction. 3862 3863This function needs to be implemented by a platform if it enables 3864IMPDEF_SYSREG_TRAP. 3865 3866Build flags 3867----------- 3868 3869There are some build flags which can be defined by the platform to control 3870inclusion or exclusion of certain BL stages from the FIP image. These flags 3871need to be defined in the platform makefile which will get included by the 3872build system. 3873 3874- **NEED_BL33** 3875 By default, this flag is defined ``yes`` by the build system and ``BL33`` 3876 build option should be supplied as a build option. The platform has the 3877 option of excluding the BL33 image in the ``fip`` image by defining this flag 3878 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 3879 are used, this flag will be set to ``no`` automatically. 3880 3881- **ARM_ARCH_MAJOR and ARM_ARCH_MINOR** 3882 By default, ARM_ARCH_MAJOR.ARM_ARCH_MINOR is set to 8.0 in ``defaults.mk``, 3883 if the platform makefile/build defines or uses the correct ARM_ARCH_MAJOR and 3884 ARM_ARCH_MINOR then mandatory Architectural features available for that Arch 3885 version will be enabled by default and any optional Arch feature supported by 3886 the Architecture and available in TF-A can be enabled from platform specific 3887 makefile. Look up to ``arch_features.mk`` for details pertaining to mandatory 3888 and optional Arch specific features. 3889 3890Platform include paths 3891---------------------- 3892 3893Platforms are allowed to add more include paths to be passed to the compiler. 3894The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in 3895particular for the file ``platform_def.h``. 3896 3897Example: 3898 3899.. code:: c 3900 3901 PLAT_INCLUDES += -Iinclude/plat/myplat/include 3902 3903C Library 3904--------- 3905 3906To avoid subtle toolchain behavioral dependencies, the header files provided 3907by the compiler are not used. The software is built with the ``-nostdinc`` flag 3908to ensure no headers are included from the toolchain inadvertently. Instead the 3909required headers are included in the TF-A source tree. The library only 3910contains those C library definitions required by the local implementation. If 3911more functionality is required, the needed library functions will need to be 3912added to the local implementation. 3913 3914Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3915been written specifically for TF-A. Some implementation files have been obtained 3916from `FreeBSD`_, others have been written specifically for TF-A as well. The 3917files can be found in ``include/lib/libc`` and ``lib/libc``. 3918 3919SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 3920can be obtained from http://github.com/freebsd/freebsd. 3921 3922Storage abstraction layer 3923------------------------- 3924 3925In order to improve platform independence and portability a storage abstraction 3926layer is used to load data from non-volatile platform storage. Currently 3927storage access is only required by BL1 and BL2 phases and performed inside the 3928``load_image()`` function in ``bl_common.c``. 3929 3930.. uml:: resources/diagrams/plantuml/io_framework_usage_overview.puml 3931 3932It is mandatory to implement at least one storage driver. For the Arm 3933development platforms the Firmware Image Package (FIP) driver is provided as 3934the default means to load data from storage (see :ref:`firmware_design_fip`). 3935The storage layer is described in the header file 3936``include/drivers/io/io_storage.h``. The implementation of the common library is 3937in ``drivers/io/io_storage.c`` and the driver files are located in 3938``drivers/io/``. 3939 3940.. uml:: resources/diagrams/plantuml/io_arm_class_diagram.puml 3941 3942Each IO driver must provide ``io_dev_*`` structures, as described in 3943``drivers/io/io_driver.h``. These are returned via a mandatory registration 3944function that is called on platform initialization. The semi-hosting driver 3945implementation in ``io_semihosting.c`` can be used as an example. 3946 3947Each platform should register devices and their drivers via the storage 3948abstraction layer. These drivers then need to be initialized by bootloader 3949phases as required in their respective ``blx_platform_setup()`` functions. 3950 3951.. uml:: resources/diagrams/plantuml/io_dev_registration.puml 3952 3953The storage abstraction layer provides mechanisms (``io_dev_init()``) to 3954initialize storage devices before IO operations are called. 3955 3956.. uml:: resources/diagrams/plantuml/io_dev_init_and_check.puml 3957 3958The basic operations supported by the layer 3959include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3960Drivers do not have to implement all operations, but each platform must 3961provide at least one driver for a device capable of supporting generic 3962operations such as loading a bootloader image. 3963 3964The current implementation only allows for known images to be loaded by the 3965firmware. These images are specified by using their identifiers, as defined in 3966``include/plat/common/common_def.h`` (or a separate header file included from 3967there). The platform layer (``plat_get_image_source()``) then returns a reference 3968to a device and a driver-specific ``spec`` which will be understood by the driver 3969to allow access to the image data. 3970 3971The layer is designed in such a way that is it possible to chain drivers with 3972other drivers. For example, file-system drivers may be implemented on top of 3973physical block devices, both represented by IO devices with corresponding 3974drivers. In such a case, the file-system "binding" with the block device may 3975be deferred until the file-system device is initialised. 3976 3977The abstraction currently depends on structures being statically allocated 3978by the drivers and callers, as the system does not yet provide a means of 3979dynamically allocating memory. This may also have the affect of limiting the 3980amount of open resources per driver. 3981 3982Measured Boot Platform Interface 3983-------------------------------- 3984 3985Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer 3986to :ref:`Measured Boot Design` for more details. 3987 3988Live Firmware Activation Interface 3989---------------------------------- 3990 3991Function : plat_lfa_get_components() 3992~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3993 3994:: 3995 3996 Argument : plat_lfa_component_info_t ** 3997 Return : int 3998 3999This platform API provides the list of LFA components available for activation. 4000It populates a pointer to an array of ``plat_lfa_component_info_t`` structures, 4001which contain information about each component (like UUID, ID, etc.). It returns 40020 on success, or a standard error code on failure. 4003 4004Function : is_plat_lfa_activation_pending() 4005~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4006 4007:: 4008 4009 Argument : uint32_t 4010 Return : bool 4011 4012This platform API checks if the specified LFA component, identified 4013by its ``lfa_component_id``, is available for activation. It returns 4014true if available, otherwise false. 4015 4016Function : plat_lfa_cancel() 4017~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4018 4019:: 4020 4021 Argument : uint32_t 4022 Return : int 4023 4024This platform API allows the platform to cancel an ongoing update or activation 4025process for the specified ``lfa_component_id``. It returns 0 on success or 4026a standard error code on failure. 4027 4028Function : plat_lfa_load_auth_image() 4029~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4030 4031:: 4032 4033 Argument : uint32_t 4034 Return : int 4035 4036The platform uses this API to load, authenticate and measure the component 4037specified by ``lfa_component_id``. It should return 0 on success or appropriate 4038error codes for load/authentication failures. 4039 4040-------------- 4041 4042*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.* 4043 4044.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 4045.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 4046.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 4047.. _FreeBSD: https://www.freebsd.org 4048.. _SCC: http://www.simple-cc.org/ 4049.. _DRTM: https://developer.arm.com/documentation/den0113/a 4050