1ARM Trusted Firmware Porting Guide 2================================== 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Please note that this document has been updated for the new platform API 16as required by the PSCI v1.0 implementation. Please refer to the 17`Migration Guide`_ for the previous platform API. 18 19Porting the ARM Trusted Firmware to a new platform involves making some 20mandatory and optional modifications for both the cold and warm boot paths. 21Modifications consist of: 22 23- Implementing a platform-specific function or variable, 24- Setting up the execution context in a certain way, or 25- Defining certain constants (for example #defines). 26 27The platform-specific functions and variables are declared in 28`include/plat/common/platform.h`_. The firmware provides a default implementation 29of variables and functions to fulfill the optional requirements. These 30implementations are all weakly defined; they are provided to ease the porting 31effort. Each platform port can override them with its own implementation if the 32default implementation is inadequate. 33 34Platform ports that want to be aligned with standard ARM platforms (for example 35FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the 36corresponding source files in ``plat/arm/common/``. These provide standard 37implementations for some of the required platform porting functions. However, 38using these functions requires the platform port to implement additional 39ARM standard platform porting functions. These additional functions are not 40documented here. 41 42Some modifications are common to all Boot Loader (BL) stages. Section 2 43discusses these in detail. The subsequent sections discuss the remaining 44modifications for each BL stage in detail. 45 46This document should be read in conjunction with the ARM Trusted Firmware 47`User Guide`_. 48 49Common modifications 50-------------------- 51 52This section covers the modifications that should be made by the platform for 53each BL stage to correctly port the firmware stack. They are categorized as 54either mandatory or optional. 55 56Common mandatory modifications 57------------------------------ 58 59A platform port must enable the Memory Management Unit (MMU) as well as the 60instruction and data caches for each BL stage. Setting up the translation 61tables is the responsibility of the platform port because memory maps differ 62across platforms. A memory translation library (see ``lib/xlat_tables/``) is 63provided to help in this setup. 64 65Note that although this library supports non-identity mappings, this is intended 66only for re-mapping peripheral physical addresses and allows platforms with high 67I/O addresses to reduce their virtual address space. All other addresses 68corresponding to code and data must currently use an identity mapping. 69 70Also, the only translation granule size supported in Trusted Firmware is 4KB, as 71various parts of the code assume that is the case. It is not possible to switch 72to 16 KB or 64 KB granule sizes at the moment. 73 74In ARM standard platforms, each BL stage configures the MMU in the 75platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 76an identity mapping for all addresses. 77 78If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 79block of identity mapped secure memory with Device-nGnRE attributes aligned to 80page boundary (4K) for each BL stage. All sections which allocate coherent 81memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 82section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 83possible for the firmware to place variables in it using the following C code 84directive: 85 86:: 87 88 __section("bakery_lock") 89 90Or alternatively the following assembler code directive: 91 92:: 93 94 .section bakery_lock 95 96The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 97used to allocate any data structures that are accessed both when a CPU is 98executing with its MMU and caches enabled, and when it's running with its MMU 99and caches disabled. Examples are given below. 100 101The following variables, functions and constants must be defined by the platform 102for the firmware to work correctly. 103 104File : platform\_def.h [mandatory] 105~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 106 107Each platform must ensure that a header file of this name is in the system 108include path with the following constants defined. This may require updating the 109list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the ARM development 110platforms, this file is found in ``plat/arm/board/<plat_name>/include/``. 111 112Platform ports may optionally use the file `include/plat/common/common\_def.h`_, 113which provides typical values for some of the constants below. These values are 114likely to be suitable for all platform ports. 115 116Platform ports that want to be aligned with standard ARM platforms (for example 117FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides 118standard values for some of the constants below. However, this requires the 119platform port to define additional platform porting constants in 120``platform_def.h``. These additional constants are not documented here. 121 122- **#define : PLATFORM\_LINKER\_FORMAT** 123 124 Defines the linker format used by the platform, for example 125 ``elf64-littleaarch64``. 126 127- **#define : PLATFORM\_LINKER\_ARCH** 128 129 Defines the processor architecture for the linker by the platform, for 130 example ``aarch64``. 131 132- **#define : PLATFORM\_STACK\_SIZE** 133 134 Defines the normal stack memory available to each CPU. This constant is used 135 by `plat/common/aarch64/platform\_mp\_stack.S`_ and 136 `plat/common/aarch64/platform\_up\_stack.S`_. 137 138- **define : CACHE\_WRITEBACK\_GRANULE** 139 140 Defines the size in bits of the largest cache line across all the cache 141 levels in the platform. 142 143- **#define : FIRMWARE\_WELCOME\_STR** 144 145 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 146 function. 147 148- **#define : PLATFORM\_CORE\_COUNT** 149 150 Defines the total number of CPUs implemented by the platform across all 151 clusters in the system. 152 153- **#define : PLAT\_NUM\_PWR\_DOMAINS** 154 155 Defines the total number of nodes in the power domain topology 156 tree at all the power domain levels used by the platform. 157 This macro is used by the PSCI implementation to allocate 158 data structures to represent power domain topology. 159 160- **#define : PLAT\_MAX\_PWR\_LVL** 161 162 Defines the maximum power domain level that the power management operations 163 should apply to. More often, but not always, the power domain level 164 corresponds to affinity level. This macro allows the PSCI implementation 165 to know the highest power domain level that it should consider for power 166 management operations in the system that the platform implements. For 167 example, the Base AEM FVP implements two clusters with a configurable 168 number of CPUs and it reports the maximum power domain level as 1. 169 170- **#define : PLAT\_MAX\_OFF\_STATE** 171 172 Defines the local power state corresponding to the deepest power down 173 possible at every power domain level in the platform. The local power 174 states for each level may be sparsely allocated between 0 and this value 175 with 0 being reserved for the RUN state. The PSCI implementation uses this 176 value to initialize the local power states of the power domain nodes and 177 to specify the requested power state for a PSCI\_CPU\_OFF call. 178 179- **#define : PLAT\_MAX\_RET\_STATE** 180 181 Defines the local power state corresponding to the deepest retention state 182 possible at every power domain level in the platform. This macro should be 183 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the 184 PSCI implementation to distinguish between retention and power down local 185 power states within PSCI\_CPU\_SUSPEND call. 186 187- **#define : PLAT\_MAX\_PWR\_LVL\_STATES** 188 189 Defines the maximum number of local power states per power domain level 190 that the platform supports. The default value of this macro is 2 since 191 most platforms just support a maximum of two local power states at each 192 power domain level (power-down and retention). If the platform needs to 193 account for more local power states, then it must redefine this macro. 194 195 Currently, this macro is used by the Generic PSCI implementation to size 196 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting. 197 198- **#define : BL1\_RO\_BASE** 199 200 Defines the base address in secure ROM where BL1 originally lives. Must be 201 aligned on a page-size boundary. 202 203- **#define : BL1\_RO\_LIMIT** 204 205 Defines the maximum address in secure ROM that BL1's actual content (i.e. 206 excluding any data section allocated at runtime) can occupy. 207 208- **#define : BL1\_RW\_BASE** 209 210 Defines the base address in secure RAM where BL1's read-write data will live 211 at runtime. Must be aligned on a page-size boundary. 212 213- **#define : BL1\_RW\_LIMIT** 214 215 Defines the maximum address in secure RAM that BL1's read-write data can 216 occupy at runtime. 217 218- **#define : BL2\_BASE** 219 220 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 221 Must be aligned on a page-size boundary. 222 223- **#define : BL2\_LIMIT** 224 225 Defines the maximum address in secure RAM that the BL2 image can occupy. 226 227- **#define : BL31\_BASE** 228 229 Defines the base address in secure RAM where BL2 loads the BL31 binary 230 image. Must be aligned on a page-size boundary. 231 232- **#define : BL31\_LIMIT** 233 234 Defines the maximum address in secure RAM that the BL31 image can occupy. 235 236For every image, the platform must define individual identifiers that will be 237used by BL1 or BL2 to load the corresponding image into memory from non-volatile 238storage. For the sake of performance, integer numbers will be used as 239identifiers. The platform will use those identifiers to return the relevant 240information about the image to be loaded (file handler, load address, 241authentication information, etc.). The following image identifiers are 242mandatory: 243 244- **#define : BL2\_IMAGE\_ID** 245 246 BL2 image identifier, used by BL1 to load BL2. 247 248- **#define : BL31\_IMAGE\_ID** 249 250 BL31 image identifier, used by BL2 to load BL31. 251 252- **#define : BL33\_IMAGE\_ID** 253 254 BL33 image identifier, used by BL2 to load BL33. 255 256If Trusted Board Boot is enabled, the following certificate identifiers must 257also be defined: 258 259- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID** 260 261 BL2 content certificate identifier, used by BL1 to load the BL2 content 262 certificate. 263 264- **#define : TRUSTED\_KEY\_CERT\_ID** 265 266 Trusted key certificate identifier, used by BL2 to load the trusted key 267 certificate. 268 269- **#define : SOC\_FW\_KEY\_CERT\_ID** 270 271 BL31 key certificate identifier, used by BL2 to load the BL31 key 272 certificate. 273 274- **#define : SOC\_FW\_CONTENT\_CERT\_ID** 275 276 BL31 content certificate identifier, used by BL2 to load the BL31 content 277 certificate. 278 279- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID** 280 281 BL33 key certificate identifier, used by BL2 to load the BL33 key 282 certificate. 283 284- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID** 285 286 BL33 content certificate identifier, used by BL2 to load the BL33 content 287 certificate. 288 289- **#define : FWU\_CERT\_ID** 290 291 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the 292 FWU content certificate. 293 294- **#define : PLAT\_CRYPTOCELL\_BASE** 295 296 This defines the base address of ARM® TrustZone® CryptoCell and must be 297 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 298 capable ARM platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 299 set. 300 301If the AP Firmware Updater Configuration image, BL2U is used, the following 302must also be defined: 303 304- **#define : BL2U\_BASE** 305 306 Defines the base address in secure memory where BL1 copies the BL2U binary 307 image. Must be aligned on a page-size boundary. 308 309- **#define : BL2U\_LIMIT** 310 311 Defines the maximum address in secure memory that the BL2U image can occupy. 312 313- **#define : BL2U\_IMAGE\_ID** 314 315 BL2U image identifier, used by BL1 to fetch an image descriptor 316 corresponding to BL2U. 317 318If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following 319must also be defined: 320 321- **#define : SCP\_BL2U\_IMAGE\_ID** 322 323 SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor 324 corresponding to SCP\_BL2U. 325 NOTE: TF does not provide source code for this image. 326 327If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must 328also be defined: 329 330- **#define : NS\_BL1U\_BASE** 331 332 Defines the base address in non-secure ROM where NS\_BL1U executes. 333 Must be aligned on a page-size boundary. 334 NOTE: TF does not provide source code for this image. 335 336- **#define : NS\_BL1U\_IMAGE\_ID** 337 338 NS\_BL1U image identifier, used by BL1 to fetch an image descriptor 339 corresponding to NS\_BL1U. 340 341If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also 342be defined: 343 344- **#define : NS\_BL2U\_BASE** 345 346 Defines the base address in non-secure memory where NS\_BL2U executes. 347 Must be aligned on a page-size boundary. 348 NOTE: TF does not provide source code for this image. 349 350- **#define : NS\_BL2U\_IMAGE\_ID** 351 352 NS\_BL2U image identifier, used by BL1 to fetch an image descriptor 353 corresponding to NS\_BL2U. 354 355For the the Firmware update capability of TRUSTED BOARD BOOT, the following 356macros may also be defined: 357 358- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES** 359 360 Total number of images that can be loaded simultaneously. If the platform 361 doesn't specify any value, it defaults to 10. 362 363If a SCP\_BL2 image is supported by the platform, the following constants must 364also be defined: 365 366- **#define : SCP\_BL2\_IMAGE\_ID** 367 368 SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory 369 from platform storage before being transfered to the SCP. 370 371- **#define : SCP\_FW\_KEY\_CERT\_ID** 372 373 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key 374 certificate (mandatory when Trusted Board Boot is enabled). 375 376- **#define : SCP\_FW\_CONTENT\_CERT\_ID** 377 378 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2 379 content certificate (mandatory when Trusted Board Boot is enabled). 380 381If a BL32 image is supported by the platform, the following constants must 382also be defined: 383 384- **#define : BL32\_IMAGE\_ID** 385 386 BL32 image identifier, used by BL2 to load BL32. 387 388- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID** 389 390 BL32 key certificate identifier, used by BL2 to load the BL32 key 391 certificate (mandatory when Trusted Board Boot is enabled). 392 393- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID** 394 395 BL32 content certificate identifier, used by BL2 to load the BL32 content 396 certificate (mandatory when Trusted Board Boot is enabled). 397 398- **#define : BL32\_BASE** 399 400 Defines the base address in secure memory where BL2 loads the BL32 binary 401 image. Must be aligned on a page-size boundary. 402 403- **#define : BL32\_LIMIT** 404 405 Defines the maximum address that the BL32 image can occupy. 406 407If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 408platform, the following constants must also be defined: 409 410- **#define : TSP\_SEC\_MEM\_BASE** 411 412 Defines the base address of the secure memory used by the TSP image on the 413 platform. This must be at the same address or below ``BL32_BASE``. 414 415- **#define : TSP\_SEC\_MEM\_SIZE** 416 417 Defines the size of the secure memory used by the BL32 image on the 418 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate 419 the memory required by the BL32 image, defined by ``BL32_BASE`` and 420 ``BL32_LIMIT``. 421 422- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER** 423 424 Defines the ID of the secure physical generic timer interrupt used by the 425 TSP's interrupt handling code. 426 427If the platform port uses the translation table library code, the following 428constants must also be defined: 429 430- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC** 431 432 Optional flag that can be set per-image to enable the dynamic allocation of 433 regions even when the MMU is enabled. If not defined, only static 434 functionality will be available, if defined and set to 1 it will also 435 include the dynamic functionality. 436 437- **#define : MAX\_XLAT\_TABLES** 438 439 Defines the maximum number of translation tables that are allocated by the 440 translation table library code. To minimize the amount of runtime memory 441 used, choose the smallest value needed to map the required virtual addresses 442 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 443 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 444 as well. 445 446- **#define : MAX\_MMAP\_REGIONS** 447 448 Defines the maximum number of regions that are allocated by the translation 449 table library code. A region consists of physical base address, virtual base 450 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 451 defined in the ``mmap_region_t`` structure. The platform defines the regions 452 that should be mapped. Then, the translation table library will create the 453 corresponding tables and descriptors at runtime. To minimize the amount of 454 runtime memory used, choose the smallest value needed to register the 455 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 456 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 457 the dynamic regions as well. 458 459- **#define : ADDR\_SPACE\_SIZE** 460 461 Defines the total size of the address space in bytes. For example, for a 32 462 bit address space, this value should be ``(1ull << 32)``. This definition is 463 now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and 464 ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead. 465 466- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE** 467 468 Defines the total size of the virtual address space in bytes. For example, 469 for a 32 bit virtual address space, this value should be ``(1ull << 32)``. 470 471- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE** 472 473 Defines the total size of the physical address space in bytes. For example, 474 for a 32 bit physical address space, this value should be ``(1ull << 32)``. 475 476If the platform port uses the IO storage framework, the following constants 477must also be defined: 478 479- **#define : MAX\_IO\_DEVICES** 480 481 Defines the maximum number of registered IO devices. Attempting to register 482 more devices than this value using ``io_register_device()`` will fail with 483 -ENOMEM. 484 485- **#define : MAX\_IO\_HANDLES** 486 487 Defines the maximum number of open IO handles. Attempting to open more IO 488 entities than this value using ``io_open()`` will fail with -ENOMEM. 489 490- **#define : MAX\_IO\_BLOCK\_DEVICES** 491 492 Defines the maximum number of registered IO block devices. Attempting to 493 register more devices this value using ``io_dev_open()`` will fail 494 with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES. 495 With this macro, multiple block devices could be supported at the same 496 time. 497 498If the platform needs to allocate data within the per-cpu data framework in 499BL31, it should define the following macro. Currently this is only required if 500the platform decides not to use the coherent memory section by undefining the 501``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 502required memory within the the per-cpu data to minimize wastage. 503 504- **#define : PLAT\_PCPU\_DATA\_SIZE** 505 506 Defines the memory (in bytes) to be reserved within the per-cpu data 507 structure for use by the platform layer. 508 509The following constants are optional. They should be defined when the platform 510memory layout implies some image overlaying like in ARM standard platforms. 511 512- **#define : BL31\_PROGBITS\_LIMIT** 513 514 Defines the maximum address in secure RAM that the BL31's progbits sections 515 can occupy. 516 517- **#define : TSP\_PROGBITS\_LIMIT** 518 519 Defines the maximum address that the TSP's progbits sections can occupy. 520 521If the platform port uses the PL061 GPIO driver, the following constant may 522optionally be defined: 523 524- **PLAT\_PL061\_MAX\_GPIOS** 525 Maximum number of GPIOs required by the platform. This allows control how 526 much memory is allocated for PL061 GPIO controllers. The default value is 527 528 #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS)) 529 530If the platform port uses the partition driver, the following constant may 531optionally be defined: 532 533- **PLAT\_PARTITION\_MAX\_ENTRIES** 534 Maximum number of partition entries required by the platform. This allows 535 control how much memory is allocated for partition entries. The default 536 value is 128. 537 `For example, define the build flag in platform.mk`_: 538 PLAT\_PARTITION\_MAX\_ENTRIES := 12 539 $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES)) 540 541The following constant is optional. It should be defined to override the default 542behaviour of the ``assert()`` function (for example, to save memory). 543 544- **PLAT\_LOG\_LEVEL\_ASSERT** 545 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 546 ``assert()`` prints the name of the file, the line number and the asserted 547 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 548 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 549 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 550 defined, it defaults to ``LOG_LEVEL``. 551 552If the platform port uses the Activity Monitor Unit, the following constants 553may be defined: 554 555- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK** 556 This mask reflects the set of group counters that should be enabled. The 557 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 558 can be at most 0xffff. If the platform does not define this mask, no group 1 559 counters are enabled. If the platform defines this mask, the following 560 constant needs to also be defined. 561 562- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS** 563 This value is used to allocate an array to save and restore the counters 564 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 565 This value should be equal to the highest bit position set in the 566 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 567 568File : plat\_macros.S [mandatory] 569~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 570 571Each platform must ensure a file of this name is in the system include path with 572the following macro defined. In the ARM development platforms, this file is 573found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 574 575- **Macro : plat\_crash\_print\_regs** 576 577 This macro allows the crash reporting routine to print relevant platform 578 registers in case of an unhandled exception in BL31. This aids in debugging 579 and this macro can be defined to be empty in case register reporting is not 580 desired. 581 582 For instance, GIC or interconnect registers may be helpful for 583 troubleshooting. 584 585Handling Reset 586-------------- 587 588BL1 by default implements the reset vector where execution starts from a cold 589or warm boot. BL31 can be optionally set as a reset vector using the 590``RESET_TO_BL31`` make variable. 591 592For each CPU, the reset vector code is responsible for the following tasks: 593 594#. Distinguishing between a cold boot and a warm boot. 595 596#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 597 the CPU is placed in a platform-specific state until the primary CPU 598 performs the necessary steps to remove it from this state. 599 600#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 601 specific address in the BL31 image in the same processor mode as it was 602 when released from reset. 603 604The following functions need to be implemented by the platform port to enable 605reset vector code to perform the above tasks. 606 607Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0] 608~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 609 610:: 611 612 Argument : void 613 Return : uintptr_t 614 615This function is called with the MMU and caches disabled 616(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 617distinguishing between a warm and cold reset for the current CPU using 618platform-specific means. If it's a warm reset, then it returns the warm 619reset entrypoint point provided to ``plat_setup_psci_ops()`` during 620BL31 initialization. If it's a cold reset then this function must return zero. 621 622This function does not follow the Procedure Call Standard used by the 623Application Binary Interface for the ARM 64-bit architecture. The caller should 624not assume that callee saved registers are preserved across a call to this 625function. 626 627This function fulfills requirement 1 and 3 listed above. 628 629Note that for platforms that support programming the reset address, it is 630expected that a CPU will start executing code directly at the right address, 631both on a cold and warm reset. In this case, there is no need to identify the 632type of reset nor to query the warm reset entrypoint. Therefore, implementing 633this function is not required on such platforms. 634 635Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 636~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 637 638:: 639 640 Argument : void 641 642This function is called with the MMU and data caches disabled. It is responsible 643for placing the executing secondary CPU in a platform-specific state until the 644primary CPU performs the necessary actions to bring it out of that state and 645allow entry into the OS. This function must not return. 646 647In the ARM FVP port, when using the normal boot flow, each secondary CPU powers 648itself off. The primary CPU is responsible for powering up the secondary CPUs 649when normal world software requires them. When booting an EL3 payload instead, 650they stay powered on and are put in a holding pen until their mailbox gets 651populated. 652 653This function fulfills requirement 2 above. 654 655Note that for platforms that can't release secondary CPUs out of reset, only the 656primary CPU will execute the cold boot code. Therefore, implementing this 657function is not required on such platforms. 658 659Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 660~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 661 662:: 663 664 Argument : void 665 Return : unsigned int 666 667This function identifies whether the current CPU is the primary CPU or a 668secondary CPU. A return value of zero indicates that the CPU is not the 669primary CPU, while a non-zero return value indicates that the CPU is the 670primary CPU. 671 672Note that for platforms that can't release secondary CPUs out of reset, only the 673primary CPU will execute the cold boot code. Therefore, there is no need to 674distinguish between primary and secondary CPUs and implementing this function is 675not required. 676 677Function : platform\_mem\_init() [mandatory] 678~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 679 680:: 681 682 Argument : void 683 Return : void 684 685This function is called before any access to data is made by the firmware, in 686order to carry out any essential memory initialization. 687 688Function: plat\_get\_rotpk\_info() 689~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 690 691:: 692 693 Argument : void *, void **, unsigned int *, unsigned int * 694 Return : int 695 696This function is mandatory when Trusted Board Boot is enabled. It returns a 697pointer to the ROTPK stored in the platform (or a hash of it) and its length. 698The ROTPK must be encoded in DER format according to the following ASN.1 699structure: 700 701:: 702 703 AlgorithmIdentifier ::= SEQUENCE { 704 algorithm OBJECT IDENTIFIER, 705 parameters ANY DEFINED BY algorithm OPTIONAL 706 } 707 708 SubjectPublicKeyInfo ::= SEQUENCE { 709 algorithm AlgorithmIdentifier, 710 subjectPublicKey BIT STRING 711 } 712 713In case the function returns a hash of the key: 714 715:: 716 717 DigestInfo ::= SEQUENCE { 718 digestAlgorithm AlgorithmIdentifier, 719 digest OCTET STRING 720 } 721 722The function returns 0 on success. Any other value is treated as error by the 723Trusted Board Boot. The function also reports extra information related 724to the ROTPK in the flags parameter: 725 726:: 727 728 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 729 hash. 730 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 731 verification while the platform ROTPK is not deployed. 732 When this flag is set, the function does not need to 733 return a platform ROTPK, and the authentication 734 framework uses the ROTPK in the certificate without 735 verifying it against the platform value. This flag 736 must not be used in a deployed production environment. 737 738Function: plat\_get\_nv\_ctr() 739~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 740 741:: 742 743 Argument : void *, unsigned int * 744 Return : int 745 746This function is mandatory when Trusted Board Boot is enabled. It returns the 747non-volatile counter value stored in the platform in the second argument. The 748cookie in the first argument may be used to select the counter in case the 749platform provides more than one (for example, on platforms that use the default 750TBBR CoT, the cookie will correspond to the OID values defined in 751TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID). 752 753The function returns 0 on success. Any other value means the counter value could 754not be retrieved from the platform. 755 756Function: plat\_set\_nv\_ctr() 757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 758 759:: 760 761 Argument : void *, unsigned int 762 Return : int 763 764This function is mandatory when Trusted Board Boot is enabled. It sets a new 765counter value in the platform. The cookie in the first argument may be used to 766select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is 767the updated counter value to be written to the NV counter. 768 769The function returns 0 on success. Any other value means the counter value could 770not be updated. 771 772Function: plat\_set\_nv\_ctr2() 773~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 774 775:: 776 777 Argument : void *, const auth_img_desc_t *, unsigned int 778 Return : int 779 780This function is optional when Trusted Board Boot is enabled. If this 781interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 782first argument passed is a cookie and is typically used to 783differentiate between a Non Trusted NV Counter and a Trusted NV 784Counter. The second argument is a pointer to an authentication image 785descriptor and may be used to decide if the counter is allowed to be 786updated or not. The third argument is the updated counter value to 787be written to the NV counter. 788 789The function returns 0 on success. Any other value means the counter value 790either could not be updated or the authentication image descriptor indicates 791that it is not allowed to be updated. 792 793Common mandatory function modifications 794--------------------------------------- 795 796The following functions are mandatory functions which need to be implemented 797by the platform port. 798 799Function : plat\_my\_core\_pos() 800~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 801 802:: 803 804 Argument : void 805 Return : unsigned int 806 807This funtion returns the index of the calling CPU which is used as a 808CPU-specific linear index into blocks of memory (for example while allocating 809per-CPU stacks). This function will be invoked very early in the 810initialization sequence which mandates that this function should be 811implemented in assembly and should not rely on the avalability of a C 812runtime environment. This function can clobber x0 - x8 and must preserve 813x9 - x29. 814 815This function plays a crucial role in the power domain topology framework in 816PSCI and details of this can be found in `Power Domain Topology Design`_. 817 818Function : plat\_core\_pos\_by\_mpidr() 819~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 820 821:: 822 823 Argument : u_register_t 824 Return : int 825 826This function validates the ``MPIDR`` of a CPU and converts it to an index, 827which can be used as a CPU-specific linear index into blocks of memory. In 828case the ``MPIDR`` is invalid, this function returns -1. This function will only 829be invoked by BL31 after the power domain topology is initialized and can 830utilize the C runtime environment. For further details about how ARM Trusted 831Firmware represents the power domain topology and how this relates to the 832linear CPU index, please refer `Power Domain Topology Design`_. 833 834Common optional modifications 835----------------------------- 836 837The following are helper functions implemented by the firmware that perform 838common platform-specific tasks. A platform may choose to override these 839definitions. 840 841Function : plat\_set\_my\_stack() 842~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 843 844:: 845 846 Argument : void 847 Return : void 848 849This function sets the current stack pointer to the normal memory stack that 850has been allocated for the current CPU. For BL images that only require a 851stack for the primary CPU, the UP version of the function is used. The size 852of the stack allocated to each CPU is specified by the platform defined 853constant ``PLATFORM_STACK_SIZE``. 854 855Common implementations of this function for the UP and MP BL images are 856provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 857`plat/common/aarch64/platform\_mp\_stack.S`_ 858 859Function : plat\_get\_my\_stack() 860~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 861 862:: 863 864 Argument : void 865 Return : uintptr_t 866 867This function returns the base address of the normal memory stack that 868has been allocated for the current CPU. For BL images that only require a 869stack for the primary CPU, the UP version of the function is used. The size 870of the stack allocated to each CPU is specified by the platform defined 871constant ``PLATFORM_STACK_SIZE``. 872 873Common implementations of this function for the UP and MP BL images are 874provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 875`plat/common/aarch64/platform\_mp\_stack.S`_ 876 877Function : plat\_report\_exception() 878~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 879 880:: 881 882 Argument : unsigned int 883 Return : void 884 885A platform may need to report various information about its status when an 886exception is taken, for example the current exception level, the CPU security 887state (secure/non-secure), the exception type, and so on. This function is 888called in the following circumstances: 889 890- In BL1, whenever an exception is taken. 891- In BL2, whenever an exception is taken. 892 893The default implementation doesn't do anything, to avoid making assumptions 894about the way the platform displays its status information. 895 896For AArch64, this function receives the exception type as its argument. 897Possible values for exceptions types are listed in the 898`include/common/bl\_common.h`_ header file. Note that these constants are not 899related to any architectural exception code; they are just an ARM Trusted 900Firmware convention. 901 902For AArch32, this function receives the exception mode as its argument. 903Possible values for exception modes are listed in the 904`include/lib/aarch32/arch.h`_ header file. 905 906Function : plat\_reset\_handler() 907~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 908 909:: 910 911 Argument : void 912 Return : void 913 914A platform may need to do additional initialization after reset. This function 915allows the platform to do the platform specific intializations. Platform 916specific errata workarounds could also be implemented here. The api should 917preserve the values of callee saved registers x19 to x29. 918 919The default implementation doesn't do anything. If a platform needs to override 920the default implementation, refer to the `Firmware Design`_ for general 921guidelines. 922 923Function : plat\_disable\_acp() 924~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 925 926:: 927 928 Argument : void 929 Return : void 930 931This api allows a platform to disable the Accelerator Coherency Port (if 932present) during a cluster power down sequence. The default weak implementation 933doesn't do anything. Since this api is called during the power down sequence, 934it has restrictions for stack usage and it can use the registers x0 - x17 as 935scratch registers. It should preserve the value in x18 register as it is used 936by the caller to store the return address. 937 938Function : plat\_error\_handler() 939~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 940 941:: 942 943 Argument : int 944 Return : void 945 946This API is called when the generic code encounters an error situation from 947which it cannot continue. It allows the platform to perform error reporting or 948recovery actions (for example, reset the system). This function must not return. 949 950The parameter indicates the type of error using standard codes from ``errno.h``. 951Possible errors reported by the generic code are: 952 953- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 954 Board Boot is enabled) 955- ``-ENOENT``: the requested image or certificate could not be found or an IO 956 error was detected 957- ``-ENOMEM``: resources exhausted. Trusted Firmware does not use dynamic 958 memory, so this error is usually an indication of an incorrect array size 959 960The default implementation simply spins. 961 962Function : plat\_panic\_handler() 963~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 964 965:: 966 967 Argument : void 968 Return : void 969 970This API is called when the generic code encounters an unexpected error 971situation from which it cannot recover. This function must not return, 972and must be implemented in assembly because it may be called before the C 973environment is initialized. 974 975Note: The address from where it was called is stored in x30 (Link Register). 976The default implementation simply spins. 977 978Function : plat\_get\_bl\_image\_load\_info() 979~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 980 981:: 982 983 Argument : void 984 Return : bl_load_info_t * 985 986This function returns pointer to the list of images that the platform has 987populated to load. This function is currently invoked in BL2 to load the 988BL3xx images, when LOAD\_IMAGE\_V2 is enabled. 989 990Function : plat\_get\_next\_bl\_params() 991~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 992 993:: 994 995 Argument : void 996 Return : bl_params_t * 997 998This function returns a pointer to the shared memory that the platform has 999kept aside to pass trusted firmware related information that next BL image 1000needs. This function is currently invoked in BL2 to pass this information to 1001the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1002 1003Function : plat\_get\_stack\_protector\_canary() 1004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1005 1006:: 1007 1008 Argument : void 1009 Return : u_register_t 1010 1011This function returns a random value that is used to initialize the canary used 1012when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable 1013value will weaken the protection as the attacker could easily write the right 1014value as part of the attack most of the time. Therefore, it should return a 1015true random number. 1016 1017Note: For the protection to be effective, the global data need to be placed at 1018a lower address than the stack bases. Failure to do so would allow an attacker 1019to overwrite the canary as part of the stack buffer overflow attack. 1020 1021Function : plat\_flush\_next\_bl\_params() 1022~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1023 1024:: 1025 1026 Argument : void 1027 Return : void 1028 1029This function flushes to main memory all the image params that are passed to 1030next image. This function is currently invoked in BL2 to flush this information 1031to the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1032 1033Function : plat\_log\_get\_prefix() 1034~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1035 1036:: 1037 1038 Argument : unsigned int 1039 Return : const char * 1040 1041This function defines the prefix string corresponding to the `log_level` to be 1042prepended to all the log output from ARM Trusted Firmware. The `log_level` 1043(argument) will correspond to one of the standard log levels defined in 1044debug.h. The platform can override the common implementation to define a 1045different prefix string for the log output. The implementation should be 1046robust to future changes that increase the number of log levels. 1047 1048Modifications specific to a Boot Loader stage 1049--------------------------------------------- 1050 1051Boot Loader Stage 1 (BL1) 1052------------------------- 1053 1054BL1 implements the reset vector where execution starts from after a cold or 1055warm boot. For each CPU, BL1 is responsible for the following tasks: 1056 1057#. Handling the reset as described in section 2.2 1058 1059#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1060 only this CPU executes the remaining BL1 code, including loading and passing 1061 control to the BL2 stage. 1062 1063#. Identifying and starting the Firmware Update process (if required). 1064 1065#. Loading the BL2 image from non-volatile storage into secure memory at the 1066 address specified by the platform defined constant ``BL2_BASE``. 1067 1068#. Populating a ``meminfo`` structure with the following information in memory, 1069 accessible by BL2 immediately upon entry. 1070 1071 :: 1072 1073 meminfo.total_base = Base address of secure RAM visible to BL2 1074 meminfo.total_size = Size of secure RAM visible to BL2 1075 meminfo.free_base = Base address of secure RAM available for 1076 allocation to BL2 1077 meminfo.free_size = Size of secure RAM available for allocation to BL2 1078 1079 BL1 places this ``meminfo`` structure at the beginning of the free memory 1080 available for its use. Since BL1 cannot allocate memory dynamically at the 1081 moment, its free memory will be available for BL2's use as-is. However, this 1082 means that BL2 must read the ``meminfo`` structure before it starts using its 1083 free memory (this is discussed in Section 3.2). 1084 1085 In future releases of the ARM Trusted Firmware it will be possible for 1086 the platform to decide where it wants to place the ``meminfo`` structure for 1087 BL2. 1088 1089 BL1 implements the ``bl1_init_bl2_mem_layout()`` function to populate the 1090 BL2 ``meminfo`` structure. The platform may override this implementation, for 1091 example if the platform wants to restrict the amount of memory visible to 1092 BL2. Details of how to do this are given below. 1093 1094The following functions need to be implemented by the platform port to enable 1095BL1 to perform the above tasks. 1096 1097Function : bl1\_early\_platform\_setup() [mandatory] 1098~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1099 1100:: 1101 1102 Argument : void 1103 Return : void 1104 1105This function executes with the MMU and data caches disabled. It is only called 1106by the primary CPU. 1107 1108On ARM standard platforms, this function: 1109 1110- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1111 1112- Initializes a UART (PL011 console), which enables access to the ``printf`` 1113 family of functions in BL1. 1114 1115- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1116 the CCI slave interface corresponding to the cluster that includes the 1117 primary CPU. 1118 1119Function : bl1\_plat\_arch\_setup() [mandatory] 1120~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1121 1122:: 1123 1124 Argument : void 1125 Return : void 1126 1127This function performs any platform-specific and architectural setup that the 1128platform requires. Platform-specific setup might include configuration of 1129memory controllers and the interconnect. 1130 1131In ARM standard platforms, this function enables the MMU. 1132 1133This function helps fulfill requirement 2 above. 1134 1135Function : bl1\_platform\_setup() [mandatory] 1136~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1137 1138:: 1139 1140 Argument : void 1141 Return : void 1142 1143This function executes with the MMU and data caches enabled. It is responsible 1144for performing any remaining platform-specific setup that can occur after the 1145MMU and data cache have been enabled. 1146 1147if support for multiple boot sources is required, it initializes the boot 1148sequence used by plat\_try\_next\_boot\_source(). 1149 1150In ARM standard platforms, this function initializes the storage abstraction 1151layer used to load the next bootloader image. 1152 1153This function helps fulfill requirement 4 above. 1154 1155Function : bl1\_plat\_sec\_mem\_layout() [mandatory] 1156~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1157 1158:: 1159 1160 Argument : void 1161 Return : meminfo * 1162 1163This function should only be called on the cold boot path. It executes with the 1164MMU and data caches enabled. The pointer returned by this function must point to 1165a ``meminfo`` structure containing the extents and availability of secure RAM for 1166the BL1 stage. 1167 1168:: 1169 1170 meminfo.total_base = Base address of secure RAM visible to BL1 1171 meminfo.total_size = Size of secure RAM visible to BL1 1172 meminfo.free_base = Base address of secure RAM available for allocation 1173 to BL1 1174 meminfo.free_size = Size of secure RAM available for allocation to BL1 1175 1176This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1177populates a similar structure to tell BL2 the extents of memory available for 1178its own use. 1179 1180This function helps fulfill requirements 4 and 5 above. 1181 1182Function : bl1\_init\_bl2\_mem\_layout() [optional] 1183~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1184 1185:: 1186 1187 Argument : meminfo *, meminfo * 1188 Return : void 1189 1190BL1 needs to tell the next stage the amount of secure RAM available 1191for it to use. This information is populated in a ``meminfo`` 1192structure. 1193 1194Depending upon where BL2 has been loaded in secure RAM (determined by 1195``BL2_BASE``), BL1 calculates the amount of free memory available for BL2 to use. 1196BL1 also ensures that its data sections resident in secure RAM are not visible 1197to BL2. An illustration of how this is done in ARM standard platforms is given 1198in the **Memory layout on ARM development platforms** section in the 1199`Firmware Design`_. 1200 1201Function : bl1\_plat\_prepare\_exit() [optional] 1202~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1203 1204:: 1205 1206 Argument : entry_point_info_t * 1207 Return : void 1208 1209This function is called prior to exiting BL1 in response to the 1210``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1211platform specific clean up or bookkeeping operations before transferring 1212control to the next image. It receives the address of the ``entry_point_info_t`` 1213structure passed from BL2. This function runs with MMU disabled. 1214 1215Function : bl1\_plat\_set\_ep\_info() [optional] 1216~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1217 1218:: 1219 1220 Argument : unsigned int image_id, entry_point_info_t *ep_info 1221 Return : void 1222 1223This function allows platforms to override ``ep_info`` for the given ``image_id``. 1224 1225The default implementation just returns. 1226 1227Function : bl1\_plat\_get\_next\_image\_id() [optional] 1228~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1229 1230:: 1231 1232 Argument : void 1233 Return : unsigned int 1234 1235This and the following function must be overridden to enable the FWU feature. 1236 1237BL1 calls this function after platform setup to identify the next image to be 1238loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1239with the normal boot sequence, which loads and executes BL2. If the platform 1240returns a different image id, BL1 assumes that Firmware Update is required. 1241 1242The default implementation always returns ``BL2_IMAGE_ID``. The ARM development 1243platforms override this function to detect if firmware update is required, and 1244if so, return the first image in the firmware update process. 1245 1246Function : bl1\_plat\_get\_image\_desc() [optional] 1247~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1248 1249:: 1250 1251 Argument : unsigned int image_id 1252 Return : image_desc_t * 1253 1254BL1 calls this function to get the image descriptor information ``image_desc_t`` 1255for the provided ``image_id`` from the platform. 1256 1257The default implementation always returns a common BL2 image descriptor. ARM 1258standard platforms return an image descriptor corresponding to BL2 or one of 1259the firmware update images defined in the Trusted Board Boot Requirements 1260specification. 1261 1262Function : bl1\_plat\_fwu\_done() [optional] 1263~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1264 1265:: 1266 1267 Argument : unsigned int image_id, uintptr_t image_src, 1268 unsigned int image_size 1269 Return : void 1270 1271BL1 calls this function when the FWU process is complete. It must not return. 1272The platform may override this function to take platform specific action, for 1273example to initiate the normal boot flow. 1274 1275The default implementation spins forever. 1276 1277Function : bl1\_plat\_mem\_check() [mandatory] 1278~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1279 1280:: 1281 1282 Argument : uintptr_t mem_base, unsigned int mem_size, 1283 unsigned int flags 1284 Return : int 1285 1286BL1 calls this function while handling FWU related SMCs, more specifically when 1287copying or authenticating an image. Its responsibility is to ensure that the 1288region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1289that this memory corresponds to either a secure or non-secure memory region as 1290indicated by the security state of the ``flags`` argument. 1291 1292This function can safely assume that the value resulting from the addition of 1293``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1294overflow. 1295 1296This function must return 0 on success, a non-null error code otherwise. 1297 1298The default implementation of this function asserts therefore platforms must 1299override it when using the FWU feature. 1300 1301Boot Loader Stage 2 (BL2) 1302------------------------- 1303 1304The BL2 stage is executed only by the primary CPU, which is determined in BL1 1305using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1306``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for: 1307 1308#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform 1309 provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of 1310 the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function. 1311 The platform also defines the address in memory where SCP\_BL2 is loaded 1312 through the optional constant ``SCP_BL2_BASE``. BL2 uses this information 1313 to determine if there is enough memory to load the SCP\_BL2 image. 1314 Subsequent handling of the SCP\_BL2 image is platform-specific and is 1315 implemented in the ``bl2_plat_handle_scp_bl2()`` function. 1316 If ``SCP_BL2_BASE`` is not defined then this step is not performed. 1317 1318#. Loading the BL31 binary image into secure RAM from non-volatile storage. To 1319 load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it 1320 by BL1. This structure allows BL2 to calculate how much secure RAM is 1321 available for its use. The platform also defines the address in secure RAM 1322 where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this 1323 information to determine if there is enough memory to load the BL31 image. 1324 1325#. (Optional) Loading the BL32 binary image (if present) from platform 1326 provided non-volatile storage. To load the BL32 image, BL2 makes use of 1327 the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function. 1328 The platform also defines the address in memory where BL32 is loaded 1329 through the optional constant ``BL32_BASE``. BL2 uses this information 1330 to determine if there is enough memory to load the BL32 image. 1331 If ``BL32_BASE`` is not defined then this and the next step is not performed. 1332 1333#. (Optional) Arranging to pass control to the BL32 image (if present) that 1334 has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info`` 1335 structure in memory provided by the platform with information about how 1336 BL31 should pass control to the BL32 image. 1337 1338#. (Optional) Loading the normal world BL33 binary image (if not loaded by 1339 other means) into non-secure DRAM from platform storage and arranging for 1340 BL31 to pass control to this image. This address is determined using the 1341 ``plat_get_ns_image_entrypoint()`` function described below. 1342 1343#. BL2 populates an ``entry_point_info`` structure in memory provided by the 1344 platform with information about how BL31 should pass control to the 1345 other BL images. 1346 1347The following functions must be implemented by the platform port to enable BL2 1348to perform the above tasks. 1349 1350Function : bl2\_early\_platform\_setup() [mandatory] 1351~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1352 1353:: 1354 1355 Argument : meminfo * 1356 Return : void 1357 1358This function executes with the MMU and data caches disabled. It is only called 1359by the primary CPU. The arguments to this function is the address of the 1360``meminfo`` structure populated by BL1. 1361 1362The platform may copy the contents of the ``meminfo`` structure into a private 1363variable as the original memory may be subsequently overwritten by BL2. The 1364copied structure is made available to all BL2 code through the 1365``bl2_plat_sec_mem_layout()`` function. 1366 1367On ARM standard platforms, this function also: 1368 1369- Initializes a UART (PL011 console), which enables access to the ``printf`` 1370 family of functions in BL2. 1371 1372- Initializes the storage abstraction layer used to load further bootloader 1373 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1374 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1375 1376Function : bl2\_plat\_arch\_setup() [mandatory] 1377~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1378 1379:: 1380 1381 Argument : void 1382 Return : void 1383 1384This function executes with the MMU and data caches disabled. It is only called 1385by the primary CPU. 1386 1387The purpose of this function is to perform any architectural initialization 1388that varies across platforms. 1389 1390On ARM standard platforms, this function enables the MMU. 1391 1392Function : bl2\_platform\_setup() [mandatory] 1393~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1394 1395:: 1396 1397 Argument : void 1398 Return : void 1399 1400This function may execute with the MMU and data caches enabled if the platform 1401port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1402called by the primary CPU. 1403 1404The purpose of this function is to perform any platform initialization 1405specific to BL2. 1406 1407In ARM standard platforms, this function performs security setup, including 1408configuration of the TrustZone controller to allow non-secure masters access 1409to most of DRAM. Part of DRAM is reserved for secure world use. 1410 1411Function : bl2\_plat\_sec\_mem\_layout() [mandatory] 1412~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1413 1414:: 1415 1416 Argument : void 1417 Return : meminfo * 1418 1419This function should only be called on the cold boot path. It may execute with 1420the MMU and data caches enabled if the platform port does the necessary 1421initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU. 1422 1423The purpose of this function is to return a pointer to a ``meminfo`` structure 1424populated with the extents of secure RAM available for BL2 to use. See 1425``bl2_early_platform_setup()`` above. 1426 1427Following function is required only when LOAD\_IMAGE\_V2 is enabled. 1428 1429Function : bl2\_plat\_handle\_post\_image\_load() [mandatory] 1430~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1431 1432:: 1433 1434 Argument : unsigned int 1435 Return : int 1436 1437This function can be used by the platforms to update/use image information 1438for given ``image_id``. This function is currently invoked in BL2 to handle 1439BL image specific information based on the ``image_id`` passed, when 1440LOAD\_IMAGE\_V2 is enabled. 1441 1442Following functions are required only when LOAD\_IMAGE\_V2 is disabled. 1443 1444Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory] 1445~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1446 1447:: 1448 1449 Argument : meminfo * 1450 Return : void 1451 1452This function is used to get the memory limits where BL2 can load the 1453SCP\_BL2 image. The meminfo provided by this is used by load\_image() to 1454validate whether the SCP\_BL2 image can be loaded within the given 1455memory from the given base. 1456 1457Function : bl2\_plat\_handle\_scp\_bl2() [mandatory] 1458~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1459 1460:: 1461 1462 Argument : image_info * 1463 Return : int 1464 1465This function is called after loading SCP\_BL2 image and it is used to perform 1466any platform-specific actions required to handle the SCP firmware. Typically it 1467transfers the image into SCP memory using a platform-specific protocol and waits 1468until SCP executes it and signals to the Application Processor (AP) for BL2 1469execution to continue. 1470 1471This function returns 0 on success, a negative error code otherwise. 1472 1473Function : bl2\_plat\_get\_bl31\_params() [mandatory] 1474~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1475 1476:: 1477 1478 Argument : void 1479 Return : bl31_params * 1480 1481BL2 platform code needs to return a pointer to a ``bl31_params`` structure it 1482will use for passing information to BL31. The ``bl31_params`` structure carries 1483the following information. 1484- Header describing the version information for interpreting the bl31\_param 1485structure 1486- Information about executing the BL33 image in the ``bl33_ep_info`` field 1487- Information about executing the BL32 image in the ``bl32_ep_info`` field 1488- Information about the type and extents of BL31 image in the 1489``bl31_image_info`` field 1490- Information about the type and extents of BL32 image in the 1491``bl32_image_info`` field 1492- Information about the type and extents of BL33 image in the 1493``bl33_image_info`` field 1494 1495The memory pointed by this structure and its sub-structures should be 1496accessible from BL31 initialisation code. BL31 might choose to copy the 1497necessary content, or maintain the structures until BL33 is initialised. 1498 1499Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory] 1500~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1501 1502:: 1503 1504 Argument : void 1505 Return : entry_point_info * 1506 1507BL2 platform code returns a pointer which is used to populate the entry point 1508information for BL31 entry point. The location pointed by it should be 1509accessible from BL1 while processing the synchronous exception to run to BL31. 1510 1511In ARM standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem 1512structure in BL2 memory. 1513 1514Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory] 1515~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1516 1517:: 1518 1519 Argument : image_info *, entry_point_info * 1520 Return : void 1521 1522In the normal boot flow, this function is called after loading BL31 image and 1523it can be used to overwrite the entry point set by loader and also set the 1524security state and SPSR which represents the entry point system state for BL31. 1525 1526When booting an EL3 payload instead, this function is called after populating 1527its entry point address and can be used for the same purpose for the payload 1528image. It receives a null pointer as its first argument in this case. 1529 1530Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory] 1531~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1532 1533:: 1534 1535 Argument : image_info *, entry_point_info * 1536 Return : void 1537 1538This function is called after loading BL32 image and it can be used to 1539overwrite the entry point set by loader and also set the security state 1540and SPSR which represents the entry point system state for BL32. 1541 1542Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory] 1543~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1544 1545:: 1546 1547 Argument : image_info *, entry_point_info * 1548 Return : void 1549 1550This function is called after loading BL33 image and it can be used to 1551overwrite the entry point set by loader and also set the security state 1552and SPSR which represents the entry point system state for BL33. 1553 1554In the preloaded BL33 alternative boot flow, this function is called after 1555populating its entry point address. It is passed a null pointer as its first 1556argument in this case. 1557 1558Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory] 1559~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1560 1561:: 1562 1563 Argument : meminfo * 1564 Return : void 1565 1566This function is used to get the memory limits where BL2 can load the 1567BL32 image. The meminfo provided by this is used by load\_image() to 1568validate whether the BL32 image can be loaded with in the given 1569memory from the given base. 1570 1571Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory] 1572~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1573 1574:: 1575 1576 Argument : meminfo * 1577 Return : void 1578 1579This function is used to get the memory limits where BL2 can load the 1580BL33 image. The meminfo provided by this is used by load\_image() to 1581validate whether the BL33 image can be loaded with in the given 1582memory from the given base. 1583 1584This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1585build options are used. 1586 1587Function : bl2\_plat\_flush\_bl31\_params() [mandatory] 1588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1589 1590:: 1591 1592 Argument : void 1593 Return : void 1594 1595Once BL2 has populated all the structures that needs to be read by BL1 1596and BL31 including the bl31\_params structures and its sub-structures, 1597the bl31\_ep\_info structure and any platform specific data. It flushes 1598all these data to the main memory so that it is available when we jump to 1599later Bootloader stages with MMU off 1600 1601Function : plat\_get\_ns\_image\_entrypoint() [mandatory] 1602~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1603 1604:: 1605 1606 Argument : void 1607 Return : uintptr_t 1608 1609As previously described, BL2 is responsible for arranging for control to be 1610passed to a normal world BL image through BL31. This function returns the 1611entrypoint of that image, which BL31 uses to jump to it. 1612 1613BL2 is responsible for loading the normal world BL33 image (e.g. UEFI). 1614 1615This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1616build options are used. 1617 1618Function : bl2\_plat\_preload\_setup [optional] 1619~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1620 1621:: 1622 Argument : void 1623 Return : void 1624 1625This optional function performs any BL2 platform initialization 1626required before image loading, that is not done later in 1627bl2\_platform\_setup(). Specifically, if support for multiple 1628boot sources is required, it initializes the boot sequence used by 1629plat\_try\_next\_boot\_source(). 1630 1631Function : plat\_try\_next\_boot\_source() [optional] 1632~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1633 1634:: 1635 Argument : void 1636 Return : int 1637 1638This optional function passes to the next boot source in the redundancy 1639sequence. 1640 1641This function moves the current boot redundancy source to the next 1642element in the boot sequence. If there are no more boot sources then it 1643must return 0, otherwise it must return 1. The default implementation 1644of this always returns 0. 1645 1646Boot Loader Stage 2 (BL2) at EL3 1647-------------------------------- 1648 1649When the platform has a non-TF Boot ROM it is desirable to jump 1650directly to BL2 instead of TF BL1. In this case BL2 is expected to 1651execute at EL3 instead of executing at EL1. Refer to the `Firmware 1652Design`_ for more information. 1653 1654All mandatory functions of BL2 must be implemented, except the functions 1655bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because 1656their work is done now by bl2\_el3\_early\_platform\_setup and 1657bl2\_el3\_plat\_arch\_setup. These functions should generally implement 1658the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined. 1659 1660 1661Function : bl2\_el3\_early\_platform\_setup() [mandatory] 1662~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1663 1664:: 1665 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1666 Return : void 1667 1668This function executes with the MMU and data caches disabled. It is only called 1669by the primary CPU. This function receives four parameters which can be used 1670by the platform to pass any needed information from the Boot ROM to BL2. 1671 1672On ARM standard platforms, this function does the following: 1673 1674- Initializes a UART (PL011 console), which enables access to the ``printf`` 1675 family of functions in BL2. 1676 1677- Initializes the storage abstraction layer used to load further bootloader 1678 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1679 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1680 1681- Initializes the private variables that define the memory layout used. 1682 1683Function : bl2\_el3\_plat\_arch\_setup() [mandatory] 1684~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1685 1686:: 1687 Argument : void 1688 Return : void 1689 1690This function executes with the MMU and data caches disabled. It is only called 1691by the primary CPU. 1692 1693The purpose of this function is to perform any architectural initialization 1694that varies across platforms. 1695 1696On ARM standard platforms, this function enables the MMU. 1697 1698Function : bl2\_el3\_plat\_prepare\_exit() [optional] 1699~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1700 1701:: 1702 Argument : void 1703 Return : void 1704 1705This function is called prior to exiting BL2 and run the next image. 1706It should be used to perform platform specific clean up or bookkeeping 1707operations before transferring control to the next image. This function 1708runs with MMU disabled. 1709 1710FWU Boot Loader Stage 2 (BL2U) 1711------------------------------ 1712 1713The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1714process and is executed only by the primary CPU. BL1 passes control to BL2U at 1715``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1716 1717#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure 1718 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1. 1719 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U 1720 should be copied from. Subsequent handling of the SCP\_BL2U image is 1721 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1722 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1723 1724#. Any platform specific setup required to perform the FWU process. For 1725 example, ARM standard platforms initialize the TZC controller so that the 1726 normal world can access DDR memory. 1727 1728The following functions must be implemented by the platform port to enable 1729BL2U to perform the tasks mentioned above. 1730 1731Function : bl2u\_early\_platform\_setup() [mandatory] 1732~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1733 1734:: 1735 1736 Argument : meminfo *mem_info, void *plat_info 1737 Return : void 1738 1739This function executes with the MMU and data caches disabled. It is only 1740called by the primary CPU. The arguments to this function is the address 1741of the ``meminfo`` structure and platform specific info provided by BL1. 1742 1743The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1744private storage as the original memory may be subsequently overwritten by BL2U. 1745 1746On ARM CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1747to extract SCP\_BL2U image information, which is then copied into a private 1748variable. 1749 1750Function : bl2u\_plat\_arch\_setup() [mandatory] 1751~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1752 1753:: 1754 1755 Argument : void 1756 Return : void 1757 1758This function executes with the MMU and data caches disabled. It is only 1759called by the primary CPU. 1760 1761The purpose of this function is to perform any architectural initialization 1762that varies across platforms, for example enabling the MMU (since the memory 1763map differs across platforms). 1764 1765Function : bl2u\_platform\_setup() [mandatory] 1766~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1767 1768:: 1769 1770 Argument : void 1771 Return : void 1772 1773This function may execute with the MMU and data caches enabled if the platform 1774port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1775called by the primary CPU. 1776 1777The purpose of this function is to perform any platform initialization 1778specific to BL2U. 1779 1780In ARM standard platforms, this function performs security setup, including 1781configuration of the TrustZone controller to allow non-secure masters access 1782to most of DRAM. Part of DRAM is reserved for secure world use. 1783 1784Function : bl2u\_plat\_handle\_scp\_bl2u() [optional] 1785~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1786 1787:: 1788 1789 Argument : void 1790 Return : int 1791 1792This function is used to perform any platform-specific actions required to 1793handle the SCP firmware. Typically it transfers the image into SCP memory using 1794a platform-specific protocol and waits until SCP executes it and signals to the 1795Application Processor (AP) for BL2U execution to continue. 1796 1797This function returns 0 on success, a negative error code otherwise. 1798This function is included if SCP\_BL2U\_BASE is defined. 1799 1800Boot Loader Stage 3-1 (BL31) 1801---------------------------- 1802 1803During cold boot, the BL31 stage is executed only by the primary CPU. This is 1804determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1805control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1806CPUs. BL31 executes at EL3 and is responsible for: 1807 1808#. Re-initializing all architectural and platform state. Although BL1 performs 1809 some of this initialization, BL31 remains resident in EL3 and must ensure 1810 that EL3 architectural and platform state is completely initialized. It 1811 should make no assumptions about the system state when it receives control. 1812 1813#. Passing control to a normal world BL image, pre-loaded at a platform- 1814 specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2 1815 populated in memory to do this. 1816 1817#. Providing runtime firmware services. Currently, BL31 only implements a 1818 subset of the Power State Coordination Interface (PSCI) API as a runtime 1819 service. See Section 3.3 below for details of porting the PSCI 1820 implementation. 1821 1822#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1823 specific address by BL2. BL31 exports a set of apis that allow runtime 1824 services to specify the security state in which the next image should be 1825 executed and run the corresponding image. BL31 uses the ``entry_point_info`` 1826 structure populated by BL2 to do this. 1827 1828If BL31 is a reset vector, It also needs to handle the reset as specified in 1829section 2.2 before the tasks described above. 1830 1831The following functions must be implemented by the platform port to enable BL31 1832to perform the above tasks. 1833 1834Function : bl31\_early\_platform\_setup() [mandatory] 1835~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1836 1837:: 1838 1839 Argument : bl31_params *, void * 1840 Return : void 1841 1842This function executes with the MMU and data caches disabled. It is only called 1843by the primary CPU. The arguments to this function are: 1844 1845- The address of the ``bl31_params`` structure populated by BL2. 1846- An opaque pointer that the platform may use as needed. 1847 1848The platform can copy the contents of the ``bl31_params`` structure and its 1849sub-structures into private variables if the original memory may be 1850subsequently overwritten by BL31 and similarly the ``void *`` pointing 1851to the platform data also needs to be saved. 1852 1853In ARM standard platforms, BL2 passes a pointer to a ``bl31_params`` structure 1854in BL2 memory. BL31 copies the information in this pointer to internal data 1855structures. It also performs the following: 1856 1857- Initialize a UART (PL011 console), which enables access to the ``printf`` 1858 family of functions in BL31. 1859 1860- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1861 CCI slave interface corresponding to the cluster that includes the primary 1862 CPU. 1863 1864Function : bl31\_plat\_arch\_setup() [mandatory] 1865~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1866 1867:: 1868 1869 Argument : void 1870 Return : void 1871 1872This function executes with the MMU and data caches disabled. It is only called 1873by the primary CPU. 1874 1875The purpose of this function is to perform any architectural initialization 1876that varies across platforms. 1877 1878On ARM standard platforms, this function enables the MMU. 1879 1880Function : bl31\_platform\_setup() [mandatory] 1881~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1882 1883:: 1884 1885 Argument : void 1886 Return : void 1887 1888This function may execute with the MMU and data caches enabled if the platform 1889port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1890called by the primary CPU. 1891 1892The purpose of this function is to complete platform initialization so that both 1893BL31 runtime services and normal world software can function correctly. 1894 1895On ARM standard platforms, this function does the following: 1896 1897- Initialize the generic interrupt controller. 1898 1899 Depending on the GIC driver selected by the platform, the appropriate GICv2 1900 or GICv3 initialization will be done, which mainly consists of: 1901 1902 - Enable secure interrupts in the GIC CPU interface. 1903 - Disable the legacy interrupt bypass mechanism. 1904 - Configure the priority mask register to allow interrupts of all priorities 1905 to be signaled to the CPU interface. 1906 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1907 - Target all secure SPIs to CPU0. 1908 - Enable these secure interrupts in the GIC distributor. 1909 - Configure all other interrupts as non-secure. 1910 - Enable signaling of secure interrupts in the GIC distributor. 1911 1912- Enable system-level implementation of the generic timer counter through the 1913 memory mapped interface. 1914 1915- Grant access to the system counter timer module 1916 1917- Initialize the power controller device. 1918 1919 In particular, initialise the locks that prevent concurrent accesses to the 1920 power controller device. 1921 1922Function : bl31\_plat\_runtime\_setup() [optional] 1923~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1924 1925:: 1926 1927 Argument : void 1928 Return : void 1929 1930The purpose of this function is allow the platform to perform any BL31 runtime 1931setup just prior to BL31 exit during cold boot. The default weak 1932implementation of this function will invoke ``console_switch_state()`` to switch 1933console output to consoles marked for use in the ``runtime`` state. 1934 1935Function : bl31\_get\_next\_image\_info() [mandatory] 1936~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1937 1938:: 1939 1940 Argument : unsigned int 1941 Return : entry_point_info * 1942 1943This function may execute with the MMU and data caches enabled if the platform 1944port does the necessary initializations in ``bl31_plat_arch_setup()``. 1945 1946This function is called by ``bl31_main()`` to retrieve information provided by 1947BL2 for the next image in the security state specified by the argument. BL31 1948uses this information to pass control to that image in the specified security 1949state. This function must return a pointer to the ``entry_point_info`` structure 1950(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1951should return NULL otherwise. 1952 1953Function : plat\_get\_syscnt\_freq2() [mandatory] 1954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1955 1956:: 1957 1958 Argument : void 1959 Return : unsigned int 1960 1961This function is used by the architecture setup code to retrieve the counter 1962frequency for the CPU's generic timer. This value will be programmed into the 1963``CNTFRQ_EL0`` register. In ARM standard platforms, it returns the base frequency 1964of the system counter, which is retrieved from the first entry in the frequency 1965modes table. 1966 1967#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional] 1968~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1969 1970When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 1971bytes) aligned to the cache line boundary that should be allocated per-cpu to 1972accommodate all the bakery locks. 1973 1974If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 1975calculates the size of the ``bakery_lock`` input section, aligns it to the 1976nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 1977and stores the result in a linker symbol. This constant prevents a platform 1978from relying on the linker and provide a more efficient mechanism for 1979accessing per-cpu bakery lock information. 1980 1981If this constant is defined and its value is not equal to the value 1982calculated by the linker then a link time assertion is raised. A compile time 1983assertion is raised if the value of the constant is not aligned to the cache 1984line boundary. 1985 1986SDEI porting requirements 1987~~~~~~~~~~~~~~~~~~~~~~~~~ 1988 1989The SDEI dispatcher requires the platform to provide the following macros 1990and functions, of which some are optional, and some others mandatory. 1991 1992Macros 1993...... 1994 1995Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 1996^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1997 1998This macro must be defined to the EL3 exception priority level associated with 1999Normal SDEI events on the platform. This must have a higher value (therefore of 2000lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2001 2002Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2003^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2004 2005This macro must be defined to the EL3 exception priority level associated with 2006Critical SDEI events on the platform. This must have a lower value (therefore of 2007higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2008 2009It's recommended that SDEI exception priorities in general are assigned the 2010lowest among Secure priorities. Among the SDEI exceptions, Critical SDEI 2011priority must be higher than Normal SDEI priority. 2012 2013Functions 2014......... 2015 2016Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 2017^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2018 2019:: 2020 2021 Argument: uintptr_t 2022 Return: int 2023 2024This function validates the address of client entry points provided for both 2025event registration and *Complete and Resume* SDEI calls. The function takes one 2026argument, which is the address of the handler the SDEI client requested to 2027register. The function must return ``0`` for successful validation, or ``-1`` 2028upon failure. 2029 2030The default implementation always returns ``0``. On ARM platforms, this function 2031is implemented to translate the entry point to physical address, and further to 2032ensure that the address is located in Non-secure DRAM. 2033 2034Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2035^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2036 2037:: 2038 2039 Argument: uint64_t 2040 Argument: unsigned int 2041 Return: void 2042 2043SDEI specification requires that a PE comes out of reset with the events masked. 2044The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 2045the PE. No SDEI events can be dispatched until such time. 2046 2047Should a PE receive an interrupt that was bound to an SDEI event while the 2048events are masked on the PE, the dispatcher implementation invokes the function 2049``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2050interrupt and the interrupt ID are passed as parameters. 2051 2052The default implementation only prints out a warning message. 2053 2054Power State Coordination Interface (in BL31) 2055-------------------------------------------- 2056 2057The ARM Trusted Firmware's implementation of the PSCI API is based around the 2058concept of a *power domain*. A *power domain* is a CPU or a logical group of 2059CPUs which share some state on which power management operations can be 2060performed as specified by `PSCI`_. Each CPU in the system is assigned a cpu 2061index which is a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. 2062The *power domains* are arranged in a hierarchical tree structure and 2063each *power domain* can be identified in a system by the cpu index of any CPU 2064that is part of that domain and a *power domain level*. A processing element 2065(for example, a CPU) is at level 0. If the *power domain* node above a CPU is 2066a logical grouping of CPUs that share some state, then level 1 is that group 2067of CPUs (for example, a cluster), and level 2 is a group of clusters 2068(for example, the system). More details on the power domain topology and its 2069organization can be found in `Power Domain Topology Design`_. 2070 2071BL31's platform initialization code exports a pointer to the platform-specific 2072power management operations required for the PSCI implementation to function 2073correctly. This information is populated in the ``plat_psci_ops`` structure. The 2074PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2075power management operations on the power domains. For example, the target 2076CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2077handler (if present) is called for the CPU power domain. 2078 2079The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2080describe composite power states specific to a platform. The PSCI implementation 2081defines a generic representation of the power-state parameter viz which is an 2082array of local power states where each index corresponds to a power domain 2083level. Each entry contains the local power state the power domain at that power 2084level could enter. It depends on the ``validate_power_state()`` handler to 2085convert the power-state parameter (possibly encoding a composite power state) 2086passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2087 2088The following functions form part of platform port of PSCI functionality. 2089 2090Function : plat\_psci\_stat\_accounting\_start() [optional] 2091~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2092 2093:: 2094 2095 Argument : const psci_power_state_t * 2096 Return : void 2097 2098This is an optional hook that platforms can implement for residency statistics 2099accounting before entering a low power state. The ``pwr_domain_state`` field of 2100``state_info`` (first argument) can be inspected if stat accounting is done 2101differently at CPU level versus higher levels. As an example, if the element at 2102index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2103state, special hardware logic may be programmed in order to keep track of the 2104residency statistics. For higher levels (array indices > 0), the residency 2105statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2106default implementation will use PMF to capture timestamps. 2107 2108Function : plat\_psci\_stat\_accounting\_stop() [optional] 2109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2110 2111:: 2112 2113 Argument : const psci_power_state_t * 2114 Return : void 2115 2116This is an optional hook that platforms can implement for residency statistics 2117accounting after exiting from a low power state. The ``pwr_domain_state`` field 2118of ``state_info`` (first argument) can be inspected if stat accounting is done 2119differently at CPU level versus higher levels. As an example, if the element at 2120index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2121state, special hardware logic may be programmed in order to keep track of the 2122residency statistics. For higher levels (array indices > 0), the residency 2123statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2124default implementation will use PMF to capture timestamps. 2125 2126Function : plat\_psci\_stat\_get\_residency() [optional] 2127~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2128 2129:: 2130 2131 Argument : unsigned int, const psci_power_state_t *, int 2132 Return : u_register_t 2133 2134This is an optional interface that is is invoked after resuming from a low power 2135state and provides the time spent resident in that low power state by the power 2136domain at a particular power domain level. When a CPU wakes up from suspend, 2137all its parent power domain levels are also woken up. The generic PSCI code 2138invokes this function for each parent power domain that is resumed and it 2139identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2140argument) describes the low power state that the power domain has resumed from. 2141The current CPU is the first CPU in the power domain to resume from the low 2142power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2143CPU in the power domain to suspend and may be needed to calculate the residency 2144for that power domain. 2145 2146Function : plat\_get\_target\_pwr\_state() [optional] 2147~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2148 2149:: 2150 2151 Argument : unsigned int, const plat_local_state_t *, unsigned int 2152 Return : plat_local_state_t 2153 2154The PSCI generic code uses this function to let the platform participate in 2155state coordination during a power management operation. The function is passed 2156a pointer to an array of platform specific local power state ``states`` (second 2157argument) which contains the requested power state for each CPU at a particular 2158power domain level ``lvl`` (first argument) within the power domain. The function 2159is expected to traverse this array of upto ``ncpus`` (third argument) and return 2160a coordinated target power state by the comparing all the requested power 2161states. The target power state should not be deeper than any of the requested 2162power states. 2163 2164A weak definition of this API is provided by default wherein it assumes 2165that the platform assigns a local state value in order of increasing depth 2166of the power state i.e. for two power states X & Y, if X < Y 2167then X represents a shallower power state than Y. As a result, the 2168coordinated target local power state for a power domain will be the minimum 2169of the requested local power state values. 2170 2171Function : plat\_get\_power\_domain\_tree\_desc() [mandatory] 2172~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2173 2174:: 2175 2176 Argument : void 2177 Return : const unsigned char * 2178 2179This function returns a pointer to the byte array containing the power domain 2180topology tree description. The format and method to construct this array are 2181described in `Power Domain Topology Design`_. The BL31 PSCI initilization code 2182requires this array to be described by the platform, either statically or 2183dynamically, to initialize the power domain topology tree. In case the array 2184is populated dynamically, then plat\_core\_pos\_by\_mpidr() and 2185plat\_my\_core\_pos() should also be implemented suitably so that the topology 2186tree description matches the CPU indices returned by these APIs. These APIs 2187together form the platform interface for the PSCI topology framework. 2188 2189Function : plat\_setup\_psci\_ops() [mandatory] 2190~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2191 2192:: 2193 2194 Argument : uintptr_t, const plat_psci_ops ** 2195 Return : int 2196 2197This function may execute with the MMU and data caches enabled if the platform 2198port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2199called by the primary CPU. 2200 2201This function is called by PSCI initialization code. Its purpose is to let 2202the platform layer know about the warm boot entrypoint through the 2203``sec_entrypoint`` (first argument) and to export handler routines for 2204platform-specific psci power management actions by populating the passed 2205pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2206 2207A description of each member of this structure is given below. Please refer to 2208the ARM FVP specific implementation of these handlers in 2209`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the 2210platform wants to support, the associated operation or operations in this 2211structure must be provided and implemented (Refer section 4 of 2212`Firmware Design`_ for the PSCI API supported in Trusted Firmware). To disable 2213a PSCI function in a platform port, the operation should be removed from this 2214structure instead of providing an empty implementation. 2215 2216plat\_psci\_ops.cpu\_standby() 2217.............................. 2218 2219Perform the platform-specific actions to enter the standby state for a cpu 2220indicated by the passed argument. This provides a fast path for CPU standby 2221wherein overheads of PSCI state management and lock acquistion is avoided. 2222For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2223the suspend state type specified in the ``power-state`` parameter should be 2224STANDBY and the target power domain level specified should be the CPU. The 2225handler should put the CPU into a low power retention state (usually by 2226issuing a wfi instruction) and ensure that it can be woken up from that 2227state by a normal interrupt. The generic code expects the handler to succeed. 2228 2229plat\_psci\_ops.pwr\_domain\_on() 2230................................. 2231 2232Perform the platform specific actions to power on a CPU, specified 2233by the ``MPIDR`` (first argument). The generic code expects the platform to 2234return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure. 2235 2236plat\_psci\_ops.pwr\_domain\_off() 2237.................................. 2238 2239Perform the platform specific actions to prepare to power off the calling CPU 2240and its higher parent power domain levels as indicated by the ``target_state`` 2241(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2242 2243The ``target_state`` encodes the platform coordinated target local power states 2244for the CPU power domain and its parent power domain levels. The handler 2245needs to perform power management operation corresponding to the local state 2246at each power level. 2247 2248For this handler, the local power state for the CPU power domain will be a 2249power down state where as it could be either power down, retention or run state 2250for the higher power domain levels depending on the result of state 2251coordination. The generic code expects the handler to succeed. 2252 2253plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] 2254................................................................. 2255 2256This optional function may be used as a performance optimization to replace 2257or complement pwr_domain_suspend() on some platforms. Its calling semantics 2258are identical to pwr_domain_suspend(), except the PSCI implementation only 2259calls this function when suspending to a power down state, and it guarantees 2260that data caches are enabled. 2261 2262When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2263before calling pwr_domain_suspend(). If the target_state corresponds to a 2264power down state and it is safe to perform some or all of the platform 2265specific actions in that function with data caches enabled, it may be more 2266efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2267= 1, data caches remain enabled throughout, and so there is no advantage to 2268moving platform specific actions to this function. 2269 2270plat\_psci\_ops.pwr\_domain\_suspend() 2271...................................... 2272 2273Perform the platform specific actions to prepare to suspend the calling 2274CPU and its higher parent power domain levels as indicated by the 2275``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2276API implementation. 2277 2278The ``target_state`` has a similar meaning as described in 2279the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2280target local power states for the CPU power domain and its parent 2281power domain levels. The handler needs to perform power management operation 2282corresponding to the local state at each power level. The generic code 2283expects the handler to succeed. 2284 2285The difference between turning a power domain off versus suspending it is that 2286in the former case, the power domain is expected to re-initialize its state 2287when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2288case, the power domain is expected to save enough state so that it can resume 2289execution by restoring this state when its powered on (see 2290``pwr_domain_suspend_finish()``). 2291 2292When suspending a core, the platform can also choose to power off the GICv3 2293Redistributor and ITS through an implementation-defined sequence. To achieve 2294this safely, the ITS context must be saved first. The architectural part is 2295implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2296sequence is implementation defined and it is therefore the responsibility of 2297the platform code to implement the necessary sequence. Then the GIC 2298Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2299Powering off the Redistributor requires the implementation to support it and it 2300is the responsibility of the platform code to execute the right implementation 2301defined sequence. 2302 2303When a system suspend is requested, the platform can also make use of the 2304``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2305it has saved the context of the Redistributors and ITS of all the cores in the 2306system. The context of the Distributor can be large and may require it to be 2307allocated in a special area if it cannot fit in the platform's global static 2308data, for example in DRAM. The Distributor can then be powered down using an 2309implementation-defined sequence. 2310 2311plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi() 2312............................................. 2313 2314This is an optional function and, if implemented, is expected to perform 2315platform specific actions including the ``wfi`` invocation which allows the 2316CPU to powerdown. Since this function is invoked outside the PSCI locks, 2317the actions performed in this hook must be local to the CPU or the platform 2318must ensure that races between multiple CPUs cannot occur. 2319 2320The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2321operation and it encodes the platform coordinated target local power states for 2322the CPU power domain and its parent power domain levels. This function must 2323not return back to the caller. 2324 2325If this function is not implemented by the platform, PSCI generic 2326implementation invokes ``psci_power_down_wfi()`` for power down. 2327 2328plat\_psci\_ops.pwr\_domain\_on\_finish() 2329......................................... 2330 2331This function is called by the PSCI implementation after the calling CPU is 2332powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2333It performs the platform-specific setup required to initialize enough state for 2334this CPU to enter the normal world and also provide secure runtime firmware 2335services. 2336 2337The ``target_state`` (first argument) is the prior state of the power domains 2338immediately before the CPU was turned on. It indicates which power domains 2339above the CPU might require initialization due to having previously been in 2340low power states. The generic code expects the handler to succeed. 2341 2342plat\_psci\_ops.pwr\_domain\_suspend\_finish() 2343.............................................. 2344 2345This function is called by the PSCI implementation after the calling CPU is 2346powered on and released from reset in response to an asynchronous wakeup 2347event, for example a timer interrupt that was programmed by the CPU during the 2348``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2349setup required to restore the saved state for this CPU to resume execution 2350in the normal world and also provide secure runtime firmware services. 2351 2352The ``target_state`` (first argument) has a similar meaning as described in 2353the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2354to succeed. 2355 2356If the Distributor, Redistributors or ITS have been powered off as part of a 2357suspend, their context must be restored in this function in the reverse order 2358to how they were saved during suspend sequence. 2359 2360plat\_psci\_ops.system\_off() 2361............................. 2362 2363This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2364call. It performs the platform-specific system poweroff sequence after 2365notifying the Secure Payload Dispatcher. 2366 2367plat\_psci\_ops.system\_reset() 2368............................... 2369 2370This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2371call. It performs the platform-specific system reset sequence after 2372notifying the Secure Payload Dispatcher. 2373 2374plat\_psci\_ops.validate\_power\_state() 2375........................................ 2376 2377This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2378call to validate the ``power_state`` parameter of the PSCI API and if valid, 2379populate it in ``req_state`` (second argument) array as power domain level 2380specific local states. If the ``power_state`` is invalid, the platform must 2381return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the 2382normal world PSCI client. 2383 2384plat\_psci\_ops.validate\_ns\_entrypoint() 2385.......................................... 2386 2387This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2388``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2389parameter passed by the normal world. If the ``entry_point`` is invalid, 2390the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is 2391propagated back to the normal world PSCI client. 2392 2393plat\_psci\_ops.get\_sys\_suspend\_power\_state() 2394................................................. 2395 2396This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2397call to get the ``req_state`` parameter from platform which encodes the power 2398domain level specific local states to suspend to system affinity level. The 2399``req_state`` will be utilized to do the PSCI state coordination and 2400``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2401enter system suspend. 2402 2403plat\_psci\_ops.get\_pwr\_lvl\_state\_idx() 2404........................................... 2405 2406This is an optional function and, if implemented, is invoked by the PSCI 2407implementation to convert the ``local_state`` (first argument) at a specified 2408``pwr_lvl`` (second argument) to an index between 0 and 2409``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2410supports more than two local power states at each power domain level, that is 2411``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2412local power states. 2413 2414plat\_psci\_ops.translate\_power\_state\_by\_mpidr() 2415.................................................... 2416 2417This is an optional function and, if implemented, verifies the ``power_state`` 2418(second argument) parameter of the PSCI API corresponding to a target power 2419domain. The target power domain is identified by using both ``MPIDR`` (first 2420argument) and the power domain level encoded in ``power_state``. The power domain 2421level specific local states are to be extracted from ``power_state`` and be 2422populated in the ``output_state`` (third argument) array. The functionality 2423is similar to the ``validate_power_state`` function described above and is 2424envisaged to be used in case the validity of ``power_state`` depend on the 2425targeted power domain. If the ``power_state`` is invalid for the targeted power 2426domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this 2427function is not implemented, then the generic implementation relies on 2428``validate_power_state`` function to translate the ``power_state``. 2429 2430This function can also be used in case the platform wants to support local 2431power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY 2432APIs as described in Section 5.18 of `PSCI`_. 2433 2434plat\_psci\_ops.get\_node\_hw\_state() 2435...................................... 2436 2437This is an optional function. If implemented this function is intended to return 2438the power state of a node (identified by the first parameter, the ``MPIDR``) in 2439the power domain topology (identified by the second parameter, ``power_level``), 2440as retrieved from a power controller or equivalent component on the platform. 2441Upon successful completion, the implementation must map and return the final 2442status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2443must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2444appropriate. 2445 2446Implementations are not expected to handle ``power_levels`` greater than 2447``PLAT_MAX_PWR_LVL``. 2448 2449plat\_psci\_ops.system\_reset2() 2450................................ 2451 2452This is an optional function. If implemented this function is 2453called during the ``SYSTEM_RESET2`` call to perform a reset 2454based on the first parameter ``reset_type`` as specified in 2455`PSCI`_. The parameter ``cookie`` can be used to pass additional 2456reset information. If the ``reset_type`` is not supported, the 2457function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2458resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2459and vendor reset can return other PSCI error codes as defined 2460in `PSCI`_. On success this function will not return. 2461 2462plat\_psci\_ops.write\_mem\_protect() 2463.................................... 2464 2465This is an optional function. If implemented it enables or disables the 2466``MEM_PROTECT`` functionality based on the value of ``val``. 2467A non-zero value enables ``MEM_PROTECT`` and a value of zero 2468disables it. Upon encountering failures it must return a negative value 2469and on success it must return 0. 2470 2471plat\_psci\_ops.read\_mem\_protect() 2472..................................... 2473 2474This is an optional function. If implemented it returns the current 2475state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2476failures it must return a negative value and on success it must 2477return 0. 2478 2479plat\_psci\_ops.mem\_protect\_chk() 2480................................... 2481 2482This is an optional function. If implemented it checks if a memory 2483region defined by a base address ``base`` and with a size of ``length`` 2484bytes is protected by ``MEM_PROTECT``. If the region is protected 2485then it must return 0, otherwise it must return a negative number. 2486 2487Interrupt Management framework (in BL31) 2488---------------------------------------- 2489 2490BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2491generated in either security state and targeted to EL1 or EL2 in the non-secure 2492state or EL3/S-EL1 in the secure state. The design of this framework is 2493described in the `IMF Design Guide`_ 2494 2495A platform should export the following APIs to support the IMF. The following 2496text briefly describes each api and its implementation in ARM standard 2497platforms. The API implementation depends upon the type of interrupt controller 2498present in the platform. ARM standard platform layer supports both 2499`ARM Generic Interrupt Controller version 2.0 (GICv2)`_ 2500and `3.0 (GICv3)`_. Juno builds the ARM 2501Standard layer to use GICv2 and the FVP can be configured to use either GICv2 or 2502GICv3 depending on the build flag ``FVP_USE_GIC_DRIVER`` (See FVP platform 2503specific build options in `User Guide`_ for more details). 2504 2505See also: `Interrupt Controller Abstraction APIs`__. 2506 2507.. __: platform-interrupt-controller-API.rst 2508 2509Function : plat\_interrupt\_type\_to\_line() [mandatory] 2510~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2511 2512:: 2513 2514 Argument : uint32_t, uint32_t 2515 Return : uint32_t 2516 2517The ARM processor signals an interrupt exception either through the IRQ or FIQ 2518interrupt line. The specific line that is signaled depends on how the interrupt 2519controller (IC) reports different interrupt types from an execution context in 2520either security state. The IMF uses this API to determine which interrupt line 2521the platform IC uses to signal each type of interrupt supported by the framework 2522from a given security state. This API must be invoked at EL3. 2523 2524The first parameter will be one of the ``INTR_TYPE_*`` values (see 2525`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2526security state of the originating execution context. The return result is the 2527bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2528FIQ=2. 2529 2530In the case of ARM standard platforms using GICv2, S-EL1 interrupts are 2531configured as FIQs and Non-secure interrupts as IRQs from either security 2532state. 2533 2534In the case of ARM standard platforms using GICv3, the interrupt line to be 2535configured depends on the security state of the execution context when the 2536interrupt is signalled and are as follows: 2537 2538- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2539 NS-EL0/1/2 context. 2540- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2541 in the NS-EL0/1/2 context. 2542- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2543 context. 2544 2545Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory] 2546~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2547 2548:: 2549 2550 Argument : void 2551 Return : uint32_t 2552 2553This API returns the type of the highest priority pending interrupt at the 2554platform IC. The IMF uses the interrupt type to retrieve the corresponding 2555handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2556pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2557``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2558 2559In the case of ARM standard platforms using GICv2, the *Highest Priority 2560Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2561the pending interrupt. The type of interrupt depends upon the id value as 2562follows. 2563 2564#. id < 1022 is reported as a S-EL1 interrupt 2565#. id = 1022 is reported as a Non-secure interrupt. 2566#. id = 1023 is reported as an invalid interrupt type. 2567 2568In the case of ARM standard platforms using GICv3, the system register 2569``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2570is read to determine the id of the pending interrupt. The type of interrupt 2571depends upon the id value as follows. 2572 2573#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2574#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2575#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2576#. All other interrupt id's are reported as EL3 interrupt. 2577 2578Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory] 2579~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2580 2581:: 2582 2583 Argument : void 2584 Return : uint32_t 2585 2586This API returns the id of the highest priority pending interrupt at the 2587platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2588pending. 2589 2590In the case of ARM standard platforms using GICv2, the *Highest Priority 2591Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2592pending interrupt. The id that is returned by API depends upon the value of 2593the id read from the interrupt controller as follows. 2594 2595#. id < 1022. id is returned as is. 2596#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2597 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2598 This id is returned by the API. 2599#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2600 2601In the case of ARM standard platforms using GICv3, if the API is invoked from 2602EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2603group 0 Register*, is read to determine the id of the pending interrupt. The id 2604that is returned by API depends upon the value of the id read from the 2605interrupt controller as follows. 2606 2607#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2608#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2609 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2610 Register* is read to determine the id of the group 1 interrupt. This id 2611 is returned by the API as long as it is a valid interrupt id 2612#. If the id is any of the special interrupt identifiers, 2613 ``INTR_ID_UNAVAILABLE`` is returned. 2614 2615When the API invoked from S-EL1 for GICv3 systems, the id read from system 2616register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2617Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else 2618``INTR_ID_UNAVAILABLE`` is returned. 2619 2620Function : plat\_ic\_acknowledge\_interrupt() [mandatory] 2621~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2622 2623:: 2624 2625 Argument : void 2626 Return : uint32_t 2627 2628This API is used by the CPU to indicate to the platform IC that processing of 2629the highest pending interrupt has begun. It should return the raw, unmodified 2630value obtained from the interrupt controller when acknowledging an interrupt. 2631The actual interrupt number shall be extracted from this raw value using the API 2632`plat_ic_get_interrupt_id()`__. 2633 2634.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2635 2636This function in ARM standard platforms using GICv2, reads the *Interrupt 2637Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2638priority pending interrupt from pending to active in the interrupt controller. 2639It returns the value read from the ``GICC_IAR``, unmodified. 2640 2641In the case of ARM standard platforms using GICv3, if the API is invoked 2642from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2643Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2644reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2645group 1*. The read changes the state of the highest pending interrupt from 2646pending to active in the interrupt controller. The value read is returned 2647unmodified. 2648 2649The TSP uses this API to start processing of the secure physical timer 2650interrupt. 2651 2652Function : plat\_ic\_end\_of\_interrupt() [mandatory] 2653~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2654 2655:: 2656 2657 Argument : uint32_t 2658 Return : void 2659 2660This API is used by the CPU to indicate to the platform IC that processing of 2661the interrupt corresponding to the id (passed as the parameter) has 2662finished. The id should be the same as the id returned by the 2663``plat_ic_acknowledge_interrupt()`` API. 2664 2665ARM standard platforms write the id to the *End of Interrupt Register* 2666(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2667system register in case of GICv3 depending on where the API is invoked from, 2668EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2669controller. 2670 2671The TSP uses this API to finish processing of the secure physical timer 2672interrupt. 2673 2674Function : plat\_ic\_get\_interrupt\_type() [mandatory] 2675~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2676 2677:: 2678 2679 Argument : uint32_t 2680 Return : uint32_t 2681 2682This API returns the type of the interrupt id passed as the parameter. 2683``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2684interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2685returned depending upon how the interrupt has been configured by the platform 2686IC. This API must be invoked at EL3. 2687 2688ARM standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2689and Non-secure interrupts as Group1 interrupts. It reads the group value 2690corresponding to the interrupt id from the relevant *Interrupt Group Register* 2691(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2692 2693In the case of ARM standard platforms using GICv3, both the *Interrupt Group 2694Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2695(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2696as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2697 2698Crash Reporting mechanism (in BL31) 2699----------------------------------- 2700 2701NOTE: This section assumes that your platform is enabling the MULTI_CONSOLE_API 2702flag in its platform.mk. Not using this flag is deprecated for new platforms. 2703 2704BL31 implements a crash reporting mechanism which prints the various registers 2705of the CPU to enable quick crash analysis and debugging. By default, the 2706definitions in ``plat/common/aarch64/platform\_helpers.S`` will cause the crash 2707output to be routed over the normal console infrastructure and get printed on 2708consoles configured to output in crash state. ``console_set_scope()`` can be 2709used to control whether a console is used for crash output. 2710 2711In some cases (such as debugging very early crashes that happen before the 2712normal boot console can be set up), platforms may want to control crash output 2713more explicitly. For these, the following functions can be overridden by 2714platform code. They are executed outside of a C environment and without a stack. 2715 2716Function : plat\_crash\_console\_init 2717~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2718 2719:: 2720 2721 Argument : void 2722 Return : int 2723 2724This API is used by the crash reporting mechanism to initialize the crash 2725console. It must only use the general purpose registers x0 through x7 to do the 2726initialization and returns 1 on success. 2727 2728If you are trying to debug crashes before the console driver would normally get 2729registered, you can use this to register a driver from assembly with hardcoded 2730parameters. For example, you could register the 16550 driver like this: 2731 2732:: 2733 2734 .section .data.crash_console /* Reserve space for console structure */ 2735 crash_console: 2736 .zero 6 * 8 /* console_16550_t has 6 8-byte words */ 2737 func plat_crash_console_init 2738 ldr x0, =YOUR_16550_BASE_ADDR 2739 ldr x1, =YOUR_16550_SRCCLK_IN_HZ 2740 ldr x2, =YOUR_16550_TARGET_BAUD_RATE 2741 adrp x3, crash_console 2742 add x3, x3, :lo12:crash_console 2743 b console_16550_register /* tail call, returns 1 on success */ 2744 endfunc plat_crash_console_init 2745 2746If you're trying to debug crashes in BL1, you can call the console_xxx_core_init 2747function exported by some console drivers from here. 2748 2749Function : plat\_crash\_console\_putc 2750~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2751 2752:: 2753 2754 Argument : int 2755 Return : int 2756 2757This API is used by the crash reporting mechanism to print a character on the 2758designated crash console. It must only use general purpose registers x1 and 2759x2 to do its work. The parameter and the return value are in general purpose 2760register x0. 2761 2762If you have registered a normal console driver in ``plat_crash_console_init``, 2763you can keep the default implementation here (which calls ``console_putc()``). 2764 2765If you're trying to debug crashes in BL1, you can call the console_xxx_core_putc 2766function exported by some console drivers from here. 2767 2768Function : plat\_crash\_console\_flush 2769~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2770 2771:: 2772 2773 Argument : void 2774 Return : int 2775 2776This API is used by the crash reporting mechanism to force write of all buffered 2777data on the designated crash console. It should only use general purpose 2778registers x0 through x5 to do its work. The return value is 0 on successful 2779completion; otherwise the return value is -1. 2780 2781If you have registered a normal console driver in ``plat_crash_console_init``, 2782you can keep the default implementation here (which calls ``console_flush()``). 2783 2784If you're trying to debug crashes in BL1, you can call the console_xx_core_flush 2785function exported by some console drivers from here. 2786 2787Build flags 2788----------- 2789 2790- **ENABLE\_PLAT\_COMPAT** 2791 All the platforms ports conforming to this API specification should define 2792 the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should 2793 be disabled. For more details on compatibility layer, refer 2794 `Migration Guide`_. 2795 2796There are some build flags which can be defined by the platform to control 2797inclusion or exclusion of certain BL stages from the FIP image. These flags 2798need to be defined in the platform makefile which will get included by the 2799build system. 2800 2801- **NEED\_BL33** 2802 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2803 build option should be supplied as a build option. The platform has the 2804 option of excluding the BL33 image in the ``fip`` image by defining this flag 2805 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2806 are used, this flag will be set to ``no`` automatically. 2807 2808C Library 2809--------- 2810 2811To avoid subtle toolchain behavioral dependencies, the header files provided 2812by the compiler are not used. The software is built with the ``-nostdinc`` flag 2813to ensure no headers are included from the toolchain inadvertently. Instead the 2814required headers are included in the ARM Trusted Firmware source tree. The 2815library only contains those C library definitions required by the local 2816implementation. If more functionality is required, the needed library functions 2817will need to be added to the local implementation. 2818 2819Versions of `FreeBSD`_ headers can be found in ``include/lib/stdlib``. Some of 2820these headers have been cut down in order to simplify the implementation. In 2821order to minimize changes to the header files, the `FreeBSD`_ layout has been 2822maintained. The generic C library definitions can be found in 2823``include/lib/stdlib`` with more system and machine specific declarations in 2824``include/lib/stdlib/sys`` and ``include/lib/stdlib/machine``. 2825 2826The local C library implementations can be found in ``lib/stdlib``. In order to 2827extend the C library these files may need to be modified. It is recommended to 2828use a release version of `FreeBSD`_ as a starting point. 2829 2830The C library header files in the `FreeBSD`_ source tree are located in the 2831``include`` and ``sys/sys`` directories. `FreeBSD`_ machine specific definitions 2832can be found in the ``sys/<machine-type>`` directories. These files define things 2833like 'the size of a pointer' and 'the range of an integer'. Since an AArch64 2834port for `FreeBSD`_ does not yet exist, the machine specific definitions are 2835based on existing machine types with similar properties (for example SPARC64). 2836 2837Where possible, C library function implementations were taken from `FreeBSD`_ 2838as found in the ``lib/libc`` directory. 2839 2840A copy of the `FreeBSD`_ sources can be downloaded with ``git``. 2841 2842:: 2843 2844 git clone git://github.com/freebsd/freebsd.git -b origin/release/9.2.0 2845 2846Storage abstraction layer 2847------------------------- 2848 2849In order to improve platform independence and portability an storage abstraction 2850layer is used to load data from non-volatile platform storage. 2851 2852Each platform should register devices and their drivers via the Storage layer. 2853These drivers then need to be initialized by bootloader phases as 2854required in their respective ``blx_platform_setup()`` functions. Currently 2855storage access is only required by BL1 and BL2 phases. The ``load_image()`` 2856function uses the storage layer to access non-volatile platform storage. 2857 2858It is mandatory to implement at least one storage driver. For the ARM 2859development platforms the Firmware Image Package (FIP) driver is provided as 2860the default means to load data from storage (see the "Firmware Image Package" 2861section in the `User Guide`_). The storage layer is described in the header file 2862``include/drivers/io/io_storage.h``. The implementation of the common library 2863is in ``drivers/io/io_storage.c`` and the driver files are located in 2864``drivers/io/``. 2865 2866Each IO driver must provide ``io_dev_*`` structures, as described in 2867``drivers/io/io_driver.h``. These are returned via a mandatory registration 2868function that is called on platform initialization. The semi-hosting driver 2869implementation in ``io_semihosting.c`` can be used as an example. 2870 2871The Storage layer provides mechanisms to initialize storage devices before 2872IO operations are called. The basic operations supported by the layer 2873include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 2874Drivers do not have to implement all operations, but each platform must 2875provide at least one driver for a device capable of supporting generic 2876operations such as loading a bootloader image. 2877 2878The current implementation only allows for known images to be loaded by the 2879firmware. These images are specified by using their identifiers, as defined in 2880[include/plat/common/platform\_def.h] (or a separate header file included from 2881there). The platform layer (``plat_get_image_source()``) then returns a reference 2882to a device and a driver-specific ``spec`` which will be understood by the driver 2883to allow access to the image data. 2884 2885The layer is designed in such a way that is it possible to chain drivers with 2886other drivers. For example, file-system drivers may be implemented on top of 2887physical block devices, both represented by IO devices with corresponding 2888drivers. In such a case, the file-system "binding" with the block device may 2889be deferred until the file-system device is initialised. 2890 2891The abstraction currently depends on structures being statically allocated 2892by the drivers and callers, as the system does not yet provide a means of 2893dynamically allocating memory. This may also have the affect of limiting the 2894amount of open resources per driver. 2895 2896-------------- 2897 2898*Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.* 2899 2900.. _Migration Guide: platform-migration-guide.rst 2901.. _include/plat/common/platform.h: ../include/plat/common/platform.h 2902.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D 2903.. _User Guide: user-guide.rst 2904.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h 2905.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h 2906.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S 2907.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S 2908.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 2909.. _Power Domain Topology Design: psci-pd-tree.rst 2910.. _include/common/bl\_common.h: ../include/common/bl_common.h 2911.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 2912.. _Firmware Design: firmware-design.rst 2913.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 2914.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c 2915.. _IMF Design Guide: interrupt-framework-design.rst 2916.. _ARM Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 2917.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 2918.. _FreeBSD: http://www.freebsd.org 2919