1Trusted Firmware-A Porting Guide 2================================ 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Please note that this document has been updated for the new platform API 16as required by the PSCI v1.0 implementation. Please refer to the 17`Migration Guide`_ for the previous platform API. 18 19Porting Trusted Firmware-A (TF-A) to a new platform involves making some 20mandatory and optional modifications for both the cold and warm boot paths. 21Modifications consist of: 22 23- Implementing a platform-specific function or variable, 24- Setting up the execution context in a certain way, or 25- Defining certain constants (for example #defines). 26 27The platform-specific functions and variables are declared in 28`include/plat/common/platform.h`_. The firmware provides a default implementation 29of variables and functions to fulfill the optional requirements. These 30implementations are all weakly defined; they are provided to ease the porting 31effort. Each platform port can override them with its own implementation if the 32default implementation is inadequate. 33 34Platform ports that want to be aligned with standard Arm platforms (for example 35FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the 36corresponding source files in ``plat/arm/common/``. These provide standard 37implementations for some of the required platform porting functions. However, 38using these functions requires the platform port to implement additional 39Arm standard platform porting functions. These additional functions are not 40documented here. 41 42Some modifications are common to all Boot Loader (BL) stages. Section 2 43discusses these in detail. The subsequent sections discuss the remaining 44modifications for each BL stage in detail. 45 46This document should be read in conjunction with the TF-A `User Guide`_. 47 48Common modifications 49-------------------- 50 51This section covers the modifications that should be made by the platform for 52each BL stage to correctly port the firmware stack. They are categorized as 53either mandatory or optional. 54 55Common mandatory modifications 56------------------------------ 57 58A platform port must enable the Memory Management Unit (MMU) as well as the 59instruction and data caches for each BL stage. Setting up the translation 60tables is the responsibility of the platform port because memory maps differ 61across platforms. A memory translation library (see ``lib/xlat_tables/``) is 62provided to help in this setup. 63 64Note that although this library supports non-identity mappings, this is intended 65only for re-mapping peripheral physical addresses and allows platforms with high 66I/O addresses to reduce their virtual address space. All other addresses 67corresponding to code and data must currently use an identity mapping. 68 69Also, the only translation granule size supported in TF-A is 4KB, as various 70parts of the code assume that is the case. It is not possible to switch to 7116 KB or 64 KB granule sizes at the moment. 72 73In Arm standard platforms, each BL stage configures the MMU in the 74platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 75an identity mapping for all addresses. 76 77If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 78block of identity mapped secure memory with Device-nGnRE attributes aligned to 79page boundary (4K) for each BL stage. All sections which allocate coherent 80memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 81section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 82possible for the firmware to place variables in it using the following C code 83directive: 84 85:: 86 87 __section("bakery_lock") 88 89Or alternatively the following assembler code directive: 90 91:: 92 93 .section bakery_lock 94 95The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 96used to allocate any data structures that are accessed both when a CPU is 97executing with its MMU and caches enabled, and when it's running with its MMU 98and caches disabled. Examples are given below. 99 100The following variables, functions and constants must be defined by the platform 101for the firmware to work correctly. 102 103File : platform\_def.h [mandatory] 104~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 105 106Each platform must ensure that a header file of this name is in the system 107include path with the following constants defined. This may require updating the 108list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the Arm development 109platforms, this file is found in ``plat/arm/board/<plat_name>/include/``. 110 111Platform ports may optionally use the file `include/plat/common/common\_def.h`_, 112which provides typical values for some of the constants below. These values are 113likely to be suitable for all platform ports. 114 115Platform ports that want to be aligned with standard Arm platforms (for example 116FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides 117standard values for some of the constants below. However, this requires the 118platform port to define additional platform porting constants in 119``platform_def.h``. These additional constants are not documented here. 120 121- **#define : PLATFORM\_LINKER\_FORMAT** 122 123 Defines the linker format used by the platform, for example 124 ``elf64-littleaarch64``. 125 126- **#define : PLATFORM\_LINKER\_ARCH** 127 128 Defines the processor architecture for the linker by the platform, for 129 example ``aarch64``. 130 131- **#define : PLATFORM\_STACK\_SIZE** 132 133 Defines the normal stack memory available to each CPU. This constant is used 134 by `plat/common/aarch64/platform\_mp\_stack.S`_ and 135 `plat/common/aarch64/platform\_up\_stack.S`_. 136 137- **define : CACHE\_WRITEBACK\_GRANULE** 138 139 Defines the size in bits of the largest cache line across all the cache 140 levels in the platform. 141 142- **#define : FIRMWARE\_WELCOME\_STR** 143 144 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 145 function. 146 147- **#define : PLATFORM\_CORE\_COUNT** 148 149 Defines the total number of CPUs implemented by the platform across all 150 clusters in the system. 151 152- **#define : PLAT\_NUM\_PWR\_DOMAINS** 153 154 Defines the total number of nodes in the power domain topology 155 tree at all the power domain levels used by the platform. 156 This macro is used by the PSCI implementation to allocate 157 data structures to represent power domain topology. 158 159- **#define : PLAT\_MAX\_PWR\_LVL** 160 161 Defines the maximum power domain level that the power management operations 162 should apply to. More often, but not always, the power domain level 163 corresponds to affinity level. This macro allows the PSCI implementation 164 to know the highest power domain level that it should consider for power 165 management operations in the system that the platform implements. For 166 example, the Base AEM FVP implements two clusters with a configurable 167 number of CPUs and it reports the maximum power domain level as 1. 168 169- **#define : PLAT\_MAX\_OFF\_STATE** 170 171 Defines the local power state corresponding to the deepest power down 172 possible at every power domain level in the platform. The local power 173 states for each level may be sparsely allocated between 0 and this value 174 with 0 being reserved for the RUN state. The PSCI implementation uses this 175 value to initialize the local power states of the power domain nodes and 176 to specify the requested power state for a PSCI\_CPU\_OFF call. 177 178- **#define : PLAT\_MAX\_RET\_STATE** 179 180 Defines the local power state corresponding to the deepest retention state 181 possible at every power domain level in the platform. This macro should be 182 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the 183 PSCI implementation to distinguish between retention and power down local 184 power states within PSCI\_CPU\_SUSPEND call. 185 186- **#define : PLAT\_MAX\_PWR\_LVL\_STATES** 187 188 Defines the maximum number of local power states per power domain level 189 that the platform supports. The default value of this macro is 2 since 190 most platforms just support a maximum of two local power states at each 191 power domain level (power-down and retention). If the platform needs to 192 account for more local power states, then it must redefine this macro. 193 194 Currently, this macro is used by the Generic PSCI implementation to size 195 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting. 196 197- **#define : BL1\_RO\_BASE** 198 199 Defines the base address in secure ROM where BL1 originally lives. Must be 200 aligned on a page-size boundary. 201 202- **#define : BL1\_RO\_LIMIT** 203 204 Defines the maximum address in secure ROM that BL1's actual content (i.e. 205 excluding any data section allocated at runtime) can occupy. 206 207- **#define : BL1\_RW\_BASE** 208 209 Defines the base address in secure RAM where BL1's read-write data will live 210 at runtime. Must be aligned on a page-size boundary. 211 212- **#define : BL1\_RW\_LIMIT** 213 214 Defines the maximum address in secure RAM that BL1's read-write data can 215 occupy at runtime. 216 217- **#define : BL2\_BASE** 218 219 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 220 Must be aligned on a page-size boundary. This constant is not applicable 221 when BL2_IN_XIP_MEM is set to '1'. 222 223- **#define : BL2\_LIMIT** 224 225 Defines the maximum address in secure RAM that the BL2 image can occupy. 226 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 227 228- **#define : BL2\_RO\_BASE** 229 230 Defines the base address in secure XIP memory where BL2 RO section originally 231 lives. Must be aligned on a page-size boundary. This constant is only needed 232 when BL2_IN_XIP_MEM is set to '1'. 233 234- **#define : BL2\_RO\_LIMIT** 235 236 Defines the maximum address in secure XIP memory that BL2's actual content 237 (i.e. excluding any data section allocated at runtime) can occupy. This 238 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 239 240- **#define : BL2\_RW\_BASE** 241 242 Defines the base address in secure RAM where BL2's read-write data will live 243 at runtime. Must be aligned on a page-size boundary. This constant is only 244 needed when BL2_IN_XIP_MEM is set to '1'. 245 246- **#define : BL2\_RW\_LIMIT** 247 248 Defines the maximum address in secure RAM that BL2's read-write data can 249 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 250 to '1'. 251 252- **#define : BL31\_BASE** 253 254 Defines the base address in secure RAM where BL2 loads the BL31 binary 255 image. Must be aligned on a page-size boundary. 256 257- **#define : BL31\_LIMIT** 258 259 Defines the maximum address in secure RAM that the BL31 image can occupy. 260 261For every image, the platform must define individual identifiers that will be 262used by BL1 or BL2 to load the corresponding image into memory from non-volatile 263storage. For the sake of performance, integer numbers will be used as 264identifiers. The platform will use those identifiers to return the relevant 265information about the image to be loaded (file handler, load address, 266authentication information, etc.). The following image identifiers are 267mandatory: 268 269- **#define : BL2\_IMAGE\_ID** 270 271 BL2 image identifier, used by BL1 to load BL2. 272 273- **#define : BL31\_IMAGE\_ID** 274 275 BL31 image identifier, used by BL2 to load BL31. 276 277- **#define : BL33\_IMAGE\_ID** 278 279 BL33 image identifier, used by BL2 to load BL33. 280 281If Trusted Board Boot is enabled, the following certificate identifiers must 282also be defined: 283 284- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID** 285 286 BL2 content certificate identifier, used by BL1 to load the BL2 content 287 certificate. 288 289- **#define : TRUSTED\_KEY\_CERT\_ID** 290 291 Trusted key certificate identifier, used by BL2 to load the trusted key 292 certificate. 293 294- **#define : SOC\_FW\_KEY\_CERT\_ID** 295 296 BL31 key certificate identifier, used by BL2 to load the BL31 key 297 certificate. 298 299- **#define : SOC\_FW\_CONTENT\_CERT\_ID** 300 301 BL31 content certificate identifier, used by BL2 to load the BL31 content 302 certificate. 303 304- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID** 305 306 BL33 key certificate identifier, used by BL2 to load the BL33 key 307 certificate. 308 309- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID** 310 311 BL33 content certificate identifier, used by BL2 to load the BL33 content 312 certificate. 313 314- **#define : FWU\_CERT\_ID** 315 316 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the 317 FWU content certificate. 318 319- **#define : PLAT\_CRYPTOCELL\_BASE** 320 321 This defines the base address of Arm® TrustZone® CryptoCell and must be 322 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 323 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 324 set. 325 326If the AP Firmware Updater Configuration image, BL2U is used, the following 327must also be defined: 328 329- **#define : BL2U\_BASE** 330 331 Defines the base address in secure memory where BL1 copies the BL2U binary 332 image. Must be aligned on a page-size boundary. 333 334- **#define : BL2U\_LIMIT** 335 336 Defines the maximum address in secure memory that the BL2U image can occupy. 337 338- **#define : BL2U\_IMAGE\_ID** 339 340 BL2U image identifier, used by BL1 to fetch an image descriptor 341 corresponding to BL2U. 342 343If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following 344must also be defined: 345 346- **#define : SCP\_BL2U\_IMAGE\_ID** 347 348 SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor 349 corresponding to SCP\_BL2U. 350 NOTE: TF-A does not provide source code for this image. 351 352If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must 353also be defined: 354 355- **#define : NS\_BL1U\_BASE** 356 357 Defines the base address in non-secure ROM where NS\_BL1U executes. 358 Must be aligned on a page-size boundary. 359 NOTE: TF-A does not provide source code for this image. 360 361- **#define : NS\_BL1U\_IMAGE\_ID** 362 363 NS\_BL1U image identifier, used by BL1 to fetch an image descriptor 364 corresponding to NS\_BL1U. 365 366If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also 367be defined: 368 369- **#define : NS\_BL2U\_BASE** 370 371 Defines the base address in non-secure memory where NS\_BL2U executes. 372 Must be aligned on a page-size boundary. 373 NOTE: TF-A does not provide source code for this image. 374 375- **#define : NS\_BL2U\_IMAGE\_ID** 376 377 NS\_BL2U image identifier, used by BL1 to fetch an image descriptor 378 corresponding to NS\_BL2U. 379 380For the the Firmware update capability of TRUSTED BOARD BOOT, the following 381macros may also be defined: 382 383- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES** 384 385 Total number of images that can be loaded simultaneously. If the platform 386 doesn't specify any value, it defaults to 10. 387 388If a SCP\_BL2 image is supported by the platform, the following constants must 389also be defined: 390 391- **#define : SCP\_BL2\_IMAGE\_ID** 392 393 SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory 394 from platform storage before being transfered to the SCP. 395 396- **#define : SCP\_FW\_KEY\_CERT\_ID** 397 398 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key 399 certificate (mandatory when Trusted Board Boot is enabled). 400 401- **#define : SCP\_FW\_CONTENT\_CERT\_ID** 402 403 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2 404 content certificate (mandatory when Trusted Board Boot is enabled). 405 406If a BL32 image is supported by the platform, the following constants must 407also be defined: 408 409- **#define : BL32\_IMAGE\_ID** 410 411 BL32 image identifier, used by BL2 to load BL32. 412 413- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID** 414 415 BL32 key certificate identifier, used by BL2 to load the BL32 key 416 certificate (mandatory when Trusted Board Boot is enabled). 417 418- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID** 419 420 BL32 content certificate identifier, used by BL2 to load the BL32 content 421 certificate (mandatory when Trusted Board Boot is enabled). 422 423- **#define : BL32\_BASE** 424 425 Defines the base address in secure memory where BL2 loads the BL32 binary 426 image. Must be aligned on a page-size boundary. 427 428- **#define : BL32\_LIMIT** 429 430 Defines the maximum address that the BL32 image can occupy. 431 432If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 433platform, the following constants must also be defined: 434 435- **#define : TSP\_SEC\_MEM\_BASE** 436 437 Defines the base address of the secure memory used by the TSP image on the 438 platform. This must be at the same address or below ``BL32_BASE``. 439 440- **#define : TSP\_SEC\_MEM\_SIZE** 441 442 Defines the size of the secure memory used by the BL32 image on the 443 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate 444 the memory required by the BL32 image, defined by ``BL32_BASE`` and 445 ``BL32_LIMIT``. 446 447- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER** 448 449 Defines the ID of the secure physical generic timer interrupt used by the 450 TSP's interrupt handling code. 451 452If the platform port uses the translation table library code, the following 453constants must also be defined: 454 455- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC** 456 457 Optional flag that can be set per-image to enable the dynamic allocation of 458 regions even when the MMU is enabled. If not defined, only static 459 functionality will be available, if defined and set to 1 it will also 460 include the dynamic functionality. 461 462- **#define : MAX\_XLAT\_TABLES** 463 464 Defines the maximum number of translation tables that are allocated by the 465 translation table library code. To minimize the amount of runtime memory 466 used, choose the smallest value needed to map the required virtual addresses 467 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 468 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 469 as well. 470 471- **#define : MAX\_MMAP\_REGIONS** 472 473 Defines the maximum number of regions that are allocated by the translation 474 table library code. A region consists of physical base address, virtual base 475 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 476 defined in the ``mmap_region_t`` structure. The platform defines the regions 477 that should be mapped. Then, the translation table library will create the 478 corresponding tables and descriptors at runtime. To minimize the amount of 479 runtime memory used, choose the smallest value needed to register the 480 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 481 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 482 the dynamic regions as well. 483 484- **#define : ADDR\_SPACE\_SIZE** 485 486 Defines the total size of the address space in bytes. For example, for a 32 487 bit address space, this value should be ``(1ULL << 32)``. This definition is 488 now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and 489 ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead. 490 491- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE** 492 493 Defines the total size of the virtual address space in bytes. For example, 494 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 495 496- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE** 497 498 Defines the total size of the physical address space in bytes. For example, 499 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 500 501If the platform port uses the IO storage framework, the following constants 502must also be defined: 503 504- **#define : MAX\_IO\_DEVICES** 505 506 Defines the maximum number of registered IO devices. Attempting to register 507 more devices than this value using ``io_register_device()`` will fail with 508 -ENOMEM. 509 510- **#define : MAX\_IO\_HANDLES** 511 512 Defines the maximum number of open IO handles. Attempting to open more IO 513 entities than this value using ``io_open()`` will fail with -ENOMEM. 514 515- **#define : MAX\_IO\_BLOCK\_DEVICES** 516 517 Defines the maximum number of registered IO block devices. Attempting to 518 register more devices this value using ``io_dev_open()`` will fail 519 with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES. 520 With this macro, multiple block devices could be supported at the same 521 time. 522 523If the platform needs to allocate data within the per-cpu data framework in 524BL31, it should define the following macro. Currently this is only required if 525the platform decides not to use the coherent memory section by undefining the 526``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 527required memory within the the per-cpu data to minimize wastage. 528 529- **#define : PLAT\_PCPU\_DATA\_SIZE** 530 531 Defines the memory (in bytes) to be reserved within the per-cpu data 532 structure for use by the platform layer. 533 534The following constants are optional. They should be defined when the platform 535memory layout implies some image overlaying like in Arm standard platforms. 536 537- **#define : BL31\_PROGBITS\_LIMIT** 538 539 Defines the maximum address in secure RAM that the BL31's progbits sections 540 can occupy. 541 542- **#define : TSP\_PROGBITS\_LIMIT** 543 544 Defines the maximum address that the TSP's progbits sections can occupy. 545 546If the platform port uses the PL061 GPIO driver, the following constant may 547optionally be defined: 548 549- **PLAT\_PL061\_MAX\_GPIOS** 550 Maximum number of GPIOs required by the platform. This allows control how 551 much memory is allocated for PL061 GPIO controllers. The default value is 552 553 #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS)) 554 555If the platform port uses the partition driver, the following constant may 556optionally be defined: 557 558- **PLAT\_PARTITION\_MAX\_ENTRIES** 559 Maximum number of partition entries required by the platform. This allows 560 control how much memory is allocated for partition entries. The default 561 value is 128. 562 `For example, define the build flag in platform.mk`_: 563 PLAT\_PARTITION\_MAX\_ENTRIES := 12 564 $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES)) 565 566The following constant is optional. It should be defined to override the default 567behaviour of the ``assert()`` function (for example, to save memory). 568 569- **PLAT\_LOG\_LEVEL\_ASSERT** 570 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 571 ``assert()`` prints the name of the file, the line number and the asserted 572 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 573 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 574 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 575 defined, it defaults to ``LOG_LEVEL``. 576 577If the platform port uses the Activity Monitor Unit, the following constants 578may be defined: 579 580- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK** 581 This mask reflects the set of group counters that should be enabled. The 582 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 583 can be at most 0xffff. If the platform does not define this mask, no group 1 584 counters are enabled. If the platform defines this mask, the following 585 constant needs to also be defined. 586 587- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS** 588 This value is used to allocate an array to save and restore the counters 589 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 590 This value should be equal to the highest bit position set in the 591 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 592 593File : plat\_macros.S [mandatory] 594~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 595 596Each platform must ensure a file of this name is in the system include path with 597the following macro defined. In the Arm development platforms, this file is 598found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 599 600- **Macro : plat\_crash\_print\_regs** 601 602 This macro allows the crash reporting routine to print relevant platform 603 registers in case of an unhandled exception in BL31. This aids in debugging 604 and this macro can be defined to be empty in case register reporting is not 605 desired. 606 607 For instance, GIC or interconnect registers may be helpful for 608 troubleshooting. 609 610Handling Reset 611-------------- 612 613BL1 by default implements the reset vector where execution starts from a cold 614or warm boot. BL31 can be optionally set as a reset vector using the 615``RESET_TO_BL31`` make variable. 616 617For each CPU, the reset vector code is responsible for the following tasks: 618 619#. Distinguishing between a cold boot and a warm boot. 620 621#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 622 the CPU is placed in a platform-specific state until the primary CPU 623 performs the necessary steps to remove it from this state. 624 625#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 626 specific address in the BL31 image in the same processor mode as it was 627 when released from reset. 628 629The following functions need to be implemented by the platform port to enable 630reset vector code to perform the above tasks. 631 632Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0] 633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 634 635:: 636 637 Argument : void 638 Return : uintptr_t 639 640This function is called with the MMU and caches disabled 641(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 642distinguishing between a warm and cold reset for the current CPU using 643platform-specific means. If it's a warm reset, then it returns the warm 644reset entrypoint point provided to ``plat_setup_psci_ops()`` during 645BL31 initialization. If it's a cold reset then this function must return zero. 646 647This function does not follow the Procedure Call Standard used by the 648Application Binary Interface for the Arm 64-bit architecture. The caller should 649not assume that callee saved registers are preserved across a call to this 650function. 651 652This function fulfills requirement 1 and 3 listed above. 653 654Note that for platforms that support programming the reset address, it is 655expected that a CPU will start executing code directly at the right address, 656both on a cold and warm reset. In this case, there is no need to identify the 657type of reset nor to query the warm reset entrypoint. Therefore, implementing 658this function is not required on such platforms. 659 660Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 661~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 662 663:: 664 665 Argument : void 666 667This function is called with the MMU and data caches disabled. It is responsible 668for placing the executing secondary CPU in a platform-specific state until the 669primary CPU performs the necessary actions to bring it out of that state and 670allow entry into the OS. This function must not return. 671 672In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 673itself off. The primary CPU is responsible for powering up the secondary CPUs 674when normal world software requires them. When booting an EL3 payload instead, 675they stay powered on and are put in a holding pen until their mailbox gets 676populated. 677 678This function fulfills requirement 2 above. 679 680Note that for platforms that can't release secondary CPUs out of reset, only the 681primary CPU will execute the cold boot code. Therefore, implementing this 682function is not required on such platforms. 683 684Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 685~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 686 687:: 688 689 Argument : void 690 Return : unsigned int 691 692This function identifies whether the current CPU is the primary CPU or a 693secondary CPU. A return value of zero indicates that the CPU is not the 694primary CPU, while a non-zero return value indicates that the CPU is the 695primary CPU. 696 697Note that for platforms that can't release secondary CPUs out of reset, only the 698primary CPU will execute the cold boot code. Therefore, there is no need to 699distinguish between primary and secondary CPUs and implementing this function is 700not required. 701 702Function : platform\_mem\_init() [mandatory] 703~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 704 705:: 706 707 Argument : void 708 Return : void 709 710This function is called before any access to data is made by the firmware, in 711order to carry out any essential memory initialization. 712 713Function: plat\_get\_rotpk\_info() 714~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 715 716:: 717 718 Argument : void *, void **, unsigned int *, unsigned int * 719 Return : int 720 721This function is mandatory when Trusted Board Boot is enabled. It returns a 722pointer to the ROTPK stored in the platform (or a hash of it) and its length. 723The ROTPK must be encoded in DER format according to the following ASN.1 724structure: 725 726:: 727 728 AlgorithmIdentifier ::= SEQUENCE { 729 algorithm OBJECT IDENTIFIER, 730 parameters ANY DEFINED BY algorithm OPTIONAL 731 } 732 733 SubjectPublicKeyInfo ::= SEQUENCE { 734 algorithm AlgorithmIdentifier, 735 subjectPublicKey BIT STRING 736 } 737 738In case the function returns a hash of the key: 739 740:: 741 742 DigestInfo ::= SEQUENCE { 743 digestAlgorithm AlgorithmIdentifier, 744 digest OCTET STRING 745 } 746 747The function returns 0 on success. Any other value is treated as error by the 748Trusted Board Boot. The function also reports extra information related 749to the ROTPK in the flags parameter: 750 751:: 752 753 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 754 hash. 755 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 756 verification while the platform ROTPK is not deployed. 757 When this flag is set, the function does not need to 758 return a platform ROTPK, and the authentication 759 framework uses the ROTPK in the certificate without 760 verifying it against the platform value. This flag 761 must not be used in a deployed production environment. 762 763Function: plat\_get\_nv\_ctr() 764~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 765 766:: 767 768 Argument : void *, unsigned int * 769 Return : int 770 771This function is mandatory when Trusted Board Boot is enabled. It returns the 772non-volatile counter value stored in the platform in the second argument. The 773cookie in the first argument may be used to select the counter in case the 774platform provides more than one (for example, on platforms that use the default 775TBBR CoT, the cookie will correspond to the OID values defined in 776TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID). 777 778The function returns 0 on success. Any other value means the counter value could 779not be retrieved from the platform. 780 781Function: plat\_set\_nv\_ctr() 782~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 783 784:: 785 786 Argument : void *, unsigned int 787 Return : int 788 789This function is mandatory when Trusted Board Boot is enabled. It sets a new 790counter value in the platform. The cookie in the first argument may be used to 791select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is 792the updated counter value to be written to the NV counter. 793 794The function returns 0 on success. Any other value means the counter value could 795not be updated. 796 797Function: plat\_set\_nv\_ctr2() 798~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 799 800:: 801 802 Argument : void *, const auth_img_desc_t *, unsigned int 803 Return : int 804 805This function is optional when Trusted Board Boot is enabled. If this 806interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 807first argument passed is a cookie and is typically used to 808differentiate between a Non Trusted NV Counter and a Trusted NV 809Counter. The second argument is a pointer to an authentication image 810descriptor and may be used to decide if the counter is allowed to be 811updated or not. The third argument is the updated counter value to 812be written to the NV counter. 813 814The function returns 0 on success. Any other value means the counter value 815either could not be updated or the authentication image descriptor indicates 816that it is not allowed to be updated. 817 818Common mandatory function modifications 819--------------------------------------- 820 821The following functions are mandatory functions which need to be implemented 822by the platform port. 823 824Function : plat\_my\_core\_pos() 825~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 826 827:: 828 829 Argument : void 830 Return : unsigned int 831 832This funtion returns the index of the calling CPU which is used as a 833CPU-specific linear index into blocks of memory (for example while allocating 834per-CPU stacks). This function will be invoked very early in the 835initialization sequence which mandates that this function should be 836implemented in assembly and should not rely on the avalability of a C 837runtime environment. This function can clobber x0 - x8 and must preserve 838x9 - x29. 839 840This function plays a crucial role in the power domain topology framework in 841PSCI and details of this can be found in `Power Domain Topology Design`_. 842 843Function : plat\_core\_pos\_by\_mpidr() 844~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 845 846:: 847 848 Argument : u_register_t 849 Return : int 850 851This function validates the ``MPIDR`` of a CPU and converts it to an index, 852which can be used as a CPU-specific linear index into blocks of memory. In 853case the ``MPIDR`` is invalid, this function returns -1. This function will only 854be invoked by BL31 after the power domain topology is initialized and can 855utilize the C runtime environment. For further details about how TF-A 856represents the power domain topology and how this relates to the linear CPU 857index, please refer `Power Domain Topology Design`_. 858 859Common optional modifications 860----------------------------- 861 862The following are helper functions implemented by the firmware that perform 863common platform-specific tasks. A platform may choose to override these 864definitions. 865 866Function : plat\_set\_my\_stack() 867~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 868 869:: 870 871 Argument : void 872 Return : void 873 874This function sets the current stack pointer to the normal memory stack that 875has been allocated for the current CPU. For BL images that only require a 876stack for the primary CPU, the UP version of the function is used. The size 877of the stack allocated to each CPU is specified by the platform defined 878constant ``PLATFORM_STACK_SIZE``. 879 880Common implementations of this function for the UP and MP BL images are 881provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 882`plat/common/aarch64/platform\_mp\_stack.S`_ 883 884Function : plat\_get\_my\_stack() 885~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 886 887:: 888 889 Argument : void 890 Return : uintptr_t 891 892This function returns the base address of the normal memory stack that 893has been allocated for the current CPU. For BL images that only require a 894stack for the primary CPU, the UP version of the function is used. The size 895of the stack allocated to each CPU is specified by the platform defined 896constant ``PLATFORM_STACK_SIZE``. 897 898Common implementations of this function for the UP and MP BL images are 899provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 900`plat/common/aarch64/platform\_mp\_stack.S`_ 901 902Function : plat\_report\_exception() 903~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 904 905:: 906 907 Argument : unsigned int 908 Return : void 909 910A platform may need to report various information about its status when an 911exception is taken, for example the current exception level, the CPU security 912state (secure/non-secure), the exception type, and so on. This function is 913called in the following circumstances: 914 915- In BL1, whenever an exception is taken. 916- In BL2, whenever an exception is taken. 917 918The default implementation doesn't do anything, to avoid making assumptions 919about the way the platform displays its status information. 920 921For AArch64, this function receives the exception type as its argument. 922Possible values for exceptions types are listed in the 923`include/common/bl\_common.h`_ header file. Note that these constants are not 924related to any architectural exception code; they are just a TF-A convention. 925 926For AArch32, this function receives the exception mode as its argument. 927Possible values for exception modes are listed in the 928`include/lib/aarch32/arch.h`_ header file. 929 930Function : plat\_reset\_handler() 931~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 932 933:: 934 935 Argument : void 936 Return : void 937 938A platform may need to do additional initialization after reset. This function 939allows the platform to do the platform specific intializations. Platform 940specific errata workarounds could also be implemented here. The api should 941preserve the values of callee saved registers x19 to x29. 942 943The default implementation doesn't do anything. If a platform needs to override 944the default implementation, refer to the `Firmware Design`_ for general 945guidelines. 946 947Function : plat\_disable\_acp() 948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 949 950:: 951 952 Argument : void 953 Return : void 954 955This API allows a platform to disable the Accelerator Coherency Port (if 956present) during a cluster power down sequence. The default weak implementation 957doesn't do anything. Since this API is called during the power down sequence, 958it has restrictions for stack usage and it can use the registers x0 - x17 as 959scratch registers. It should preserve the value in x18 register as it is used 960by the caller to store the return address. 961 962Function : plat\_error\_handler() 963~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 964 965:: 966 967 Argument : int 968 Return : void 969 970This API is called when the generic code encounters an error situation from 971which it cannot continue. It allows the platform to perform error reporting or 972recovery actions (for example, reset the system). This function must not return. 973 974The parameter indicates the type of error using standard codes from ``errno.h``. 975Possible errors reported by the generic code are: 976 977- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 978 Board Boot is enabled) 979- ``-ENOENT``: the requested image or certificate could not be found or an IO 980 error was detected 981- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 982 error is usually an indication of an incorrect array size 983 984The default implementation simply spins. 985 986Function : plat\_panic\_handler() 987~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 988 989:: 990 991 Argument : void 992 Return : void 993 994This API is called when the generic code encounters an unexpected error 995situation from which it cannot recover. This function must not return, 996and must be implemented in assembly because it may be called before the C 997environment is initialized. 998 999Note: The address from where it was called is stored in x30 (Link Register). 1000The default implementation simply spins. 1001 1002Function : plat\_get\_bl\_image\_load\_info() 1003~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1004 1005:: 1006 1007 Argument : void 1008 Return : bl_load_info_t * 1009 1010This function returns pointer to the list of images that the platform has 1011populated to load. This function is invoked in BL2 to load the 1012BL3xx images. 1013 1014Function : plat\_get\_next\_bl\_params() 1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1016 1017:: 1018 1019 Argument : void 1020 Return : bl_params_t * 1021 1022This function returns a pointer to the shared memory that the platform has 1023kept aside to pass TF-A related information that next BL image needs. This 1024function is invoked in BL2 to pass this information to the next BL 1025image. 1026 1027Function : plat\_get\_stack\_protector\_canary() 1028~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1029 1030:: 1031 1032 Argument : void 1033 Return : u_register_t 1034 1035This function returns a random value that is used to initialize the canary used 1036when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable 1037value will weaken the protection as the attacker could easily write the right 1038value as part of the attack most of the time. Therefore, it should return a 1039true random number. 1040 1041Note: For the protection to be effective, the global data need to be placed at 1042a lower address than the stack bases. Failure to do so would allow an attacker 1043to overwrite the canary as part of the stack buffer overflow attack. 1044 1045Function : plat\_flush\_next\_bl\_params() 1046~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1047 1048:: 1049 1050 Argument : void 1051 Return : void 1052 1053This function flushes to main memory all the image params that are passed to 1054next image. This function is invoked in BL2 to flush this information 1055to the next BL image. 1056 1057Function : plat\_log\_get\_prefix() 1058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1059 1060:: 1061 1062 Argument : unsigned int 1063 Return : const char * 1064 1065This function defines the prefix string corresponding to the `log_level` to be 1066prepended to all the log output from TF-A. The `log_level` (argument) will 1067correspond to one of the standard log levels defined in debug.h. The platform 1068can override the common implementation to define a different prefix string for 1069the log output. The implementation should be robust to future changes that 1070increase the number of log levels. 1071 1072Function : plat\_get\_mbedtls\_heap() 1073~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1074 1075:: 1076 1077 Arguments : void **heap_addr, size_t *heap_size 1078 Return : int 1079 1080This function is invoked during Mbed TLS library initialisation to get 1081a heap, by means of a starting address and a size. This heap will then be used 1082internally by the Mbed TLS library. The heap is requested from the current BL 1083stage, i.e. the current BL image inside which Mbed TLS is used. 1084 1085In the default implementation a heap is statically allocated inside every image 1086(i.e. every BL stage) that utilises Mbed TLS. So, in this case, the function 1087simply returns the address and size of this "pre-allocated" heap. However, by 1088overriding the default implementation, platforms have the potential to optimise 1089memory usage. For example, on some Arm platforms, the Mbed TLS heap is shared 1090between BL1 and BL2 stages and, thus, the necessary space is not reserved 1091twice. 1092 1093On success the function should return 0 and a negative error code otherwise. 1094 1095Modifications specific to a Boot Loader stage 1096--------------------------------------------- 1097 1098Boot Loader Stage 1 (BL1) 1099------------------------- 1100 1101BL1 implements the reset vector where execution starts from after a cold or 1102warm boot. For each CPU, BL1 is responsible for the following tasks: 1103 1104#. Handling the reset as described in section 2.2 1105 1106#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1107 only this CPU executes the remaining BL1 code, including loading and passing 1108 control to the BL2 stage. 1109 1110#. Identifying and starting the Firmware Update process (if required). 1111 1112#. Loading the BL2 image from non-volatile storage into secure memory at the 1113 address specified by the platform defined constant ``BL2_BASE``. 1114 1115#. Populating a ``meminfo`` structure with the following information in memory, 1116 accessible by BL2 immediately upon entry. 1117 1118 :: 1119 1120 meminfo.total_base = Base address of secure RAM visible to BL2 1121 meminfo.total_size = Size of secure RAM visible to BL2 1122 1123 By default, BL1 places this ``meminfo`` structure at the end of secure 1124 memory visible to BL2. 1125 1126 It is possible for the platform to decide where it wants to place the 1127 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1128 BL2 by overriding the weak default implementation of 1129 ``bl1_plat_handle_post_image_load`` API. 1130 1131The following functions need to be implemented by the platform port to enable 1132BL1 to perform the above tasks. 1133 1134Function : bl1\_early\_platform\_setup() [mandatory] 1135~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1136 1137:: 1138 1139 Argument : void 1140 Return : void 1141 1142This function executes with the MMU and data caches disabled. It is only called 1143by the primary CPU. 1144 1145On Arm standard platforms, this function: 1146 1147- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1148 1149- Initializes a UART (PL011 console), which enables access to the ``printf`` 1150 family of functions in BL1. 1151 1152- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1153 the CCI slave interface corresponding to the cluster that includes the 1154 primary CPU. 1155 1156Function : bl1\_plat\_arch\_setup() [mandatory] 1157~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1158 1159:: 1160 1161 Argument : void 1162 Return : void 1163 1164This function performs any platform-specific and architectural setup that the 1165platform requires. Platform-specific setup might include configuration of 1166memory controllers and the interconnect. 1167 1168In Arm standard platforms, this function enables the MMU. 1169 1170This function helps fulfill requirement 2 above. 1171 1172Function : bl1\_platform\_setup() [mandatory] 1173~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1174 1175:: 1176 1177 Argument : void 1178 Return : void 1179 1180This function executes with the MMU and data caches enabled. It is responsible 1181for performing any remaining platform-specific setup that can occur after the 1182MMU and data cache have been enabled. 1183 1184if support for multiple boot sources is required, it initializes the boot 1185sequence used by plat\_try\_next\_boot\_source(). 1186 1187In Arm standard platforms, this function initializes the storage abstraction 1188layer used to load the next bootloader image. 1189 1190This function helps fulfill requirement 4 above. 1191 1192Function : bl1\_plat\_sec\_mem\_layout() [mandatory] 1193~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1194 1195:: 1196 1197 Argument : void 1198 Return : meminfo * 1199 1200This function should only be called on the cold boot path. It executes with the 1201MMU and data caches enabled. The pointer returned by this function must point to 1202a ``meminfo`` structure containing the extents and availability of secure RAM for 1203the BL1 stage. 1204 1205:: 1206 1207 meminfo.total_base = Base address of secure RAM visible to BL1 1208 meminfo.total_size = Size of secure RAM visible to BL1 1209 meminfo.free_base = Base address of secure RAM available for allocation 1210 to BL1 1211 meminfo.free_size = Size of secure RAM available for allocation to BL1 1212 1213This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1214populates a similar structure to tell BL2 the extents of memory available for 1215its own use. 1216 1217This function helps fulfill requirements 4 and 5 above. 1218 1219Function : bl1\_plat\_prepare\_exit() [optional] 1220~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1221 1222:: 1223 1224 Argument : entry_point_info_t * 1225 Return : void 1226 1227This function is called prior to exiting BL1 in response to the 1228``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1229platform specific clean up or bookkeeping operations before transferring 1230control to the next image. It receives the address of the ``entry_point_info_t`` 1231structure passed from BL2. This function runs with MMU disabled. 1232 1233Function : bl1\_plat\_set\_ep\_info() [optional] 1234~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1235 1236:: 1237 1238 Argument : unsigned int image_id, entry_point_info_t *ep_info 1239 Return : void 1240 1241This function allows platforms to override ``ep_info`` for the given ``image_id``. 1242 1243The default implementation just returns. 1244 1245Function : bl1\_plat\_get\_next\_image\_id() [optional] 1246~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1247 1248:: 1249 1250 Argument : void 1251 Return : unsigned int 1252 1253This and the following function must be overridden to enable the FWU feature. 1254 1255BL1 calls this function after platform setup to identify the next image to be 1256loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1257with the normal boot sequence, which loads and executes BL2. If the platform 1258returns a different image id, BL1 assumes that Firmware Update is required. 1259 1260The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1261platforms override this function to detect if firmware update is required, and 1262if so, return the first image in the firmware update process. 1263 1264Function : bl1\_plat\_get\_image\_desc() [optional] 1265~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1266 1267:: 1268 1269 Argument : unsigned int image_id 1270 Return : image_desc_t * 1271 1272BL1 calls this function to get the image descriptor information ``image_desc_t`` 1273for the provided ``image_id`` from the platform. 1274 1275The default implementation always returns a common BL2 image descriptor. Arm 1276standard platforms return an image descriptor corresponding to BL2 or one of 1277the firmware update images defined in the Trusted Board Boot Requirements 1278specification. 1279 1280Function : bl1\_plat\_handle\_pre\_image\_load() [optional] 1281~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1282 1283:: 1284 1285 Argument : unsigned int image_id 1286 Return : int 1287 1288This function can be used by the platforms to update/use image information 1289corresponding to ``image_id``. This function is invoked in BL1, both in cold 1290boot and FWU code path, before loading the image. 1291 1292Function : bl1\_plat\_handle\_post\_image\_load() [optional] 1293~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1294 1295:: 1296 1297 Argument : unsigned int image_id 1298 Return : int 1299 1300This function can be used by the platforms to update/use image information 1301corresponding to ``image_id``. This function is invoked in BL1, both in cold 1302boot and FWU code path, after loading and authenticating the image. 1303 1304The default weak implementation of this function calculates the amount of 1305Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1306structure at the beginning of this free memory and populates it. The address 1307of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1308information to BL2. 1309 1310Function : bl1\_plat\_fwu\_done() [optional] 1311~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1312 1313:: 1314 1315 Argument : unsigned int image_id, uintptr_t image_src, 1316 unsigned int image_size 1317 Return : void 1318 1319BL1 calls this function when the FWU process is complete. It must not return. 1320The platform may override this function to take platform specific action, for 1321example to initiate the normal boot flow. 1322 1323The default implementation spins forever. 1324 1325Function : bl1\_plat\_mem\_check() [mandatory] 1326~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1327 1328:: 1329 1330 Argument : uintptr_t mem_base, unsigned int mem_size, 1331 unsigned int flags 1332 Return : int 1333 1334BL1 calls this function while handling FWU related SMCs, more specifically when 1335copying or authenticating an image. Its responsibility is to ensure that the 1336region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1337that this memory corresponds to either a secure or non-secure memory region as 1338indicated by the security state of the ``flags`` argument. 1339 1340This function can safely assume that the value resulting from the addition of 1341``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1342overflow. 1343 1344This function must return 0 on success, a non-null error code otherwise. 1345 1346The default implementation of this function asserts therefore platforms must 1347override it when using the FWU feature. 1348 1349Boot Loader Stage 2 (BL2) 1350------------------------- 1351 1352The BL2 stage is executed only by the primary CPU, which is determined in BL1 1353using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1354``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1355``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1356non-volatile storage to secure/non-secure RAM. After all the images are loaded 1357then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1358images to be passed to the next BL image. 1359 1360The following functions must be implemented by the platform port to enable BL2 1361to perform the above tasks. 1362 1363Function : bl2\_early\_platform\_setup2() [mandatory] 1364~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1365 1366:: 1367 1368 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1369 Return : void 1370 1371This function executes with the MMU and data caches disabled. It is only called 1372by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1373are platform specific. 1374 1375On Arm standard platforms, the arguments received are : 1376 1377 arg0 - Points to load address of HW_CONFIG if present 1378 1379 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1380 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1381 1382On Arm standard platforms, this function also: 1383 1384- Initializes a UART (PL011 console), which enables access to the ``printf`` 1385 family of functions in BL2. 1386 1387- Initializes the storage abstraction layer used to load further bootloader 1388 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1389 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1390 1391Function : bl2\_plat\_arch\_setup() [mandatory] 1392~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1393 1394:: 1395 1396 Argument : void 1397 Return : void 1398 1399This function executes with the MMU and data caches disabled. It is only called 1400by the primary CPU. 1401 1402The purpose of this function is to perform any architectural initialization 1403that varies across platforms. 1404 1405On Arm standard platforms, this function enables the MMU. 1406 1407Function : bl2\_platform\_setup() [mandatory] 1408~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1409 1410:: 1411 1412 Argument : void 1413 Return : void 1414 1415This function may execute with the MMU and data caches enabled if the platform 1416port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1417called by the primary CPU. 1418 1419The purpose of this function is to perform any platform initialization 1420specific to BL2. 1421 1422In Arm standard platforms, this function performs security setup, including 1423configuration of the TrustZone controller to allow non-secure masters access 1424to most of DRAM. Part of DRAM is reserved for secure world use. 1425 1426Function : bl2\_plat\_handle\_pre\_image\_load() [optional] 1427~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1428 1429:: 1430 1431 Argument : unsigned int 1432 Return : int 1433 1434This function can be used by the platforms to update/use image information 1435for given ``image_id``. This function is currently invoked in BL2 before 1436loading each image. 1437 1438Function : bl2\_plat\_handle\_post\_image\_load() [optional] 1439~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1440 1441:: 1442 1443 Argument : unsigned int 1444 Return : int 1445 1446This function can be used by the platforms to update/use image information 1447for given ``image_id``. This function is currently invoked in BL2 after 1448loading each image. 1449 1450Function : bl2\_plat\_preload\_setup [optional] 1451~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1452 1453:: 1454 1455 Argument : void 1456 Return : void 1457 1458This optional function performs any BL2 platform initialization 1459required before image loading, that is not done later in 1460bl2\_platform\_setup(). Specifically, if support for multiple 1461boot sources is required, it initializes the boot sequence used by 1462plat\_try\_next\_boot\_source(). 1463 1464Function : plat\_try\_next\_boot\_source() [optional] 1465~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1466 1467:: 1468 1469 Argument : void 1470 Return : int 1471 1472This optional function passes to the next boot source in the redundancy 1473sequence. 1474 1475This function moves the current boot redundancy source to the next 1476element in the boot sequence. If there are no more boot sources then it 1477must return 0, otherwise it must return 1. The default implementation 1478of this always returns 0. 1479 1480Boot Loader Stage 2 (BL2) at EL3 1481-------------------------------- 1482 1483When the platform has a non-TF-A Boot ROM it is desirable to jump 1484directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1485execute at EL3 instead of executing at EL1. Refer to the `Firmware 1486Design`_ for more information. 1487 1488All mandatory functions of BL2 must be implemented, except the functions 1489bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because 1490their work is done now by bl2\_el3\_early\_platform\_setup and 1491bl2\_el3\_plat\_arch\_setup. These functions should generally implement 1492the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined. 1493 1494 1495Function : bl2\_el3\_early\_platform\_setup() [mandatory] 1496~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1497 1498:: 1499 1500 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1501 Return : void 1502 1503This function executes with the MMU and data caches disabled. It is only called 1504by the primary CPU. This function receives four parameters which can be used 1505by the platform to pass any needed information from the Boot ROM to BL2. 1506 1507On Arm standard platforms, this function does the following: 1508 1509- Initializes a UART (PL011 console), which enables access to the ``printf`` 1510 family of functions in BL2. 1511 1512- Initializes the storage abstraction layer used to load further bootloader 1513 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1514 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1515 1516- Initializes the private variables that define the memory layout used. 1517 1518Function : bl2\_el3\_plat\_arch\_setup() [mandatory] 1519~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1520 1521:: 1522 1523 Argument : void 1524 Return : void 1525 1526This function executes with the MMU and data caches disabled. It is only called 1527by the primary CPU. 1528 1529The purpose of this function is to perform any architectural initialization 1530that varies across platforms. 1531 1532On Arm standard platforms, this function enables the MMU. 1533 1534Function : bl2\_el3\_plat\_prepare\_exit() [optional] 1535~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1536 1537:: 1538 1539 Argument : void 1540 Return : void 1541 1542This function is called prior to exiting BL2 and run the next image. 1543It should be used to perform platform specific clean up or bookkeeping 1544operations before transferring control to the next image. This function 1545runs with MMU disabled. 1546 1547FWU Boot Loader Stage 2 (BL2U) 1548------------------------------ 1549 1550The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1551process and is executed only by the primary CPU. BL1 passes control to BL2U at 1552``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1553 1554#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure 1555 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1. 1556 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U 1557 should be copied from. Subsequent handling of the SCP\_BL2U image is 1558 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1559 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1560 1561#. Any platform specific setup required to perform the FWU process. For 1562 example, Arm standard platforms initialize the TZC controller so that the 1563 normal world can access DDR memory. 1564 1565The following functions must be implemented by the platform port to enable 1566BL2U to perform the tasks mentioned above. 1567 1568Function : bl2u\_early\_platform\_setup() [mandatory] 1569~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1570 1571:: 1572 1573 Argument : meminfo *mem_info, void *plat_info 1574 Return : void 1575 1576This function executes with the MMU and data caches disabled. It is only 1577called by the primary CPU. The arguments to this function is the address 1578of the ``meminfo`` structure and platform specific info provided by BL1. 1579 1580The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1581private storage as the original memory may be subsequently overwritten by BL2U. 1582 1583On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1584to extract SCP\_BL2U image information, which is then copied into a private 1585variable. 1586 1587Function : bl2u\_plat\_arch\_setup() [mandatory] 1588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1589 1590:: 1591 1592 Argument : void 1593 Return : void 1594 1595This function executes with the MMU and data caches disabled. It is only 1596called by the primary CPU. 1597 1598The purpose of this function is to perform any architectural initialization 1599that varies across platforms, for example enabling the MMU (since the memory 1600map differs across platforms). 1601 1602Function : bl2u\_platform\_setup() [mandatory] 1603~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1604 1605:: 1606 1607 Argument : void 1608 Return : void 1609 1610This function may execute with the MMU and data caches enabled if the platform 1611port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1612called by the primary CPU. 1613 1614The purpose of this function is to perform any platform initialization 1615specific to BL2U. 1616 1617In Arm standard platforms, this function performs security setup, including 1618configuration of the TrustZone controller to allow non-secure masters access 1619to most of DRAM. Part of DRAM is reserved for secure world use. 1620 1621Function : bl2u\_plat\_handle\_scp\_bl2u() [optional] 1622~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1623 1624:: 1625 1626 Argument : void 1627 Return : int 1628 1629This function is used to perform any platform-specific actions required to 1630handle the SCP firmware. Typically it transfers the image into SCP memory using 1631a platform-specific protocol and waits until SCP executes it and signals to the 1632Application Processor (AP) for BL2U execution to continue. 1633 1634This function returns 0 on success, a negative error code otherwise. 1635This function is included if SCP\_BL2U\_BASE is defined. 1636 1637Boot Loader Stage 3-1 (BL31) 1638---------------------------- 1639 1640During cold boot, the BL31 stage is executed only by the primary CPU. This is 1641determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1642control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1643CPUs. BL31 executes at EL3 and is responsible for: 1644 1645#. Re-initializing all architectural and platform state. Although BL1 performs 1646 some of this initialization, BL31 remains resident in EL3 and must ensure 1647 that EL3 architectural and platform state is completely initialized. It 1648 should make no assumptions about the system state when it receives control. 1649 1650#. Passing control to a normal world BL image, pre-loaded at a platform- 1651 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 1652 populated by BL2 in memory to do this. 1653 1654#. Providing runtime firmware services. Currently, BL31 only implements a 1655 subset of the Power State Coordination Interface (PSCI) API as a runtime 1656 service. See Section 3.3 below for details of porting the PSCI 1657 implementation. 1658 1659#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1660 specific address by BL2. BL31 exports a set of apis that allow runtime 1661 services to specify the security state in which the next image should be 1662 executed and run the corresponding image. On ARM platforms, BL31 uses the 1663 ``bl_params`` list populated by BL2 in memory to do this. 1664 1665If BL31 is a reset vector, It also needs to handle the reset as specified in 1666section 2.2 before the tasks described above. 1667 1668The following functions must be implemented by the platform port to enable BL31 1669to perform the above tasks. 1670 1671Function : bl31\_early\_platform\_setup2() [mandatory] 1672~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1673 1674:: 1675 1676 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1677 Return : void 1678 1679This function executes with the MMU and data caches disabled. It is only called 1680by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 1681platform specific. 1682 1683In Arm standard platforms, the arguments received are : 1684 1685 arg0 - The pointer to the head of `bl_params_t` list 1686 which is list of executable images following BL31, 1687 1688 arg1 - Points to load address of SOC_FW_CONFIG if present 1689 1690 arg2 - Points to load address of HW_CONFIG if present 1691 1692 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 1693 used in release builds. 1694 1695The function runs through the `bl_param_t` list and extracts the entry point 1696information for BL32 and BL33. It also performs the following: 1697 1698- Initialize a UART (PL011 console), which enables access to the ``printf`` 1699 family of functions in BL31. 1700 1701- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1702 CCI slave interface corresponding to the cluster that includes the primary 1703 CPU. 1704 1705Function : bl31\_plat\_arch\_setup() [mandatory] 1706~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1707 1708:: 1709 1710 Argument : void 1711 Return : void 1712 1713This function executes with the MMU and data caches disabled. It is only called 1714by the primary CPU. 1715 1716The purpose of this function is to perform any architectural initialization 1717that varies across platforms. 1718 1719On Arm standard platforms, this function enables the MMU. 1720 1721Function : bl31\_platform\_setup() [mandatory] 1722~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1723 1724:: 1725 1726 Argument : void 1727 Return : void 1728 1729This function may execute with the MMU and data caches enabled if the platform 1730port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1731called by the primary CPU. 1732 1733The purpose of this function is to complete platform initialization so that both 1734BL31 runtime services and normal world software can function correctly. 1735 1736On Arm standard platforms, this function does the following: 1737 1738- Initialize the generic interrupt controller. 1739 1740 Depending on the GIC driver selected by the platform, the appropriate GICv2 1741 or GICv3 initialization will be done, which mainly consists of: 1742 1743 - Enable secure interrupts in the GIC CPU interface. 1744 - Disable the legacy interrupt bypass mechanism. 1745 - Configure the priority mask register to allow interrupts of all priorities 1746 to be signaled to the CPU interface. 1747 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1748 - Target all secure SPIs to CPU0. 1749 - Enable these secure interrupts in the GIC distributor. 1750 - Configure all other interrupts as non-secure. 1751 - Enable signaling of secure interrupts in the GIC distributor. 1752 1753- Enable system-level implementation of the generic timer counter through the 1754 memory mapped interface. 1755 1756- Grant access to the system counter timer module 1757 1758- Initialize the power controller device. 1759 1760 In particular, initialise the locks that prevent concurrent accesses to the 1761 power controller device. 1762 1763Function : bl31\_plat\_runtime\_setup() [optional] 1764~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1765 1766:: 1767 1768 Argument : void 1769 Return : void 1770 1771The purpose of this function is allow the platform to perform any BL31 runtime 1772setup just prior to BL31 exit during cold boot. The default weak 1773implementation of this function will invoke ``console_switch_state()`` to switch 1774console output to consoles marked for use in the ``runtime`` state. 1775 1776Function : bl31\_plat\_get\_next\_image\_ep\_info() [mandatory] 1777~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1778 1779:: 1780 1781 Argument : uint32_t 1782 Return : entry_point_info * 1783 1784This function may execute with the MMU and data caches enabled if the platform 1785port does the necessary initializations in ``bl31_plat_arch_setup()``. 1786 1787This function is called by ``bl31_main()`` to retrieve information provided by 1788BL2 for the next image in the security state specified by the argument. BL31 1789uses this information to pass control to that image in the specified security 1790state. This function must return a pointer to the ``entry_point_info`` structure 1791(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1792should return NULL otherwise. 1793 1794Function : bl31_plat_enable_mmu [optional] 1795~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1796 1797:: 1798 1799 Argument : uint32_t 1800 Return : void 1801 1802This function enables the MMU. The boot code calls this function with MMU and 1803caches disabled. This function should program necessary registers to enable 1804translation, and upon return, the MMU on the calling PE must be enabled. 1805 1806The function must honor flags passed in the first argument. These flags are 1807defined by the translation library, and can be found in the file 1808``include/lib/xlat_tables/xlat_mmu_helpers.h``. 1809 1810On DynamIQ systems, this function must not use stack while enabling MMU, which 1811is how the function in xlat table library version 2 is implementated. 1812 1813Function : plat\_get\_syscnt\_freq2() [mandatory] 1814~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1815 1816:: 1817 1818 Argument : void 1819 Return : unsigned int 1820 1821This function is used by the architecture setup code to retrieve the counter 1822frequency for the CPU's generic timer. This value will be programmed into the 1823``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 1824of the system counter, which is retrieved from the first entry in the frequency 1825modes table. 1826 1827#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional] 1828~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1829 1830When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 1831bytes) aligned to the cache line boundary that should be allocated per-cpu to 1832accommodate all the bakery locks. 1833 1834If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 1835calculates the size of the ``bakery_lock`` input section, aligns it to the 1836nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 1837and stores the result in a linker symbol. This constant prevents a platform 1838from relying on the linker and provide a more efficient mechanism for 1839accessing per-cpu bakery lock information. 1840 1841If this constant is defined and its value is not equal to the value 1842calculated by the linker then a link time assertion is raised. A compile time 1843assertion is raised if the value of the constant is not aligned to the cache 1844line boundary. 1845 1846SDEI porting requirements 1847~~~~~~~~~~~~~~~~~~~~~~~~~ 1848 1849The SDEI dispatcher requires the platform to provide the following macros 1850and functions, of which some are optional, and some others mandatory. 1851 1852Macros 1853...... 1854 1855Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 1856^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1857 1858This macro must be defined to the EL3 exception priority level associated with 1859Normal SDEI events on the platform. This must have a higher value (therefore of 1860lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 1861 1862Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 1863^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1864 1865This macro must be defined to the EL3 exception priority level associated with 1866Critical SDEI events on the platform. This must have a lower value (therefore of 1867higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 1868 1869**Note**: SDEI exception priorities must be the lowest among Secure priorities. 1870Among the SDEI exceptions, Critical SDEI priority must be higher than Normal 1871SDEI priority. 1872 1873Functions 1874......... 1875 1876Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 1877^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1878 1879:: 1880 1881 Argument: uintptr_t 1882 Return: int 1883 1884This function validates the address of client entry points provided for both 1885event registration and *Complete and Resume* SDEI calls. The function takes one 1886argument, which is the address of the handler the SDEI client requested to 1887register. The function must return ``0`` for successful validation, or ``-1`` 1888upon failure. 1889 1890The default implementation always returns ``0``. On Arm platforms, this function 1891is implemented to translate the entry point to physical address, and further to 1892ensure that the address is located in Non-secure DRAM. 1893 1894Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 1895^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1896 1897:: 1898 1899 Argument: uint64_t 1900 Argument: unsigned int 1901 Return: void 1902 1903SDEI specification requires that a PE comes out of reset with the events masked. 1904The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 1905the PE. No SDEI events can be dispatched until such time. 1906 1907Should a PE receive an interrupt that was bound to an SDEI event while the 1908events are masked on the PE, the dispatcher implementation invokes the function 1909``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 1910interrupt and the interrupt ID are passed as parameters. 1911 1912The default implementation only prints out a warning message. 1913 1914Power State Coordination Interface (in BL31) 1915-------------------------------------------- 1916 1917The TF-A implementation of the PSCI API is based around the concept of a 1918*power domain*. A *power domain* is a CPU or a logical group of CPUs which 1919share some state on which power management operations can be performed as 1920specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 1921a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 1922*power domains* are arranged in a hierarchical tree structure and each 1923*power domain* can be identified in a system by the cpu index of any CPU that 1924is part of that domain and a *power domain level*. A processing element (for 1925example, a CPU) is at level 0. If the *power domain* node above a CPU is a 1926logical grouping of CPUs that share some state, then level 1 is that group of 1927CPUs (for example, a cluster), and level 2 is a group of clusters (for 1928example, the system). More details on the power domain topology and its 1929organization can be found in `Power Domain Topology Design`_. 1930 1931BL31's platform initialization code exports a pointer to the platform-specific 1932power management operations required for the PSCI implementation to function 1933correctly. This information is populated in the ``plat_psci_ops`` structure. The 1934PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 1935power management operations on the power domains. For example, the target 1936CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 1937handler (if present) is called for the CPU power domain. 1938 1939The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 1940describe composite power states specific to a platform. The PSCI implementation 1941defines a generic representation of the power-state parameter viz which is an 1942array of local power states where each index corresponds to a power domain 1943level. Each entry contains the local power state the power domain at that power 1944level could enter. It depends on the ``validate_power_state()`` handler to 1945convert the power-state parameter (possibly encoding a composite power state) 1946passed in a PSCI ``CPU_SUSPEND`` call to this representation. 1947 1948The following functions form part of platform port of PSCI functionality. 1949 1950Function : plat\_psci\_stat\_accounting\_start() [optional] 1951~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1952 1953:: 1954 1955 Argument : const psci_power_state_t * 1956 Return : void 1957 1958This is an optional hook that platforms can implement for residency statistics 1959accounting before entering a low power state. The ``pwr_domain_state`` field of 1960``state_info`` (first argument) can be inspected if stat accounting is done 1961differently at CPU level versus higher levels. As an example, if the element at 1962index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 1963state, special hardware logic may be programmed in order to keep track of the 1964residency statistics. For higher levels (array indices > 0), the residency 1965statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 1966default implementation will use PMF to capture timestamps. 1967 1968Function : plat\_psci\_stat\_accounting\_stop() [optional] 1969~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1970 1971:: 1972 1973 Argument : const psci_power_state_t * 1974 Return : void 1975 1976This is an optional hook that platforms can implement for residency statistics 1977accounting after exiting from a low power state. The ``pwr_domain_state`` field 1978of ``state_info`` (first argument) can be inspected if stat accounting is done 1979differently at CPU level versus higher levels. As an example, if the element at 1980index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 1981state, special hardware logic may be programmed in order to keep track of the 1982residency statistics. For higher levels (array indices > 0), the residency 1983statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 1984default implementation will use PMF to capture timestamps. 1985 1986Function : plat\_psci\_stat\_get\_residency() [optional] 1987~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1988 1989:: 1990 1991 Argument : unsigned int, const psci_power_state_t *, int 1992 Return : u_register_t 1993 1994This is an optional interface that is is invoked after resuming from a low power 1995state and provides the time spent resident in that low power state by the power 1996domain at a particular power domain level. When a CPU wakes up from suspend, 1997all its parent power domain levels are also woken up. The generic PSCI code 1998invokes this function for each parent power domain that is resumed and it 1999identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2000argument) describes the low power state that the power domain has resumed from. 2001The current CPU is the first CPU in the power domain to resume from the low 2002power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2003CPU in the power domain to suspend and may be needed to calculate the residency 2004for that power domain. 2005 2006Function : plat\_get\_target\_pwr\_state() [optional] 2007~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2008 2009:: 2010 2011 Argument : unsigned int, const plat_local_state_t *, unsigned int 2012 Return : plat_local_state_t 2013 2014The PSCI generic code uses this function to let the platform participate in 2015state coordination during a power management operation. The function is passed 2016a pointer to an array of platform specific local power state ``states`` (second 2017argument) which contains the requested power state for each CPU at a particular 2018power domain level ``lvl`` (first argument) within the power domain. The function 2019is expected to traverse this array of upto ``ncpus`` (third argument) and return 2020a coordinated target power state by the comparing all the requested power 2021states. The target power state should not be deeper than any of the requested 2022power states. 2023 2024A weak definition of this API is provided by default wherein it assumes 2025that the platform assigns a local state value in order of increasing depth 2026of the power state i.e. for two power states X & Y, if X < Y 2027then X represents a shallower power state than Y. As a result, the 2028coordinated target local power state for a power domain will be the minimum 2029of the requested local power state values. 2030 2031Function : plat\_get\_power\_domain\_tree\_desc() [mandatory] 2032~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2033 2034:: 2035 2036 Argument : void 2037 Return : const unsigned char * 2038 2039This function returns a pointer to the byte array containing the power domain 2040topology tree description. The format and method to construct this array are 2041described in `Power Domain Topology Design`_. The BL31 PSCI initilization code 2042requires this array to be described by the platform, either statically or 2043dynamically, to initialize the power domain topology tree. In case the array 2044is populated dynamically, then plat\_core\_pos\_by\_mpidr() and 2045plat\_my\_core\_pos() should also be implemented suitably so that the topology 2046tree description matches the CPU indices returned by these APIs. These APIs 2047together form the platform interface for the PSCI topology framework. 2048 2049Function : plat\_setup\_psci\_ops() [mandatory] 2050~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2051 2052:: 2053 2054 Argument : uintptr_t, const plat_psci_ops ** 2055 Return : int 2056 2057This function may execute with the MMU and data caches enabled if the platform 2058port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2059called by the primary CPU. 2060 2061This function is called by PSCI initialization code. Its purpose is to let 2062the platform layer know about the warm boot entrypoint through the 2063``sec_entrypoint`` (first argument) and to export handler routines for 2064platform-specific psci power management actions by populating the passed 2065pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2066 2067A description of each member of this structure is given below. Please refer to 2068the Arm FVP specific implementation of these handlers in 2069`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the 2070platform wants to support, the associated operation or operations in this 2071structure must be provided and implemented (Refer section 4 of 2072`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI 2073function in a platform port, the operation should be removed from this 2074structure instead of providing an empty implementation. 2075 2076plat\_psci\_ops.cpu\_standby() 2077.............................. 2078 2079Perform the platform-specific actions to enter the standby state for a cpu 2080indicated by the passed argument. This provides a fast path for CPU standby 2081wherein overheads of PSCI state management and lock acquistion is avoided. 2082For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2083the suspend state type specified in the ``power-state`` parameter should be 2084STANDBY and the target power domain level specified should be the CPU. The 2085handler should put the CPU into a low power retention state (usually by 2086issuing a wfi instruction) and ensure that it can be woken up from that 2087state by a normal interrupt. The generic code expects the handler to succeed. 2088 2089plat\_psci\_ops.pwr\_domain\_on() 2090................................. 2091 2092Perform the platform specific actions to power on a CPU, specified 2093by the ``MPIDR`` (first argument). The generic code expects the platform to 2094return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure. 2095 2096plat\_psci\_ops.pwr\_domain\_off() 2097.................................. 2098 2099Perform the platform specific actions to prepare to power off the calling CPU 2100and its higher parent power domain levels as indicated by the ``target_state`` 2101(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2102 2103The ``target_state`` encodes the platform coordinated target local power states 2104for the CPU power domain and its parent power domain levels. The handler 2105needs to perform power management operation corresponding to the local state 2106at each power level. 2107 2108For this handler, the local power state for the CPU power domain will be a 2109power down state where as it could be either power down, retention or run state 2110for the higher power domain levels depending on the result of state 2111coordination. The generic code expects the handler to succeed. 2112 2113plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] 2114................................................................. 2115 2116This optional function may be used as a performance optimization to replace 2117or complement pwr_domain_suspend() on some platforms. Its calling semantics 2118are identical to pwr_domain_suspend(), except the PSCI implementation only 2119calls this function when suspending to a power down state, and it guarantees 2120that data caches are enabled. 2121 2122When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2123before calling pwr_domain_suspend(). If the target_state corresponds to a 2124power down state and it is safe to perform some or all of the platform 2125specific actions in that function with data caches enabled, it may be more 2126efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2127= 1, data caches remain enabled throughout, and so there is no advantage to 2128moving platform specific actions to this function. 2129 2130plat\_psci\_ops.pwr\_domain\_suspend() 2131...................................... 2132 2133Perform the platform specific actions to prepare to suspend the calling 2134CPU and its higher parent power domain levels as indicated by the 2135``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2136API implementation. 2137 2138The ``target_state`` has a similar meaning as described in 2139the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2140target local power states for the CPU power domain and its parent 2141power domain levels. The handler needs to perform power management operation 2142corresponding to the local state at each power level. The generic code 2143expects the handler to succeed. 2144 2145The difference between turning a power domain off versus suspending it is that 2146in the former case, the power domain is expected to re-initialize its state 2147when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2148case, the power domain is expected to save enough state so that it can resume 2149execution by restoring this state when its powered on (see 2150``pwr_domain_suspend_finish()``). 2151 2152When suspending a core, the platform can also choose to power off the GICv3 2153Redistributor and ITS through an implementation-defined sequence. To achieve 2154this safely, the ITS context must be saved first. The architectural part is 2155implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2156sequence is implementation defined and it is therefore the responsibility of 2157the platform code to implement the necessary sequence. Then the GIC 2158Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2159Powering off the Redistributor requires the implementation to support it and it 2160is the responsibility of the platform code to execute the right implementation 2161defined sequence. 2162 2163When a system suspend is requested, the platform can also make use of the 2164``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2165it has saved the context of the Redistributors and ITS of all the cores in the 2166system. The context of the Distributor can be large and may require it to be 2167allocated in a special area if it cannot fit in the platform's global static 2168data, for example in DRAM. The Distributor can then be powered down using an 2169implementation-defined sequence. 2170 2171plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi() 2172............................................. 2173 2174This is an optional function and, if implemented, is expected to perform 2175platform specific actions including the ``wfi`` invocation which allows the 2176CPU to powerdown. Since this function is invoked outside the PSCI locks, 2177the actions performed in this hook must be local to the CPU or the platform 2178must ensure that races between multiple CPUs cannot occur. 2179 2180The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2181operation and it encodes the platform coordinated target local power states for 2182the CPU power domain and its parent power domain levels. This function must 2183not return back to the caller. 2184 2185If this function is not implemented by the platform, PSCI generic 2186implementation invokes ``psci_power_down_wfi()`` for power down. 2187 2188plat\_psci\_ops.pwr\_domain\_on\_finish() 2189......................................... 2190 2191This function is called by the PSCI implementation after the calling CPU is 2192powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2193It performs the platform-specific setup required to initialize enough state for 2194this CPU to enter the normal world and also provide secure runtime firmware 2195services. 2196 2197The ``target_state`` (first argument) is the prior state of the power domains 2198immediately before the CPU was turned on. It indicates which power domains 2199above the CPU might require initialization due to having previously been in 2200low power states. The generic code expects the handler to succeed. 2201 2202plat\_psci\_ops.pwr\_domain\_suspend\_finish() 2203.............................................. 2204 2205This function is called by the PSCI implementation after the calling CPU is 2206powered on and released from reset in response to an asynchronous wakeup 2207event, for example a timer interrupt that was programmed by the CPU during the 2208``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2209setup required to restore the saved state for this CPU to resume execution 2210in the normal world and also provide secure runtime firmware services. 2211 2212The ``target_state`` (first argument) has a similar meaning as described in 2213the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2214to succeed. 2215 2216If the Distributor, Redistributors or ITS have been powered off as part of a 2217suspend, their context must be restored in this function in the reverse order 2218to how they were saved during suspend sequence. 2219 2220plat\_psci\_ops.system\_off() 2221............................. 2222 2223This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2224call. It performs the platform-specific system poweroff sequence after 2225notifying the Secure Payload Dispatcher. 2226 2227plat\_psci\_ops.system\_reset() 2228............................... 2229 2230This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2231call. It performs the platform-specific system reset sequence after 2232notifying the Secure Payload Dispatcher. 2233 2234plat\_psci\_ops.validate\_power\_state() 2235........................................ 2236 2237This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2238call to validate the ``power_state`` parameter of the PSCI API and if valid, 2239populate it in ``req_state`` (second argument) array as power domain level 2240specific local states. If the ``power_state`` is invalid, the platform must 2241return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the 2242normal world PSCI client. 2243 2244plat\_psci\_ops.validate\_ns\_entrypoint() 2245.......................................... 2246 2247This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2248``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2249parameter passed by the normal world. If the ``entry_point`` is invalid, 2250the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is 2251propagated back to the normal world PSCI client. 2252 2253plat\_psci\_ops.get\_sys\_suspend\_power\_state() 2254................................................. 2255 2256This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2257call to get the ``req_state`` parameter from platform which encodes the power 2258domain level specific local states to suspend to system affinity level. The 2259``req_state`` will be utilized to do the PSCI state coordination and 2260``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2261enter system suspend. 2262 2263plat\_psci\_ops.get\_pwr\_lvl\_state\_idx() 2264........................................... 2265 2266This is an optional function and, if implemented, is invoked by the PSCI 2267implementation to convert the ``local_state`` (first argument) at a specified 2268``pwr_lvl`` (second argument) to an index between 0 and 2269``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2270supports more than two local power states at each power domain level, that is 2271``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2272local power states. 2273 2274plat\_psci\_ops.translate\_power\_state\_by\_mpidr() 2275.................................................... 2276 2277This is an optional function and, if implemented, verifies the ``power_state`` 2278(second argument) parameter of the PSCI API corresponding to a target power 2279domain. The target power domain is identified by using both ``MPIDR`` (first 2280argument) and the power domain level encoded in ``power_state``. The power domain 2281level specific local states are to be extracted from ``power_state`` and be 2282populated in the ``output_state`` (third argument) array. The functionality 2283is similar to the ``validate_power_state`` function described above and is 2284envisaged to be used in case the validity of ``power_state`` depend on the 2285targeted power domain. If the ``power_state`` is invalid for the targeted power 2286domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this 2287function is not implemented, then the generic implementation relies on 2288``validate_power_state`` function to translate the ``power_state``. 2289 2290This function can also be used in case the platform wants to support local 2291power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY 2292APIs as described in Section 5.18 of `PSCI`_. 2293 2294plat\_psci\_ops.get\_node\_hw\_state() 2295...................................... 2296 2297This is an optional function. If implemented this function is intended to return 2298the power state of a node (identified by the first parameter, the ``MPIDR``) in 2299the power domain topology (identified by the second parameter, ``power_level``), 2300as retrieved from a power controller or equivalent component on the platform. 2301Upon successful completion, the implementation must map and return the final 2302status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2303must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2304appropriate. 2305 2306Implementations are not expected to handle ``power_levels`` greater than 2307``PLAT_MAX_PWR_LVL``. 2308 2309plat\_psci\_ops.system\_reset2() 2310................................ 2311 2312This is an optional function. If implemented this function is 2313called during the ``SYSTEM_RESET2`` call to perform a reset 2314based on the first parameter ``reset_type`` as specified in 2315`PSCI`_. The parameter ``cookie`` can be used to pass additional 2316reset information. If the ``reset_type`` is not supported, the 2317function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2318resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2319and vendor reset can return other PSCI error codes as defined 2320in `PSCI`_. On success this function will not return. 2321 2322plat\_psci\_ops.write\_mem\_protect() 2323.................................... 2324 2325This is an optional function. If implemented it enables or disables the 2326``MEM_PROTECT`` functionality based on the value of ``val``. 2327A non-zero value enables ``MEM_PROTECT`` and a value of zero 2328disables it. Upon encountering failures it must return a negative value 2329and on success it must return 0. 2330 2331plat\_psci\_ops.read\_mem\_protect() 2332..................................... 2333 2334This is an optional function. If implemented it returns the current 2335state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2336failures it must return a negative value and on success it must 2337return 0. 2338 2339plat\_psci\_ops.mem\_protect\_chk() 2340................................... 2341 2342This is an optional function. If implemented it checks if a memory 2343region defined by a base address ``base`` and with a size of ``length`` 2344bytes is protected by ``MEM_PROTECT``. If the region is protected 2345then it must return 0, otherwise it must return a negative number. 2346 2347Interrupt Management framework (in BL31) 2348---------------------------------------- 2349 2350BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2351generated in either security state and targeted to EL1 or EL2 in the non-secure 2352state or EL3/S-EL1 in the secure state. The design of this framework is 2353described in the `IMF Design Guide`_ 2354 2355A platform should export the following APIs to support the IMF. The following 2356text briefly describes each api and its implementation in Arm standard 2357platforms. The API implementation depends upon the type of interrupt controller 2358present in the platform. Arm standard platform layer supports both 2359`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2360and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2361FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2362``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in 2363`User Guide`_ for more details). 2364 2365See also: `Interrupt Controller Abstraction APIs`__. 2366 2367.. __: platform-interrupt-controller-API.rst 2368 2369Function : plat\_interrupt\_type\_to\_line() [mandatory] 2370~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2371 2372:: 2373 2374 Argument : uint32_t, uint32_t 2375 Return : uint32_t 2376 2377The Arm processor signals an interrupt exception either through the IRQ or FIQ 2378interrupt line. The specific line that is signaled depends on how the interrupt 2379controller (IC) reports different interrupt types from an execution context in 2380either security state. The IMF uses this API to determine which interrupt line 2381the platform IC uses to signal each type of interrupt supported by the framework 2382from a given security state. This API must be invoked at EL3. 2383 2384The first parameter will be one of the ``INTR_TYPE_*`` values (see 2385`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2386security state of the originating execution context. The return result is the 2387bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2388FIQ=2. 2389 2390In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2391configured as FIQs and Non-secure interrupts as IRQs from either security 2392state. 2393 2394In the case of Arm standard platforms using GICv3, the interrupt line to be 2395configured depends on the security state of the execution context when the 2396interrupt is signalled and are as follows: 2397 2398- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2399 NS-EL0/1/2 context. 2400- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2401 in the NS-EL0/1/2 context. 2402- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2403 context. 2404 2405Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory] 2406~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2407 2408:: 2409 2410 Argument : void 2411 Return : uint32_t 2412 2413This API returns the type of the highest priority pending interrupt at the 2414platform IC. The IMF uses the interrupt type to retrieve the corresponding 2415handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2416pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2417``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2418 2419In the case of Arm standard platforms using GICv2, the *Highest Priority 2420Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2421the pending interrupt. The type of interrupt depends upon the id value as 2422follows. 2423 2424#. id < 1022 is reported as a S-EL1 interrupt 2425#. id = 1022 is reported as a Non-secure interrupt. 2426#. id = 1023 is reported as an invalid interrupt type. 2427 2428In the case of Arm standard platforms using GICv3, the system register 2429``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2430is read to determine the id of the pending interrupt. The type of interrupt 2431depends upon the id value as follows. 2432 2433#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2434#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2435#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2436#. All other interrupt id's are reported as EL3 interrupt. 2437 2438Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory] 2439~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2440 2441:: 2442 2443 Argument : void 2444 Return : uint32_t 2445 2446This API returns the id of the highest priority pending interrupt at the 2447platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2448pending. 2449 2450In the case of Arm standard platforms using GICv2, the *Highest Priority 2451Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2452pending interrupt. The id that is returned by API depends upon the value of 2453the id read from the interrupt controller as follows. 2454 2455#. id < 1022. id is returned as is. 2456#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2457 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2458 This id is returned by the API. 2459#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2460 2461In the case of Arm standard platforms using GICv3, if the API is invoked from 2462EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2463group 0 Register*, is read to determine the id of the pending interrupt. The id 2464that is returned by API depends upon the value of the id read from the 2465interrupt controller as follows. 2466 2467#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2468#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2469 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2470 Register* is read to determine the id of the group 1 interrupt. This id 2471 is returned by the API as long as it is a valid interrupt id 2472#. If the id is any of the special interrupt identifiers, 2473 ``INTR_ID_UNAVAILABLE`` is returned. 2474 2475When the API invoked from S-EL1 for GICv3 systems, the id read from system 2476register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2477Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else 2478``INTR_ID_UNAVAILABLE`` is returned. 2479 2480Function : plat\_ic\_acknowledge\_interrupt() [mandatory] 2481~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2482 2483:: 2484 2485 Argument : void 2486 Return : uint32_t 2487 2488This API is used by the CPU to indicate to the platform IC that processing of 2489the highest pending interrupt has begun. It should return the raw, unmodified 2490value obtained from the interrupt controller when acknowledging an interrupt. 2491The actual interrupt number shall be extracted from this raw value using the API 2492`plat_ic_get_interrupt_id()`__. 2493 2494.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2495 2496This function in Arm standard platforms using GICv2, reads the *Interrupt 2497Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2498priority pending interrupt from pending to active in the interrupt controller. 2499It returns the value read from the ``GICC_IAR``, unmodified. 2500 2501In the case of Arm standard platforms using GICv3, if the API is invoked 2502from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2503Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2504reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2505group 1*. The read changes the state of the highest pending interrupt from 2506pending to active in the interrupt controller. The value read is returned 2507unmodified. 2508 2509The TSP uses this API to start processing of the secure physical timer 2510interrupt. 2511 2512Function : plat\_ic\_end\_of\_interrupt() [mandatory] 2513~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2514 2515:: 2516 2517 Argument : uint32_t 2518 Return : void 2519 2520This API is used by the CPU to indicate to the platform IC that processing of 2521the interrupt corresponding to the id (passed as the parameter) has 2522finished. The id should be the same as the id returned by the 2523``plat_ic_acknowledge_interrupt()`` API. 2524 2525Arm standard platforms write the id to the *End of Interrupt Register* 2526(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2527system register in case of GICv3 depending on where the API is invoked from, 2528EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2529controller. 2530 2531The TSP uses this API to finish processing of the secure physical timer 2532interrupt. 2533 2534Function : plat\_ic\_get\_interrupt\_type() [mandatory] 2535~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2536 2537:: 2538 2539 Argument : uint32_t 2540 Return : uint32_t 2541 2542This API returns the type of the interrupt id passed as the parameter. 2543``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2544interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2545returned depending upon how the interrupt has been configured by the platform 2546IC. This API must be invoked at EL3. 2547 2548Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2549and Non-secure interrupts as Group1 interrupts. It reads the group value 2550corresponding to the interrupt id from the relevant *Interrupt Group Register* 2551(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2552 2553In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2554Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2555(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2556as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2557 2558Crash Reporting mechanism (in BL31) 2559----------------------------------- 2560 2561NOTE: This section assumes that your platform is enabling the MULTI_CONSOLE_API 2562flag in its platform.mk. Not using this flag is deprecated for new platforms. 2563 2564BL31 implements a crash reporting mechanism which prints the various registers 2565of the CPU to enable quick crash analysis and debugging. By default, the 2566definitions in ``plat/common/aarch64/platform\_helpers.S`` will cause the crash 2567output to be routed over the normal console infrastructure and get printed on 2568consoles configured to output in crash state. ``console_set_scope()`` can be 2569used to control whether a console is used for crash output. 2570 2571In some cases (such as debugging very early crashes that happen before the 2572normal boot console can be set up), platforms may want to control crash output 2573more explicitly. For these, the following functions can be overridden by 2574platform code. They are executed outside of a C environment and without a stack. 2575 2576Function : plat\_crash\_console\_init 2577~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2578 2579:: 2580 2581 Argument : void 2582 Return : int 2583 2584This API is used by the crash reporting mechanism to initialize the crash 2585console. It must only use the general purpose registers x0 through x7 to do the 2586initialization and returns 1 on success. 2587 2588If you are trying to debug crashes before the console driver would normally get 2589registered, you can use this to register a driver from assembly with hardcoded 2590parameters. For example, you could register the 16550 driver like this: 2591 2592:: 2593 2594 .section .data.crash_console /* Reserve space for console structure */ 2595 crash_console: 2596 .zero 6 * 8 /* console_16550_t has 6 8-byte words */ 2597 func plat_crash_console_init 2598 ldr x0, =YOUR_16550_BASE_ADDR 2599 ldr x1, =YOUR_16550_SRCCLK_IN_HZ 2600 ldr x2, =YOUR_16550_TARGET_BAUD_RATE 2601 adrp x3, crash_console 2602 add x3, x3, :lo12:crash_console 2603 b console_16550_register /* tail call, returns 1 on success */ 2604 endfunc plat_crash_console_init 2605 2606If you're trying to debug crashes in BL1, you can call the console_xxx_core_init 2607function exported by some console drivers from here. 2608 2609Function : plat\_crash\_console\_putc 2610~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2611 2612:: 2613 2614 Argument : int 2615 Return : int 2616 2617This API is used by the crash reporting mechanism to print a character on the 2618designated crash console. It must only use general purpose registers x1 and 2619x2 to do its work. The parameter and the return value are in general purpose 2620register x0. 2621 2622If you have registered a normal console driver in ``plat_crash_console_init``, 2623you can keep the default implementation here (which calls ``console_putc()``). 2624 2625If you're trying to debug crashes in BL1, you can call the console_xxx_core_putc 2626function exported by some console drivers from here. 2627 2628Function : plat\_crash\_console\_flush 2629~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2630 2631:: 2632 2633 Argument : void 2634 Return : int 2635 2636This API is used by the crash reporting mechanism to force write of all buffered 2637data on the designated crash console. It should only use general purpose 2638registers x0 through x5 to do its work. The return value is 0 on successful 2639completion; otherwise the return value is -1. 2640 2641If you have registered a normal console driver in ``plat_crash_console_init``, 2642you can keep the default implementation here (which calls ``console_flush()``). 2643 2644If you're trying to debug crashes in BL1, you can call the console_xx_core_flush 2645function exported by some console drivers from here. 2646 2647Extternal Abort handling and RAS Support 2648---------------------------------------- 2649 2650Function : plat_ea_handler 2651~~~~~~~~~~~~~~~~~~~~~~~~~~ 2652 2653:: 2654 2655 Argument : int 2656 Argument : uint64_t 2657 Argument : void * 2658 Argument : void * 2659 Argument : uint64_t 2660 Return : void 2661 2662This function is invoked by the RAS framework for the platform to handle an 2663External Abort received at EL3. The intention of the function is to attempt to 2664resolve the cause of External Abort and return; if that's not possible, to 2665initiate orderly shutdown of the system. 2666 2667The first parameter (``int ea_reason``) indicates the reason for External Abort. 2668Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 2669 2670The second parameter (``uint64_t syndrome``) is the respective syndrome 2671presented to EL3 after having received the External Abort. Depending on the 2672nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 2673can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 2674 2675The third parameter (``void *cookie``) is unused for now. The fourth parameter 2676(``void *handle``) is a pointer to the preempted context. The fifth parameter 2677(``uint64_t flags``) indicates the preempted security state. These parameters 2678are received from the top-level exception handler. 2679 2680If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this 2681function iterates through RAS handlers registered by the platform. If any of the 2682RAS handlers resolve the External Abort, no further action is taken. 2683 2684If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers 2685could resolve the External Abort, the default implementation prints an error 2686message, and panics. 2687 2688Function : plat_handle_uncontainable_ea 2689~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2690 2691:: 2692 2693 Argument : int 2694 Argument : uint64_t 2695 Return : void 2696 2697This function is invoked by the RAS framework when an External Abort of 2698Uncontainable type is received at EL3. Due to the critical nature of 2699Uncontainable errors, the intention of this function is to initiate orderly 2700shutdown of the system, and is not expected to return. 2701 2702This function must be implemented in assembly. 2703 2704The first and second parameters are the same as that of ``plat_ea_handler``. 2705 2706The default implementation of this function calls 2707``report_unhandled_exception``. 2708 2709Function : plat_handle_double_fault 2710~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2711 2712:: 2713 2714 Argument : int 2715 Argument : uint64_t 2716 Return : void 2717 2718This function is invoked by the RAS framework when another External Abort is 2719received at EL3 while one is already being handled. I.e., a call to 2720``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 2721this function is to initiate orderly shutdown of the system, and is not expected 2722recover or return. 2723 2724This function must be implemented in assembly. 2725 2726The first and second parameters are the same as that of ``plat_ea_handler``. 2727 2728The default implementation of this function calls 2729``report_unhandled_exception``. 2730 2731Function : plat_handle_el3_ea 2732~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2733 2734:: 2735 2736 Return : void 2737 2738This function is invoked when an External Abort is received while executing in 2739EL3. Due to its critical nature, the intention of this function is to initiate 2740orderly shutdown of the system, and is not expected recover or return. 2741 2742This function must be implemented in assembly. 2743 2744The default implementation of this function calls 2745``report_unhandled_exception``. 2746 2747Build flags 2748----------- 2749 2750- **ENABLE\_PLAT\_COMPAT** 2751 All the platforms ports conforming to this API specification should define 2752 the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should 2753 be disabled. For more details on compatibility layer, refer 2754 `Migration Guide`_. 2755 2756There are some build flags which can be defined by the platform to control 2757inclusion or exclusion of certain BL stages from the FIP image. These flags 2758need to be defined in the platform makefile which will get included by the 2759build system. 2760 2761- **NEED\_BL33** 2762 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2763 build option should be supplied as a build option. The platform has the 2764 option of excluding the BL33 image in the ``fip`` image by defining this flag 2765 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2766 are used, this flag will be set to ``no`` automatically. 2767 2768C Library 2769--------- 2770 2771To avoid subtle toolchain behavioral dependencies, the header files provided 2772by the compiler are not used. The software is built with the ``-nostdinc`` flag 2773to ensure no headers are included from the toolchain inadvertently. Instead the 2774required headers are included in the TF-A source tree. The library only 2775contains those C library definitions required by the local implementation. If 2776more functionality is required, the needed library functions will need to be 2777added to the local implementation. 2778 2779Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 2780been written specifically for TF-A. Fome implementation files have been obtained 2781from `FreeBSD`_, others have been written specifically for TF-A as well. The 2782files can be found in ``include/lib/libc`` and ``lib/libc``. 2783 2784SCC can be found in `http://www.simple-cc.org/`_. A copy of the `FreeBSD`_ 2785sources can be obtained from `http://github.com/freebsd/freebsd`_. 2786 2787Storage abstraction layer 2788------------------------- 2789 2790In order to improve platform independence and portability an storage abstraction 2791layer is used to load data from non-volatile platform storage. 2792 2793Each platform should register devices and their drivers via the Storage layer. 2794These drivers then need to be initialized by bootloader phases as 2795required in their respective ``blx_platform_setup()`` functions. Currently 2796storage access is only required by BL1 and BL2 phases. The ``load_image()`` 2797function uses the storage layer to access non-volatile platform storage. 2798 2799It is mandatory to implement at least one storage driver. For the Arm 2800development platforms the Firmware Image Package (FIP) driver is provided as 2801the default means to load data from storage (see the "Firmware Image Package" 2802section in the `User Guide`_). The storage layer is described in the header file 2803``include/drivers/io/io_storage.h``. The implementation of the common library 2804is in ``drivers/io/io_storage.c`` and the driver files are located in 2805``drivers/io/``. 2806 2807Each IO driver must provide ``io_dev_*`` structures, as described in 2808``drivers/io/io_driver.h``. These are returned via a mandatory registration 2809function that is called on platform initialization. The semi-hosting driver 2810implementation in ``io_semihosting.c`` can be used as an example. 2811 2812The Storage layer provides mechanisms to initialize storage devices before 2813IO operations are called. The basic operations supported by the layer 2814include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 2815Drivers do not have to implement all operations, but each platform must 2816provide at least one driver for a device capable of supporting generic 2817operations such as loading a bootloader image. 2818 2819The current implementation only allows for known images to be loaded by the 2820firmware. These images are specified by using their identifiers, as defined in 2821[include/plat/common/platform\_def.h] (or a separate header file included from 2822there). The platform layer (``plat_get_image_source()``) then returns a reference 2823to a device and a driver-specific ``spec`` which will be understood by the driver 2824to allow access to the image data. 2825 2826The layer is designed in such a way that is it possible to chain drivers with 2827other drivers. For example, file-system drivers may be implemented on top of 2828physical block devices, both represented by IO devices with corresponding 2829drivers. In such a case, the file-system "binding" with the block device may 2830be deferred until the file-system device is initialised. 2831 2832The abstraction currently depends on structures being statically allocated 2833by the drivers and callers, as the system does not yet provide a means of 2834dynamically allocating memory. This may also have the affect of limiting the 2835amount of open resources per driver. 2836 2837-------------- 2838 2839*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.* 2840 2841.. _Migration Guide: platform-migration-guide.rst 2842.. _include/plat/common/platform.h: ../include/plat/common/platform.h 2843.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D 2844.. _User Guide: user-guide.rst 2845.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h 2846.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h 2847.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S 2848.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S 2849.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 2850.. _Power Domain Topology Design: psci-pd-tree.rst 2851.. _include/common/bl\_common.h: ../include/common/bl_common.h 2852.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 2853.. _Firmware Design: firmware-design.rst 2854.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 2855.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c 2856.. _IMF Design Guide: interrupt-framework-design.rst 2857.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 2858.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 2859.. _FreeBSD: http://www.freebsd.org 2860.. _SCC: http://www.simple-cc.org/ 2861