1Xilinx Zynq UltraScale+ MPSoC 2============================= 3 4Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq 5UltraScale + MPSoC. 6The platform only uses the runtime part of TF-A as ZynqMP already has a 7BootROM (BL1) and FSBL (BL2). 8 9BL31 is TF-A. 10BL32 is an optional Secure Payload. 11BL33 is the non-secure world software (U-Boot, Linux etc). 12 13To build: 14 15.. code:: bash 16 17 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 18 19To build bl32 TSP you have to rebuild bl31 too: 20 21.. code:: bash 22 23 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd RESET_TO_BL31=1 bl31 bl32 24 25To build TF-A for JTAG DCC console: 26 27.. code:: bash 28 29 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc 30 31ZynqMP platform specific build options 32-------------------------------------- 33 34- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. 35- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. 36- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. 37- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary. 38 39- ``ZYNQMP_CONSOLE``: Select the console driver. Options: 40 41 - ``cadence``, ``cadence0``: Cadence UART 0 42 - ``cadence1`` : Cadence UART 1 43 44ZynqMP Debug behavior 45--------------------- 46 47With DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range 48due to size constraints. 49For DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location 50of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF. 51 52If the user wants to move the bl31 to a different DDR location, user can provide 53the DDR address location in the build command as follows, 54 55make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \ 56 ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> bl31 57 58 59FSBL->TF-A Parameter Passing 60---------------------------- 61 62The FSBL populates a data structure with image information for TF-A. TF-A uses 63that data to hand off to the loaded images. The address of the handoff data 64structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The 65register is free to be used by other software once TF-A has brought up 66further firmware images. 67 68Power Domain Tree 69----------------- 70 71The following power domain tree represents the power domain model used by TF-A 72for ZynqMP: 73 74:: 75 76 +-+ 77 |0| 78 +-+ 79 +-------+---+---+-------+ 80 | | | | 81 | | | | 82 v v v v 83 +-+ +-+ +-+ +-+ 84 |0| |1| |2| |3| 85 +-+ +-+ +-+ +-+ 86 87The 4 leaf power domains represent the individual A53 cores, while resources 88common to the cluster are grouped in the power domain on the top. 89