1Xilinx Zynq UltraScale+ MPSoC 2============================= 3 4Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq 5UltraScale + MPSoC. 6The platform only uses the runtime part of TF-A as ZynqMP already has a 7BootROM (BL1) and FSBL (BL2). 8 9BL31 is TF-A. 10BL32 is an optional Secure Payload. 11BL33 is the non-secure world software (U-Boot, Linux etc). 12 13To build: 14 15.. code:: bash 16 17 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 18 19To build bl32 TSP you have to rebuild bl31 too: 20 21.. code:: bash 22 23 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd RESET_TO_BL31=1 bl31 bl32 24 25To build TF-A for JTAG DCC console: 26 27.. code:: bash 28 29 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc 30 31ZynqMP platform specific build options 32-------------------------------------- 33 34- ``XILINX_OF_BOARD_DTB_ADDR`` : Specifies the base address of Device tree. 35- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. 36- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. 37- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. 38- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary. 39 40- ``ZYNQMP_CONSOLE``: Select the console driver. Options: 41 42 - ``cadence``, ``cadence0``: Cadence UART 0 43 - ``cadence1`` : Cadence UART 1 44 45ZynqMP Debug behavior 46--------------------- 47 48With DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range 49due to size constraints. 50For DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location 51of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF. By default the 52above memory range will NOT be reserved in device tree. 53 54To reserve the above memory range in device tree, the device tree base address 55must be provided during build as, 56 57make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \ 58 XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31 59 60The default DTB base address for ZynqMP platform is 0x100000. This default value 61is not set in the code and to use this default address, user still needs to 62provide it through the build command as above. 63 64If the user wants to move the bl31 to a different DDR location, user can provide 65the DDR address location using the build time parameters ZYNQMP_ATF_MEM_BASE and 66ZYNQMP_ATF_MEM_SIZE. 67 68The DDR address must be reserved in the DTB by the user, either by manually 69adding the reserved memory node, in the device tree, with the required address 70range OR let TF-A modify the device tree on the run. 71 72To let TF-A access and modify the device tree, the DTB address must be provided 73to the build command as follows, 74 75make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \ 76 ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> \ 77 XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31 78 79DDR Address Range Usage 80----------------------- 81 82When FSBL runs on RPU and TF-A is to be placed in DDR address range, 83then the user needs to make sure that the DDR address is beyond 256KB. 84In the RPU view, the first 256 KB is TCM memory. 85 86For this use case, with the minimum base address in DDR for TF-A, 87the build command example is; 88 89make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \ 90 ZYNQMP_ATF_MEM_BASE=0x40000 ZYNQMP_ATF_MEM_SIZE=<size> 91 92FSBL->TF-A Parameter Passing 93---------------------------- 94 95The FSBL populates a data structure with image information for TF-A. TF-A uses 96that data to hand off to the loaded images. The address of the handoff data 97structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The 98register is free to be used by other software once TF-A has brought up 99further firmware images. 100 101Power Domain Tree 102----------------- 103 104The following power domain tree represents the power domain model used by TF-A 105for ZynqMP: 106 107:: 108 109 +-+ 110 |0| 111 +-+ 112 +-------+---+---+-------+ 113 | | | | 114 | | | | 115 v v v v 116 +-+ +-+ +-+ +-+ 117 |0| |1| |2| |3| 118 +-+ +-+ +-+ +-+ 119 120The 4 leaf power domains represent the individual A53 cores, while resources 121common to the cluster are grouped in the power domain on the top. 122 123CUSTOM SIP service support 124-------------------------- 125 126- Dedicated SMC FID ZYNQMP_SIP_SVC_CUSTOM(0x82002000)(32-bit)/ 127 (0xC2002000)(64-bit) to be used by a custom package for 128 providing CUSTOM SIP service. 129 130- by default platform provides bare minimum definition for 131 custom_smc_handler in this service. 132 133- to use this service, custom package should implement their 134 smc handler with the name custom_smc_handler. once custom package is 135 included in TF-A build, their definition of custom_smc_handler is 136 enabled. 137 138Custom package makefile fragment inclusion in TF-A build 139-------------------------------------------------------- 140 141- custom package is not directly part of TF-A source. 142 143- <CUSTOM_PKG_PATH> is the location at which user clones a 144 custom package locally. 145 146- custom package needs to implement makefile fragment named 147 custom_pkg.mk so as to get included in TF-A build. 148 149- custom_pkg.mk specify all the rules to include custom package 150 specific header files, dependent libs, source files that are 151 supposed to be included in TF-A build. 152 153- when <CUSTOM_PKG_PATH> is specified in TF-A build command, 154 custom_pkg.mk is included from <CUSTOM_PKG_PATH> in TF-A build. 155 156- TF-A build command: 157 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 158 bl31 CUSTOM_PKG_PATH=<...> 159