124dba2b3SPaul BeesleyXilinx Zynq UltraScale+ MPSoC 224dba2b3SPaul Beesley============================= 36f625747SDouglas Raillard 44def07d5SDan HandleyTrusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq 56f625747SDouglas RaillardUltraScale + MPSoC. 64def07d5SDan HandleyThe platform only uses the runtime part of TF-A as ZynqMP already has a 76f625747SDouglas RaillardBootROM (BL1) and FSBL (BL2). 86f625747SDouglas Raillard 94def07d5SDan HandleyBL31 is TF-A. 106f625747SDouglas RaillardBL32 is an optional Secure Payload. 116f625747SDouglas RaillardBL33 is the non-secure world software (U-Boot, Linux etc). 126f625747SDouglas Raillard 136f625747SDouglas RaillardTo build: 146f625747SDouglas Raillard 156f625747SDouglas Raillard.. code:: bash 166f625747SDouglas Raillard 178cff97d1SAntonio Nino Diaz make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31 186f625747SDouglas Raillard 196f625747SDouglas RaillardTo build bl32 TSP you have to rebuild bl31 too: 206f625747SDouglas Raillard 216f625747SDouglas Raillard.. code:: bash 226f625747SDouglas Raillard 238cff97d1SAntonio Nino Diaz make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32 246f625747SDouglas Raillard 25*c00baeecSVenkatesh Yadav AbbarapuTo build TF-A for JTAG DCC console: 26*c00baeecSVenkatesh Yadav Abbarapu 27*c00baeecSVenkatesh Yadav Abbarapu.. code:: bash 28*c00baeecSVenkatesh Yadav Abbarapu 29*c00baeecSVenkatesh Yadav Abbarapu make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc 30*c00baeecSVenkatesh Yadav Abbarapu 316f625747SDouglas RaillardZynqMP platform specific build options 3224dba2b3SPaul Beesley-------------------------------------- 336f625747SDouglas Raillard 346f625747SDouglas Raillard- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. 356f625747SDouglas Raillard- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. 366f625747SDouglas Raillard- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. 376f625747SDouglas Raillard- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary. 386f625747SDouglas Raillard 396f625747SDouglas Raillard- ``ZYNQMP_CONSOLE``: Select the console driver. Options: 406f625747SDouglas Raillard 416f625747SDouglas Raillard - ``cadence``, ``cadence0``: Cadence UART 0 426f625747SDouglas Raillard - ``cadence1`` : Cadence UART 1 436f625747SDouglas Raillard 444def07d5SDan HandleyFSBL->TF-A Parameter Passing 4524dba2b3SPaul Beesley---------------------------- 466f625747SDouglas Raillard 474def07d5SDan HandleyThe FSBL populates a data structure with image information for TF-A. TF-A uses 484def07d5SDan Handleythat data to hand off to the loaded images. The address of the handoff data 496f625747SDouglas Raillardstructure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The 504def07d5SDan Handleyregister is free to be used by other software once TF-A has brought up 516f625747SDouglas Raillardfurther firmware images. 526f625747SDouglas Raillard 536f625747SDouglas RaillardPower Domain Tree 5424dba2b3SPaul Beesley----------------- 556f625747SDouglas Raillard 564def07d5SDan HandleyThe following power domain tree represents the power domain model used by TF-A 574def07d5SDan Handleyfor ZynqMP: 586f625747SDouglas Raillard 596f625747SDouglas Raillard:: 606f625747SDouglas Raillard 616f625747SDouglas Raillard +-+ 626f625747SDouglas Raillard |0| 636f625747SDouglas Raillard +-+ 646f625747SDouglas Raillard +-------+---+---+-------+ 656f625747SDouglas Raillard | | | | 666f625747SDouglas Raillard | | | | 676f625747SDouglas Raillard v v v v 686f625747SDouglas Raillard +-+ +-+ +-+ +-+ 696f625747SDouglas Raillard |0| |1| |2| |3| 706f625747SDouglas Raillard +-+ +-+ +-+ +-+ 716f625747SDouglas Raillard 726f625747SDouglas RaillardThe 4 leaf power domains represent the individual A53 cores, while resources 736f625747SDouglas Raillardcommon to the cluster are grouped in the power domain on the top. 74