1*6f625747SDouglas RaillardARM Trusted Firmware for Xilinx Zynq UltraScale+ MPSoC 2*6f625747SDouglas Raillard====================================================== 3*6f625747SDouglas Raillard 4*6f625747SDouglas RaillardARM Trusted Firmware implements the EL3 firmware layer for Xilinx Zynq 5*6f625747SDouglas RaillardUltraScale + MPSoC. 6*6f625747SDouglas RaillardThe platform only uses the runtime part of ATF as ZynqMP already has a 7*6f625747SDouglas RaillardBootROM (BL1) and FSBL (BL2). 8*6f625747SDouglas Raillard 9*6f625747SDouglas RaillardBL31 is ATF. 10*6f625747SDouglas RaillardBL32 is an optional Secure Payload. 11*6f625747SDouglas RaillardBL33 is the non-secure world software (U-Boot, Linux etc). 12*6f625747SDouglas Raillard 13*6f625747SDouglas RaillardTo build: 14*6f625747SDouglas Raillard 15*6f625747SDouglas Raillard.. code:: bash 16*6f625747SDouglas Raillard 17*6f625747SDouglas Raillard make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31 18*6f625747SDouglas Raillard 19*6f625747SDouglas RaillardTo build bl32 TSP you have to rebuild bl31 too: 20*6f625747SDouglas Raillard 21*6f625747SDouglas Raillard.. code:: bash 22*6f625747SDouglas Raillard 23*6f625747SDouglas Raillard make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32 24*6f625747SDouglas Raillard 25*6f625747SDouglas RaillardZynqMP platform specific build options 26*6f625747SDouglas Raillard====================================== 27*6f625747SDouglas Raillard 28*6f625747SDouglas Raillard- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. 29*6f625747SDouglas Raillard- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. 30*6f625747SDouglas Raillard- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. 31*6f625747SDouglas Raillard- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary. 32*6f625747SDouglas Raillard 33*6f625747SDouglas Raillard- ``ZYNQMP_CONSOLE``: Select the console driver. Options: 34*6f625747SDouglas Raillard 35*6f625747SDouglas Raillard - ``cadence``, ``cadence0``: Cadence UART 0 36*6f625747SDouglas Raillard - ``cadence1`` : Cadence UART 1 37*6f625747SDouglas Raillard 38*6f625747SDouglas RaillardFSBL->ATF Parameter Passing 39*6f625747SDouglas Raillard=========================== 40*6f625747SDouglas Raillard 41*6f625747SDouglas RaillardThe FSBL populates a data structure with image information for the ATF. The ATF 42*6f625747SDouglas Raillarduses that data to hand off to the loaded images. The address of the handoff data 43*6f625747SDouglas Raillardstructure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The 44*6f625747SDouglas Raillardregister is free to be used by other software once the ATF is bringing up 45*6f625747SDouglas Raillardfurther firmware images. 46*6f625747SDouglas Raillard 47*6f625747SDouglas RaillardPower Domain Tree 48*6f625747SDouglas Raillard================= 49*6f625747SDouglas Raillard 50*6f625747SDouglas RaillardThe following power domain tree represents the power domain model used by the 51*6f625747SDouglas RaillardATF for ZynqMP: 52*6f625747SDouglas Raillard 53*6f625747SDouglas Raillard:: 54*6f625747SDouglas Raillard 55*6f625747SDouglas Raillard +-+ 56*6f625747SDouglas Raillard |0| 57*6f625747SDouglas Raillard +-+ 58*6f625747SDouglas Raillard +-------+---+---+-------+ 59*6f625747SDouglas Raillard | | | | 60*6f625747SDouglas Raillard | | | | 61*6f625747SDouglas Raillard v v v v 62*6f625747SDouglas Raillard +-+ +-+ +-+ +-+ 63*6f625747SDouglas Raillard |0| |1| |2| |3| 64*6f625747SDouglas Raillard +-+ +-+ +-+ +-+ 65*6f625747SDouglas Raillard 66*6f625747SDouglas RaillardThe 4 leaf power domains represent the individual A53 cores, while resources 67*6f625747SDouglas Raillardcommon to the cluster are grouped in the power domain on the top. 68