1*4def07d5SDan HandleyTrusted Firmware-A for Xilinx Zynq UltraScale+ MPSoC 2*4def07d5SDan Handley==================================================== 36f625747SDouglas Raillard 4*4def07d5SDan HandleyTrusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq 56f625747SDouglas RaillardUltraScale + MPSoC. 6*4def07d5SDan HandleyThe platform only uses the runtime part of TF-A as ZynqMP already has a 76f625747SDouglas RaillardBootROM (BL1) and FSBL (BL2). 86f625747SDouglas Raillard 9*4def07d5SDan HandleyBL31 is TF-A. 106f625747SDouglas RaillardBL32 is an optional Secure Payload. 116f625747SDouglas RaillardBL33 is the non-secure world software (U-Boot, Linux etc). 126f625747SDouglas Raillard 136f625747SDouglas RaillardTo build: 146f625747SDouglas Raillard 156f625747SDouglas Raillard.. code:: bash 166f625747SDouglas Raillard 176f625747SDouglas Raillard make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31 186f625747SDouglas Raillard 196f625747SDouglas RaillardTo build bl32 TSP you have to rebuild bl31 too: 206f625747SDouglas Raillard 216f625747SDouglas Raillard.. code:: bash 226f625747SDouglas Raillard 236f625747SDouglas Raillard make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32 246f625747SDouglas Raillard 256f625747SDouglas RaillardZynqMP platform specific build options 266f625747SDouglas Raillard====================================== 276f625747SDouglas Raillard 286f625747SDouglas Raillard- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. 296f625747SDouglas Raillard- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. 306f625747SDouglas Raillard- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. 316f625747SDouglas Raillard- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary. 326f625747SDouglas Raillard 336f625747SDouglas Raillard- ``ZYNQMP_CONSOLE``: Select the console driver. Options: 346f625747SDouglas Raillard 356f625747SDouglas Raillard - ``cadence``, ``cadence0``: Cadence UART 0 366f625747SDouglas Raillard - ``cadence1`` : Cadence UART 1 376f625747SDouglas Raillard 38*4def07d5SDan HandleyFSBL->TF-A Parameter Passing 396f625747SDouglas Raillard=========================== 406f625747SDouglas Raillard 41*4def07d5SDan HandleyThe FSBL populates a data structure with image information for TF-A. TF-A uses 42*4def07d5SDan Handleythat data to hand off to the loaded images. The address of the handoff data 436f625747SDouglas Raillardstructure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The 44*4def07d5SDan Handleyregister is free to be used by other software once TF-A has brought up 456f625747SDouglas Raillardfurther firmware images. 466f625747SDouglas Raillard 476f625747SDouglas RaillardPower Domain Tree 486f625747SDouglas Raillard================= 496f625747SDouglas Raillard 50*4def07d5SDan HandleyThe following power domain tree represents the power domain model used by TF-A 51*4def07d5SDan Handleyfor ZynqMP: 526f625747SDouglas Raillard 536f625747SDouglas Raillard:: 546f625747SDouglas Raillard 556f625747SDouglas Raillard +-+ 566f625747SDouglas Raillard |0| 576f625747SDouglas Raillard +-+ 586f625747SDouglas Raillard +-------+---+---+-------+ 596f625747SDouglas Raillard | | | | 606f625747SDouglas Raillard | | | | 616f625747SDouglas Raillard v v v v 626f625747SDouglas Raillard +-+ +-+ +-+ +-+ 636f625747SDouglas Raillard |0| |1| |2| |3| 646f625747SDouglas Raillard +-+ +-+ +-+ +-+ 656f625747SDouglas Raillard 666f625747SDouglas RaillardThe 4 leaf power domains represent the individual A53 cores, while resources 676f625747SDouglas Raillardcommon to the cluster are grouped in the power domain on the top. 68