124dba2b3SPaul BeesleyXilinx Zynq UltraScale+ MPSoC 224dba2b3SPaul Beesley============================= 36f625747SDouglas Raillard 44def07d5SDan HandleyTrusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq 56f625747SDouglas RaillardUltraScale + MPSoC. 64def07d5SDan HandleyThe platform only uses the runtime part of TF-A as ZynqMP already has a 76f625747SDouglas RaillardBootROM (BL1) and FSBL (BL2). 86f625747SDouglas Raillard 94def07d5SDan HandleyBL31 is TF-A. 106f625747SDouglas RaillardBL32 is an optional Secure Payload. 116f625747SDouglas RaillardBL33 is the non-secure world software (U-Boot, Linux etc). 126f625747SDouglas Raillard 136f625747SDouglas RaillardTo build: 146f625747SDouglas Raillard 156f625747SDouglas Raillard.. code:: bash 166f625747SDouglas Raillard 17e8e7cdf3SVenkatesh Yadav Abbarapu make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 186f625747SDouglas Raillard 196f625747SDouglas RaillardTo build bl32 TSP you have to rebuild bl31 too: 206f625747SDouglas Raillard 216f625747SDouglas Raillard.. code:: bash 226f625747SDouglas Raillard 23e8e7cdf3SVenkatesh Yadav Abbarapu make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd RESET_TO_BL31=1 bl31 bl32 246f625747SDouglas Raillard 25c00baeecSVenkatesh Yadav AbbarapuTo build TF-A for JTAG DCC console: 26c00baeecSVenkatesh Yadav Abbarapu 27c00baeecSVenkatesh Yadav Abbarapu.. code:: bash 28c00baeecSVenkatesh Yadav Abbarapu 29c00baeecSVenkatesh Yadav Abbarapu make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc 30c00baeecSVenkatesh Yadav Abbarapu 316f625747SDouglas RaillardZynqMP platform specific build options 3224dba2b3SPaul Beesley-------------------------------------- 336f625747SDouglas Raillard 346f625747SDouglas Raillard- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. 356f625747SDouglas Raillard- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. 366f625747SDouglas Raillard- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. 376f625747SDouglas Raillard- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary. 386f625747SDouglas Raillard 396f625747SDouglas Raillard- ``ZYNQMP_CONSOLE``: Select the console driver. Options: 406f625747SDouglas Raillard 416f625747SDouglas Raillard - ``cadence``, ``cadence0``: Cadence UART 0 426f625747SDouglas Raillard - ``cadence1`` : Cadence UART 1 436f625747SDouglas Raillard 44*2537f072SAkshay BelsareZynqMP Debug behavior 45*2537f072SAkshay Belsare--------------------- 46*2537f072SAkshay Belsare 47*2537f072SAkshay BelsareWith DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range 48*2537f072SAkshay Belsaredue to size constraints. 49*2537f072SAkshay BelsareFor DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location 50*2537f072SAkshay Belsareof 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF. 51*2537f072SAkshay Belsare 52*2537f072SAkshay BelsareIf the user wants to move the bl31 to a different DDR location, user can provide 53*2537f072SAkshay Belsarethe DDR address location in the build command as follows, 54*2537f072SAkshay Belsare 55*2537f072SAkshay Belsaremake CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \ 56*2537f072SAkshay Belsare ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> bl31 57*2537f072SAkshay Belsare 58*2537f072SAkshay Belsare 594def07d5SDan HandleyFSBL->TF-A Parameter Passing 6024dba2b3SPaul Beesley---------------------------- 616f625747SDouglas Raillard 624def07d5SDan HandleyThe FSBL populates a data structure with image information for TF-A. TF-A uses 634def07d5SDan Handleythat data to hand off to the loaded images. The address of the handoff data 646f625747SDouglas Raillardstructure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The 654def07d5SDan Handleyregister is free to be used by other software once TF-A has brought up 666f625747SDouglas Raillardfurther firmware images. 676f625747SDouglas Raillard 686f625747SDouglas RaillardPower Domain Tree 6924dba2b3SPaul Beesley----------------- 706f625747SDouglas Raillard 714def07d5SDan HandleyThe following power domain tree represents the power domain model used by TF-A 724def07d5SDan Handleyfor ZynqMP: 736f625747SDouglas Raillard 746f625747SDouglas Raillard:: 756f625747SDouglas Raillard 766f625747SDouglas Raillard +-+ 776f625747SDouglas Raillard |0| 786f625747SDouglas Raillard +-+ 796f625747SDouglas Raillard +-------+---+---+-------+ 806f625747SDouglas Raillard | | | | 816f625747SDouglas Raillard | | | | 826f625747SDouglas Raillard v v v v 836f625747SDouglas Raillard +-+ +-+ +-+ +-+ 846f625747SDouglas Raillard |0| |1| |2| |3| 856f625747SDouglas Raillard +-+ +-+ +-+ +-+ 866f625747SDouglas Raillard 876f625747SDouglas RaillardThe 4 leaf power domains represent the individual A53 cores, while resources 886f625747SDouglas Raillardcommon to the cluster are grouped in the power domain on the top. 89