xref: /rk3399_ARM-atf/docs/plat/st/stm32mp2.rst (revision ee5076f9716591333f1f5aa73b02c130c57917db)
1*ee5076f9SYann GautierSTM32MP2
2*ee5076f9SYann Gautier========
3*ee5076f9SYann Gautier
4*ee5076f9SYann GautierSTM32MP2 is a microprocessor designed by STMicroelectronics
5*ee5076f9SYann Gautierbased on Arm Cortex-A35.
6*ee5076f9SYann Gautier
7*ee5076f9SYann GautierFor TF-A common configuration of STM32 MPUs, please check
8*ee5076f9SYann Gautier:ref:`STM32 MPUs` page.
9*ee5076f9SYann Gautier
10*ee5076f9SYann GautierSTM32MP2 Versions
11*ee5076f9SYann Gautier-----------------
12*ee5076f9SYann Gautier
13*ee5076f9SYann GautierThe STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
14*ee5076f9SYann Gautier
15*ee5076f9SYann Gautier- STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
16*ee5076f9SYann Gautier- STM32MP255: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - H264 - 3D GPU – AI / NN - LVDS
17*ee5076f9SYann Gautier- STM32MP253: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - LVDS
18*ee5076f9SYann Gautier- STM32MP251: Single Cortex-A35 core, Cortex-M33 core - 1x Ethernet
19*ee5076f9SYann Gautier
20*ee5076f9SYann GautierEach line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
21*ee5076f9SYann Gautier
22*ee5076f9SYann Gautier- A      Basic + Cortex-A35 @ 1GHz
23*ee5076f9SYann Gautier- C      Secure Boot + HW Crypto + Cortex-A35 @ 1GHz
24*ee5076f9SYann Gautier- D      Basic + Cortex-A35 @ 1.5GHz
25*ee5076f9SYann Gautier- F      Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
26*ee5076f9SYann Gautier
27*ee5076f9SYann GautierMemory mapping
28*ee5076f9SYann Gautier--------------
29*ee5076f9SYann Gautier
30*ee5076f9SYann Gautier::
31*ee5076f9SYann Gautier
32*ee5076f9SYann Gautier    0x00000000 +-----------------+
33*ee5076f9SYann Gautier               |                 |
34*ee5076f9SYann Gautier               |       ...       |
35*ee5076f9SYann Gautier               |                 |
36*ee5076f9SYann Gautier    0x0E000000 +-----------------+ \
37*ee5076f9SYann Gautier               |       BL31      | |
38*ee5076f9SYann Gautier               +-----------------+ |
39*ee5076f9SYann Gautier               |       ...       | |
40*ee5076f9SYann Gautier    0x0E012000 +-----------------+ |
41*ee5076f9SYann Gautier               |     BL2 DTB     | | Embedded SRAM
42*ee5076f9SYann Gautier    0x0E016000 +-----------------+ |
43*ee5076f9SYann Gautier               |       BL2       | |
44*ee5076f9SYann Gautier    0x0E040000 +-----------------+ /
45*ee5076f9SYann Gautier               |                 |
46*ee5076f9SYann Gautier               |       ...       |
47*ee5076f9SYann Gautier               |                 |
48*ee5076f9SYann Gautier    0x40000000 +-----------------+
49*ee5076f9SYann Gautier               |                 |
50*ee5076f9SYann Gautier               |                 |   Devices
51*ee5076f9SYann Gautier               |                 |
52*ee5076f9SYann Gautier    0x80000000 +-----------------+ \
53*ee5076f9SYann Gautier               |                 | |
54*ee5076f9SYann Gautier               |                 | | Non-secure RAM (DDR)
55*ee5076f9SYann Gautier               |                 | |
56*ee5076f9SYann Gautier    0xFFFFFFFF +-----------------+ /
57*ee5076f9SYann Gautier
58*ee5076f9SYann Gautier
59*ee5076f9SYann GautierBuild Instructions
60*ee5076f9SYann Gautier------------------
61*ee5076f9SYann Gautier
62*ee5076f9SYann GautierSTM32MP2x specific flags
63*ee5076f9SYann Gautier~~~~~~~~~~~~~~~~~~~~~~~~
64*ee5076f9SYann Gautier
65*ee5076f9SYann GautierDedicated STM32MP2 build flags:
66*ee5076f9SYann Gautier
67*ee5076f9SYann Gautier- | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
68*ee5076f9SYann Gautier  | Default: 1
69*ee5076f9SYann Gautier- | ``STM32MP25``: to select STM32MP25 variant configuration.
70*ee5076f9SYann Gautier  | Default: 1
71*ee5076f9SYann Gautier
72*ee5076f9SYann GautierTo compile the correct DDR driver, one flag must be set among:
73*ee5076f9SYann Gautier
74*ee5076f9SYann Gautier- | ``STM32MP_DDR3_TYPE``: to compile DDR3 driver and DT.
75*ee5076f9SYann Gautier  | Default: 0
76*ee5076f9SYann Gautier- | ``STM32MP_DDR4_TYPE``: to compile DDR4 driver and DT.
77*ee5076f9SYann Gautier  | Default: 0
78*ee5076f9SYann Gautier- | ``STM32MP_LPDDR4_TYPE``: to compile LpDDR4 driver and DT.
79*ee5076f9SYann Gautier  | Default: 0
80*ee5076f9SYann Gautier
81*ee5076f9SYann Gautier
82*ee5076f9SYann GautierBoot with FIP
83*ee5076f9SYann Gautier~~~~~~~~~~~~~
84*ee5076f9SYann GautierYou need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) before building FIP binary.
85*ee5076f9SYann Gautier
86*ee5076f9SYann GautierU-Boot
87*ee5076f9SYann Gautier______
88*ee5076f9SYann Gautier
89*ee5076f9SYann Gautier.. code:: bash
90*ee5076f9SYann Gautier
91*ee5076f9SYann Gautier    cd <u-boot_directory>
92*ee5076f9SYann Gautier    make stm32mp25_defconfig
93*ee5076f9SYann Gautier    make DEVICE_TREE=stm32mp257f-ev1 all
94*ee5076f9SYann Gautier
95*ee5076f9SYann GautierOP-TEE
96*ee5076f9SYann Gautier______
97*ee5076f9SYann Gautier
98*ee5076f9SYann Gautier.. code:: bash
99*ee5076f9SYann Gautier
100*ee5076f9SYann Gautier    cd <optee_directory>
101*ee5076f9SYann Gautier    make CROSS_COMPILE64=aarch64-none-elf- CROSS_COMPILE32=arm-none-eabi-
102*ee5076f9SYann Gautier        ARCH=arm PLATFORM=stm32mp2 \
103*ee5076f9SYann Gautier        CFG_EMBED_DTB_SOURCE_FILE=stm32mp257f-ev1.dts
104*ee5076f9SYann Gautier
105*ee5076f9SYann GautierTF-A BL2 & BL31
106*ee5076f9SYann Gautier_______________
107*ee5076f9SYann GautierTo build TF-A BL2 with its STM32 header and BL31 for SD-card boot:
108*ee5076f9SYann Gautier
109*ee5076f9SYann Gautier.. code:: bash
110*ee5076f9SYann Gautier
111*ee5076f9SYann Gautier    make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \
112*ee5076f9SYann Gautier        STM32MP_DDR4_TYPE=1 SPD=opteed \
113*ee5076f9SYann Gautier        DTB_FILE_NAME=stm32mp257f-ev1.dtb STM32MP_SDMMC=1
114*ee5076f9SYann Gautier
115*ee5076f9SYann GautierFor other boot devices, you have to replace STM32MP_SDMMC in the previous command
116*ee5076f9SYann Gautierwith the desired device flag.
117*ee5076f9SYann Gautier
118*ee5076f9SYann Gautier
119*ee5076f9SYann GautierFIP
120*ee5076f9SYann Gautier___
121*ee5076f9SYann Gautier
122*ee5076f9SYann Gautier.. code:: bash
123*ee5076f9SYann Gautier
124*ee5076f9SYann Gautier    make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \
125*ee5076f9SYann Gautier        STM32MP_DDR4_TYPE=1 SPD=opteed \
126*ee5076f9SYann Gautier        DTB_FILE_NAME=stm32mp257f-ev1.dtb \
127*ee5076f9SYann Gautier        BL33=<u-boot_directory>/u-boot-nodtb.bin \
128*ee5076f9SYann Gautier        BL33_CFG=<u-boot_directory>/u-boot.dtb \
129*ee5076f9SYann Gautier        BL32=<optee_directory>/tee-header_v2.bin \
130*ee5076f9SYann Gautier        BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
131*ee5076f9SYann Gautier        fip
132*ee5076f9SYann Gautier
133*ee5076f9SYann Gautier*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
134