xref: /rk3399_ARM-atf/docs/plat/rz-a3.rst (revision 66a0bb47058db8a4f74ccc1543a146094829e110)
1*2aa63355SNhut NguyenRenesas RZ/A3
2*2aa63355SNhut Nguyen=============
3*2aa63355SNhut Nguyen
4*2aa63355SNhut NguyenThe RZ/A series is an RTOS-based microprocessor (MPU) combining excellent real-time performance
5*2aa63355SNhut Nguyenand fast boot time based on Renesas' proprietary technology and Arm® ecosystem, and
6*2aa63355SNhut Nguyenis as user-friendly as Renesas MCUs.
7*2aa63355SNhut Nguyen
8*2aa63355SNhut NguyenThe high-speed performance of the RZ/A MPU can quickly process graphics and high-load applications
9*2aa63355SNhut Nguyenespecially in the third generation RZ/A3M MPU powered by the 64-bit Arm® Cortex®-A55 CPU
10*2aa63355SNhut Nguyencore with a maximum operating frequency of 1 GHz.
11*2aa63355SNhut Nguyen
12*2aa63355SNhut NguyenRenesas RZ/A3 reference platforms:
13*2aa63355SNhut Nguyen----------------------------------
14*2aa63355SNhut Nguyen
15*2aa63355SNhut Nguyen+------------------------------+------------------------------------------------------------------+
16*2aa63355SNhut Nguyen| Board                        | Details                                                          |
17*2aa63355SNhut Nguyen+==============================+==================================================================+
18*2aa63355SNhut Nguyen| EK-RZ/A3M                    | Evaluation Kit for RZ/A3M MPU                                    |
19*2aa63355SNhut Nguyen+------------------------------+------------------------------------------------------------------+
20*2aa63355SNhut Nguyen
21*2aa63355SNhut NguyenBoot Sequence
22*2aa63355SNhut Nguyen-------------
23*2aa63355SNhut Nguyen
24*2aa63355SNhut NguyenRZ/A3 SoCs implements its internal boot ROM; which loads an image
25*2aa63355SNhut Nguyenfrom a non-volatile storage to the on-chip RAM, and jumps over to it.
26*2aa63355SNhut NguyenTF-A provides a special mode, BL2-AT-EL3, which enables BL2 to execute
27*2aa63355SNhut Nguyenat EL3 and small enough to fit on-chip RAM.
28*2aa63355SNhut Nguyen
29*2aa63355SNhut NguyenOnce BL2 boots, it initializes DDR before copying the next image
30*2aa63355SNhut Nguyenfrom flash to DDR, then transfer the excution to it which is usually
31*2aa63355SNhut Nguyenrequired at EL3 at the entry point to run a RTOS (such as Zephyr or FreeRTOS).
32*2aa63355SNhut NguyenThat is the reason why only BL2 is supported.
33*2aa63355SNhut Nguyen
34*2aa63355SNhut NguyenBootROM --> BL2 --> RTOS (Zephyr/FreeRTOS)
35*2aa63355SNhut Nguyen
36*2aa63355SNhut NguyenTF-A Build Procedure
37*2aa63355SNhut Nguyen--------------------
38*2aa63355SNhut Nguyen
39*2aa63355SNhut NguyenThe TF-A build options depend on the target board so you will have to
40*2aa63355SNhut Nguyenrefer to those specific instructions. What follows is customized to
41*2aa63355SNhut Nguyenthe EK-RZ/A3M used in this port.
42*2aa63355SNhut Nguyen
43*2aa63355SNhut Nguyen.. code:: shell
44*2aa63355SNhut Nguyen
45*2aa63355SNhut Nguyen    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rza3m_ek_nor all
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