xref: /rk3399_ARM-atf/docs/plat/marvell/armada/porting.rst (revision a28471722afb3ae784d7bce2118c2ea703f8444c)
1*a2847172SGrzegorz JaszczykTF-A Porting Guide for Marvell Platforms
2*a2847172SGrzegorz Jaszczyk========================================
3*a2847172SGrzegorz Jaszczyk
4*a2847172SGrzegorz JaszczykThis section describes how to port TF-A to a customer board, assuming that the
5*a2847172SGrzegorz JaszczykSoC being used is already supported in TF-A.
6*a2847172SGrzegorz Jaszczyk
7*a2847172SGrzegorz Jaszczyk
8*a2847172SGrzegorz JaszczykSource Code Structure
9*a2847172SGrzegorz Jaszczyk---------------------
10*a2847172SGrzegorz Jaszczyk
11*a2847172SGrzegorz Jaszczyk- The customer platform specific code shall reside under ``plat/marvell/armada/<soc family>/<soc>_cust``
12*a2847172SGrzegorz Jaszczyk  (e.g. 'plat/marvell/armada/a8k/a7040_cust').
13*a2847172SGrzegorz Jaszczyk- The platform name for build purposes is called ``<soc>_cust`` (e.g. ``a7040_cust``).
14*a2847172SGrzegorz Jaszczyk- The build system will reuse all files from within the soc directory, and take only the porting
15*a2847172SGrzegorz Jaszczyk  files from the customer platform directory.
16*a2847172SGrzegorz Jaszczyk
17*a2847172SGrzegorz JaszczykFiles that require porting are located at ``plat/marvell/armada/<soc family>/<soc>_cust`` directory.
18*a2847172SGrzegorz Jaszczyk
19*a2847172SGrzegorz Jaszczyk
20*a2847172SGrzegorz JaszczykArmada-70x0/Armada-80x0 Porting
21*a2847172SGrzegorz Jaszczyk-------------------------------
22*a2847172SGrzegorz Jaszczyk
23*a2847172SGrzegorz JaszczykSoC Physical Address Map (marvell_plat_config.c)
24*a2847172SGrzegorz Jaszczyk~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
25*a2847172SGrzegorz Jaszczyk
26*a2847172SGrzegorz JaszczykThis file describes the SoC physical memory mapping to be used for the CCU,
27*a2847172SGrzegorz JaszczykIOWIN, AXI-MBUS and IOB address decode units (Refer to the functional spec for
28*a2847172SGrzegorz Jaszczykmore details).
29*a2847172SGrzegorz Jaszczyk
30*a2847172SGrzegorz JaszczykIn most cases, using the default address decode windows should work OK.
31*a2847172SGrzegorz Jaszczyk
32*a2847172SGrzegorz JaszczykIn cases where a special physical address map is needed (e.g. Special size for
33*a2847172SGrzegorz JaszczykPCIe MEM windows, large memory mapped SPI flash...), then porting of the SoC
34*a2847172SGrzegorz Jaszczykmemory map is required.
35*a2847172SGrzegorz Jaszczyk
36*a2847172SGrzegorz Jaszczyk.. note::
37*a2847172SGrzegorz Jaszczyk   For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please
38*a2847172SGrzegorz Jaszczyk   refer to the SoC functional spec, and under
39*a2847172SGrzegorz Jaszczyk   ``docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt`` files.
40*a2847172SGrzegorz Jaszczyk
41*a2847172SGrzegorz Jaszczykboot loader recovery (marvell_plat_config.c)
42*a2847172SGrzegorz Jaszczyk~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
43*a2847172SGrzegorz Jaszczyk
44*a2847172SGrzegorz Jaszczyk- Background:
45*a2847172SGrzegorz Jaszczyk
46*a2847172SGrzegorz Jaszczyk  Boot rom can skip the current image and choose to boot from next position if a
47*a2847172SGrzegorz Jaszczyk  specific value (``0xDEADB002``) is returned by the ble main function. This
48*a2847172SGrzegorz Jaszczyk  feature is used for boot loader recovery by booting from a valid flash-image
49*a2847172SGrzegorz Jaszczyk  saved in next position on flash (e.g. address 2M in SPI flash).
50*a2847172SGrzegorz Jaszczyk
51*a2847172SGrzegorz Jaszczyk  Supported options to implement the skip request are:
52*a2847172SGrzegorz Jaszczyk    - GPIO
53*a2847172SGrzegorz Jaszczyk    - I2C
54*a2847172SGrzegorz Jaszczyk    - User defined
55*a2847172SGrzegorz Jaszczyk
56*a2847172SGrzegorz Jaszczyk- Porting:
57*a2847172SGrzegorz Jaszczyk
58*a2847172SGrzegorz Jaszczyk  Under marvell_plat_config.c, implement struct skip_image that includes
59*a2847172SGrzegorz Jaszczyk  specific board parameters.
60*a2847172SGrzegorz Jaszczyk
61*a2847172SGrzegorz Jaszczyk  .. warning::
62*a2847172SGrzegorz Jaszczyk     To disable this feature make sure the struct skip_image is not implemented.
63*a2847172SGrzegorz Jaszczyk
64*a2847172SGrzegorz Jaszczyk- Example:
65*a2847172SGrzegorz Jaszczyk
66*a2847172SGrzegorz JaszczykIn A7040-DB specific implementation
67*a2847172SGrzegorz Jaszczyk(``plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c``), the image skip is
68*a2847172SGrzegorz Jaszczykimplemented using GPIO: mpp 33 (SW5).
69*a2847172SGrzegorz Jaszczyk
70*a2847172SGrzegorz JaszczykBefore resetting the board make sure there is a valid image on the next flash
71*a2847172SGrzegorz Jaszczykaddress:
72*a2847172SGrzegorz Jaszczyk
73*a2847172SGrzegorz Jaszczyk -tftp [valid address] flash-image.bin
74*a2847172SGrzegorz Jaszczyk -sf update [valid address] 0x2000000 [size]
75*a2847172SGrzegorz Jaszczyk
76*a2847172SGrzegorz JaszczykPress reset and keep pressing the button connected to the chosen GPIO pin. A
77*a2847172SGrzegorz Jaszczykskip image request message is printed on the screen and boot rom boots from the
78*a2847172SGrzegorz Jaszczyksaved image at the next position.
79*a2847172SGrzegorz Jaszczyk
80*a2847172SGrzegorz JaszczykDDR Porting (dram_port.c)
81*a2847172SGrzegorz Jaszczyk~~~~~~~~~~~~~~~~~~~~~~~~~
82*a2847172SGrzegorz Jaszczyk
83*a2847172SGrzegorz JaszczykThis file defines the dram topology and parameters of the target board.
84*a2847172SGrzegorz Jaszczyk
85*a2847172SGrzegorz JaszczykThe DDR code is part of the BLE component, which is an extension of ARM Trusted
86*a2847172SGrzegorz JaszczykFirmware (TF-A).
87*a2847172SGrzegorz Jaszczyk
88*a2847172SGrzegorz JaszczykThe DDR driver called mv_ddr is released separately apart from TF-A sources.
89*a2847172SGrzegorz Jaszczyk
90*a2847172SGrzegorz JaszczykThe BLE and consequently, the DDR init code is executed at the early stage of
91*a2847172SGrzegorz Jaszczykthe boot process.
92*a2847172SGrzegorz Jaszczyk
93*a2847172SGrzegorz JaszczykEach supported platform of the TF-A has its own DDR porting file called
94*a2847172SGrzegorz Jaszczykdram_port.c located at ``atf/plat/marvell/armada/a8k/<platform>/board`` directory.
95*a2847172SGrzegorz Jaszczyk
96*a2847172SGrzegorz JaszczykPlease refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed
97*a2847172SGrzegorz Jaszczykporting description.
98*a2847172SGrzegorz Jaszczyk
99*a2847172SGrzegorz JaszczykThe build target directory is "build/<platform>/release/ble".
100*a2847172SGrzegorz Jaszczyk
101*a2847172SGrzegorz JaszczykComphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
102*a2847172SGrzegorz Jaszczyk~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
103*a2847172SGrzegorz Jaszczyk
104*a2847172SGrzegorz Jaszczyk- Background:
105*a2847172SGrzegorz Jaszczyk    Some of the comphy's parameters value depend on the HW connection between
106*a2847172SGrzegorz Jaszczyk    the SoC and the PHY. Every board type has specific HW characteristics like
107*a2847172SGrzegorz Jaszczyk    wire length. Due to those differences some comphy parameters vary between
108*a2847172SGrzegorz Jaszczyk    board types. Therefore each board type can have its own list of values for
109*a2847172SGrzegorz Jaszczyk    all relevant comphy parameters. The PHY porting layer specifies which
110*a2847172SGrzegorz Jaszczyk    parameters need to be suited and the board designer should provide relevant
111*a2847172SGrzegorz Jaszczyk    values.
112*a2847172SGrzegorz Jaszczyk
113*a2847172SGrzegorz Jaszczyk    .. seealso::
114*a2847172SGrzegorz Jaszczyk        For XFI/SFI comphy type there is procedure "rx_training" which eases
115*a2847172SGrzegorz Jaszczyk        process of suiting some of the parameters. Please see *uboot_cmd*
116*a2847172SGrzegorz Jaszczyk        section: rx_training.
117*a2847172SGrzegorz Jaszczyk
118*a2847172SGrzegorz Jaszczyk    The PHY porting layer simplifies updating static values per board type,
119*a2847172SGrzegorz Jaszczyk    which are now grouped in one place.
120*a2847172SGrzegorz Jaszczyk
121*a2847172SGrzegorz Jaszczyk    .. note::
122*a2847172SGrzegorz Jaszczyk        The parameters for the same type of comphy may vary even for the same
123*a2847172SGrzegorz Jaszczyk        board type, it is because the lanes from comphy-x to some PHY may have
124*a2847172SGrzegorz Jaszczyk        different HW characteristic than lanes from comphy-y to the same
125*a2847172SGrzegorz Jaszczyk        (multiplexed) or other PHY.
126*a2847172SGrzegorz Jaszczyk
127*a2847172SGrzegorz Jaszczyk- Porting:
128*a2847172SGrzegorz Jaszczyk    The porting layer for PHY was introduced in TF-A. There is one file
129*a2847172SGrzegorz Jaszczyk    ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the
130*a2847172SGrzegorz Jaszczyk    defaults. Those default parameters are used only if there is no appropriate
131*a2847172SGrzegorz Jaszczyk    phy-porting-layer.h file under: ``plat/marvell/armada/<soc
132*a2847172SGrzegorz Jaszczyk    family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h
133*a2847172SGrzegorz Jaszczyk    exists, the phy-default-porting-layer.h is not going to be included.
134*a2847172SGrzegorz Jaszczyk
135*a2847172SGrzegorz Jaszczyk    .. warning::
136*a2847172SGrzegorz Jaszczyk        Not all comphy types are already reworked to support the PHY porting
137*a2847172SGrzegorz Jaszczyk        layer, currently the porting layer is supported for XFI/SFI and SATA
138*a2847172SGrzegorz Jaszczyk        comphy types.
139*a2847172SGrzegorz Jaszczyk
140*a2847172SGrzegorz Jaszczyk    The easiest way to prepare the PHY porting layer for custom board is to copy
141*a2847172SGrzegorz Jaszczyk    existing example to a new platform:
142*a2847172SGrzegorz Jaszczyk
143*a2847172SGrzegorz Jaszczyk    - cp ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/armada/<soc family>/<platform>/board/phy-porting-layer.h"
144*a2847172SGrzegorz Jaszczyk    - adjust relevant parameters or
145*a2847172SGrzegorz Jaszczyk    - if different comphy index is used for specific feature, move it to proper table entry and then adjust.
146*a2847172SGrzegorz Jaszczyk
147*a2847172SGrzegorz Jaszczyk    .. note::
148*a2847172SGrzegorz Jaszczyk        The final table size with comphy parameters can be different, depending
149*a2847172SGrzegorz Jaszczyk        on the CP module count for given SoC type.
150*a2847172SGrzegorz Jaszczyk
151*a2847172SGrzegorz Jaszczyk- Example:
152*a2847172SGrzegorz Jaszczyk    Example porting layer for armada-8040-db is under:
153*a2847172SGrzegorz Jaszczyk    ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h``
154*a2847172SGrzegorz Jaszczyk
155*a2847172SGrzegorz Jaszczyk    .. note::
156*a2847172SGrzegorz Jaszczyk        If there is no PHY porting layer for new platform (missing
157*a2847172SGrzegorz Jaszczyk        phy-porting-layer.h), the default values are used
158*a2847172SGrzegorz Jaszczyk        (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is
159*a2847172SGrzegorz Jaszczyk        warned:
160*a2847172SGrzegorz Jaszczyk
161*a2847172SGrzegorz Jaszczyk    .. warning::
162*a2847172SGrzegorz Jaszczyk        "Using default comphy parameters - it may be required to suit them for
163*a2847172SGrzegorz Jaszczyk        your board".
164