1*24dba2b3SPaul BeesleyIntel Stratix 10 SoCFPGA 2*24dba2b3SPaul Beesley======================== 31cf55abaSTien Hock, Loh 41cf55abaSTien Hock, LohStratix 10 SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A53 processor. 51cf55abaSTien Hock, Loh 61cf55abaSTien Hock, LohUpon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes 71cf55abaSTien Hock, Lohthe hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33. 81cf55abaSTien Hock, Loh 91cf55abaSTien Hock, Loh:: 101cf55abaSTien Hock, Loh 111cf55abaSTien Hock, Loh Boot ROM --> Trusted Firmware-A --> UEFI 121cf55abaSTien Hock, Loh 131cf55abaSTien Hock, LohHow to build 14*24dba2b3SPaul Beesley------------ 151cf55abaSTien Hock, Loh 161cf55abaSTien Hock, LohCode Locations 17*24dba2b3SPaul Beesley~~~~~~~~~~~~~~ 181cf55abaSTien Hock, Loh 191cf55abaSTien Hock, Loh- Trusted Firmware-A: 201cf55abaSTien Hock, Loh `link <https://github.com/ARM-software/arm-trusted-firmware>`__ 211cf55abaSTien Hock, Loh 221cf55abaSTien Hock, Loh- UEFI (to be updated with new upstreamed UEFI): 231cf55abaSTien Hock, Loh `link <https://github.com/altera-opensource/uefi-socfpga>`__ 241cf55abaSTien Hock, Loh 251cf55abaSTien Hock, LohBuild Procedure 26*24dba2b3SPaul Beesley~~~~~~~~~~~~~~~ 271cf55abaSTien Hock, Loh 281cf55abaSTien Hock, Loh- Fetch all the above 2 repositories into local host. 291cf55abaSTien Hock, Loh Make all the repositories in the same ${BUILD\_PATH}. 301cf55abaSTien Hock, Loh 311cf55abaSTien Hock, Loh- Prepare the AARCH64 toolchain. 321cf55abaSTien Hock, Loh 331cf55abaSTien Hock, Loh- Build UEFI using Stratix 10 platform as configuration 341cf55abaSTien Hock, Loh This will be updated to use an updated UEFI using the latest EDK2 source 351cf55abaSTien Hock, Loh 361cf55abaSTien Hock, Loh.. code:: bash 371cf55abaSTien Hock, Loh 381cf55abaSTien Hock, Loh make CROSS_COMPILE=aarch64-linux-gnu- device=s10 391cf55abaSTien Hock, Loh 401cf55abaSTien Hock, Loh- Build atf providing the previously generated UEFI as the BL33 image 411cf55abaSTien Hock, Loh 421cf55abaSTien Hock, Loh.. code:: bash 431cf55abaSTien Hock, Loh 441cf55abaSTien Hock, Loh make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=stratix10 451cf55abaSTien Hock, Loh BL33=PEI.ROM 461cf55abaSTien Hock, Loh 471cf55abaSTien Hock, LohInstall Procedure 48*24dba2b3SPaul Beesley~~~~~~~~~~~~~~~~~ 491cf55abaSTien Hock, Loh 501cf55abaSTien Hock, Loh- dd fip.bin to a A2 partition on the MMC drive to be booted in Stratix 10 511cf55abaSTien Hock, Loh board. 521cf55abaSTien Hock, Loh 531cf55abaSTien Hock, Loh- Generate a SOF containing bl2 541cf55abaSTien Hock, Loh 551cf55abaSTien Hock, Loh.. code:: bash 56*24dba2b3SPaul Beesley 571cf55abaSTien Hock, Loh aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex 581cf55abaSTien Hock, Loh quartus_cpf --bootloader bl2.hex <quartus_generated_sof> <output_sof_with_bl2> 591cf55abaSTien Hock, Loh 601cf55abaSTien Hock, Loh- Configure SOF to board 611cf55abaSTien Hock, Loh 621cf55abaSTien Hock, Loh.. code:: bash 63*24dba2b3SPaul Beesley 641cf55abaSTien Hock, Loh nios2-configure-sof <output_sof_with_bl2> 651cf55abaSTien Hock, Loh 661cf55abaSTien Hock, LohBoot trace 67*24dba2b3SPaul Beesley---------- 681cf55abaSTien Hock, Loh 691cf55abaSTien Hock, Loh:: 701cf55abaSTien Hock, Loh INFO: DDR: DRAM calibration success. 711cf55abaSTien Hock, Loh INFO: ECC is disabled. 721cf55abaSTien Hock, Loh INFO: Init HPS NOC's DDR Scheduler. 731cf55abaSTien Hock, Loh NOTICE: BL2: v2.0(debug):v2.0-809-g7f8474a-dirty 741cf55abaSTien Hock, Loh NOTICE: BL2: Built : 17:38:19, Feb 18 2019 751cf55abaSTien Hock, Loh INFO: BL2: Doing platform setup 761cf55abaSTien Hock, Loh INFO: BL2: Loading image id 3 771cf55abaSTien Hock, Loh INFO: Loading image id=3 at address 0xffe1c000 781cf55abaSTien Hock, Loh INFO: Image id=3 loaded: 0xffe1c000 - 0xffe24034 791cf55abaSTien Hock, Loh INFO: BL2: Loading image id 5 801cf55abaSTien Hock, Loh INFO: Loading image id=5 at address 0x50000 811cf55abaSTien Hock, Loh INFO: Image id=5 loaded: 0x50000 - 0x550000 821cf55abaSTien Hock, Loh NOTICE: BL2: Booting BL31 831cf55abaSTien Hock, Loh INFO: Entry point address = 0xffe1c000 841cf55abaSTien Hock, Loh INFO: SPSR = 0x3cd 851cf55abaSTien Hock, Loh NOTICE: BL31: v2.0(debug):v2.0-810-g788c436-dirty 861cf55abaSTien Hock, Loh NOTICE: BL31: Built : 15:17:16, Feb 20 2019 871cf55abaSTien Hock, Loh INFO: ARM GICv2 driver initialized 881cf55abaSTien Hock, Loh INFO: BL31: Initializing runtime services 891cf55abaSTien Hock, Loh WARNING: BL31: cortex_a53: CPU workaround for 855873 was missing! 901cf55abaSTien Hock, Loh INFO: BL31: Preparing for EL3 exit to normal world 911cf55abaSTien Hock, Loh INFO: Entry point address = 0x50000 921cf55abaSTien Hock, Loh INFO: SPSR = 0x3c9 931cf55abaSTien Hock, Loh UEFI firmware (version 1.0 built at 11:26:18 on Nov 7 2018) 94