1*6ec0c65bSUsama ArifTC Total Compute Platform 2*6ec0c65bSUsama Arif========================== 3*6ec0c65bSUsama Arif 4*6ec0c65bSUsama ArifSome of the features of TC platform referenced in TF-A include: 5*6ec0c65bSUsama Arif 6*6ec0c65bSUsama Arif- A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_ 7*6ec0c65bSUsama Arif to abstract power and system management tasks away from application 8*6ec0c65bSUsama Arif processors. The RAM firmware for SCP is included in the TF-A FIP and is 9*6ec0c65bSUsama Arif loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access 10*6ec0c65bSUsama Arif to AP SRAM). 11*6ec0c65bSUsama Arif- GICv4 12*6ec0c65bSUsama Arif- Trusted Board Boot 13*6ec0c65bSUsama Arif- SCMI 14*6ec0c65bSUsama Arif- MHUv2 15*6ec0c65bSUsama Arif 16*6ec0c65bSUsama ArifCurrently, the main difference between TC0 (TARGET_PLATFORM=0) and TC1 17*6ec0c65bSUsama Arif(TARGET_PLATFORM=1) platforms w.r.t to TF-A is the CPUs supported. TC0 has 18*6ec0c65bSUsama Arifsupport for Cortex A510, Cortex A710 and Cortex X2, while TC1 has support for 19*6ec0c65bSUsama ArifCortex A510, Cortex Makalu and Cortex Makalu ELP Arm CPUs. 20*6ec0c65bSUsama Arif 21*6ec0c65bSUsama Arif 22*6ec0c65bSUsama ArifBoot Sequence 23*6ec0c65bSUsama Arif------------- 24*6ec0c65bSUsama Arif 25*6ec0c65bSUsama ArifThe execution begins from SCP_BL1. SCP_BL1 powers up the AP which starts 26*6ec0c65bSUsama Arifexecuting AP_BL1 and then executes AP_BL2 which loads the SCP_BL2 from 27*6ec0c65bSUsama ArifFIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2 28*6ec0c65bSUsama Arifis communicated to SCP using SDS. SCP copies SCP_BL2 from SRAM to its own 29*6ec0c65bSUsama ArifRAM and starts executing it. The AP then continues executing the rest of TF-A 30*6ec0c65bSUsama Arifstages including BL31 runtime stage and hands off executing to 31*6ec0c65bSUsama ArifNon-secure world (u-boot). 32*6ec0c65bSUsama Arif 33*6ec0c65bSUsama ArifBuild Procedure (TF-A only) 34*6ec0c65bSUsama Arif~~~~~~~~~~~~~~~~~~~~~~~~~~~ 35*6ec0c65bSUsama Arif 36*6ec0c65bSUsama Arif- Obtain arm `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_. 37*6ec0c65bSUsama Arif Set the CROSS_COMPILE environment variable to point to the toolchain folder. 38*6ec0c65bSUsama Arif 39*6ec0c65bSUsama Arif- Build TF-A: 40*6ec0c65bSUsama Arif 41*6ec0c65bSUsama Arif .. code:: shell 42*6ec0c65bSUsama Arif 43*6ec0c65bSUsama Arif make PLAT=tc BL33=<path_to_uboot.bin> \ 44*6ec0c65bSUsama Arif SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={0,1} all fip 45*6ec0c65bSUsama Arif 46*6ec0c65bSUsama Arif Enable TBBR by adding the following options to the make command: 47*6ec0c65bSUsama Arif 48*6ec0c65bSUsama Arif .. code:: shell 49*6ec0c65bSUsama Arif 50*6ec0c65bSUsama Arif MBEDTLS_DIR=<path_to_mbedtls_directory> \ 51*6ec0c65bSUsama Arif TRUSTED_BOARD_BOOT=1 \ 52*6ec0c65bSUsama Arif GENERATE_COT=1 \ 53*6ec0c65bSUsama Arif ARM_ROTPK_LOCATION=devel_rsa \ 54*6ec0c65bSUsama Arif ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem 55*6ec0c65bSUsama Arif 56*6ec0c65bSUsama Arif*Copyright (c) 2020-2021, Arm Limited. All rights reserved.* 57