1Arm Fixed Virtual Platforms (FVP) 2================================= 3 4Fixed Virtual Platform (FVP) Support 5------------------------------------ 6 7This section lists the supported Arm |FVP| platforms. Please refer to the FVP 8documentation for a detailed description of the model parameter options. 9 10The latest version of the AArch64 build of TF-A has been tested on the following 11Arm FVPs without shifted affinities, and that do not support threaded CPU cores 12(64-bit host machine only). 13 14.. note:: 15 The FVP models used are Version 11.22 Build 14, unless otherwise stated. 16 17- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21) 18- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21) 19- ``FVP_Base_AEMvA`` 20- ``FVP_Base_AEMvA-AEMvA`` 21- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38) 22- ``FVP_Base_Cortex-A35x4`` 23- ``FVP_Base_Cortex-A53x4`` 24- ``FVP_Base_Cortex-A55`` 25- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` 26- ``FVP_Base_Cortex-A55x4+Cortex-A76x2`` 27- ``FVP_Base_Cortex-A57x1-A53x1`` 28- ``FVP_Base_Cortex-A57x2-A53x4`` 29- ``FVP_Base_Cortex-A57x4`` 30- ``FVP_Base_Cortex-A57x4-A53x4`` 31- ``FVP_Base_Cortex-A65`` 32- ``FVP_Base_Cortex-A65AE`` 33- ``FVP_Base_Cortex-A710x4`` (Version 11.17/21) 34- ``FVP_Base_Cortex-A72x4`` 35- ``FVP_Base_Cortex-A72x4-A53x4`` 36- ``FVP_Base_Cortex-A73x4`` 37- ``FVP_Base_Cortex-A73x4-A53x4`` 38- ``FVP_Base_Cortex-A75`` 39- ``FVP_Base_Cortex-A76`` 40- ``FVP_Base_Cortex-A76AE`` 41- ``FVP_Base_Cortex-A77`` 42- ``FVP_Base_Cortex-A78`` 43- ``FVP_Base_Cortex-A78AE`` 44- ``FVP_Base_Cortex-A78C`` 45- ``FVP_Base_Cortex-X2x4`` (Version 11.17/21) 46- ``FVP_Base_Neoverse-E1`` 47- ``FVP_Base_Neoverse-N1`` 48- ``FVP_Base_Neoverse-V1`` 49- ``FVP_Base_RevC-2xAEMvA`` 50- ``FVP_BaseR_AEMv8R`` 51- ``FVP_Morello`` (Version 0.11/33) 52- ``FVP_RD_V1`` 53- ``FVP_TC1`` 54- ``FVP_TC2`` (Version 11.23/17) 55 56The latest version of the AArch32 build of TF-A has been tested on the 57following Arm FVPs without shifted affinities, and that do not support threaded 58CPU cores (64-bit host machine only). 59 60- ``FVP_Base_AEMvA`` 61- ``FVP_Base_AEMvA-AEMvA`` 62- ``FVP_Base_Cortex-A32x4`` 63 64.. note:: 65 The ``FVP_Base_RevC-2xAEMvA`` FVP only supports shifted affinities, which 66 is not compatible with legacy GIC configurations. Therefore this FVP does not 67 support these legacy GIC configurations. 68 69The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm 70FVP website`_. The Cortex-A models listed above are also available to download 71from `Arm's website`_. 72 73.. note:: 74 The build numbers quoted above are those reported by launching the FVP 75 with the ``--version`` parameter. 76 77.. note:: 78 Linaro provides a ramdisk image in prebuilt FVP configurations and full 79 file systems that can be downloaded separately. To run an FVP with a virtio 80 file system image an additional FVP configuration option 81 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be 82 used. 83 84.. note:: 85 The software will not work on Version 1.0 of the Foundation FVP. 86 The commands below would report an ``unhandled argument`` error in this case. 87 88.. note:: 89 FVPs can be launched with ``--cadi-server`` option such that a 90 CADI-compliant debugger (for example, Arm DS-5) can connect to and control 91 its execution. 92 93.. warning:: 94 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 95 the internal synchronisation timings changed compared to older versions of 96 the models. The models can be launched with ``-Q 100`` option if they are 97 required to match the run time characteristics of the older versions. 98 99All the above platforms have been tested with `Linaro Release 20.01`_. 100 101.. _build_options_arm_fvp_platform: 102 103Arm FVP Platform Specific Build Options 104--------------------------------------- 105 106- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 107 build the topology tree within TF-A. By default TF-A is configured for dual 108 cluster topology and this option can be used to override the default value. 109 110- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 111 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 112 explained in the options below: 113 114 - ``FVP_CCI`` : The CCI driver is selected. This is the default 115 if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 116 - ``FVP_CCN`` : The CCN driver is selected. This is the default 117 if ``FVP_CLUSTER_COUNT`` > 2. 118 119- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 120 a single cluster. This option defaults to 4. 121 122- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 123 in the system. This option defaults to 1. Note that the build option 124 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 125 126- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 127 128 - ``FVP_GICV2`` : The GICv2 only driver is selected 129 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 130 131- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 132 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 133 details on HW_CONFIG. By default, this is initialized to a sensible DTS 134 file in ``fdts/`` folder depending on other build options. But some cases, 135 like shifted affinity format for MPIDR, cannot be detected at build time 136 and this option is needed to specify the appropriate DTS file. 137 138- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 139 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 140 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 141 HW_CONFIG blob instead of the DTS file. This option is useful to override 142 the default HW_CONFIG selected by the build system. 143 144- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of 145 inactive/fused CPU cores as read-only. The default value of this option 146 is ``0``, which means the redistributor pages of all CPU cores are marked 147 as read and write. 148 149Booting Firmware Update images 150------------------------------ 151 152When Firmware Update (FWU) is enabled there are at least 2 new images 153that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the 154FWU FIP. 155 156The additional fip images must be loaded with: 157 158:: 159 160 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] 161 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] 162 163The address ns_bl1u_base_address is the value of NS_BL1U_BASE. 164In the same way, the address ns_bl2u_base_address is the value of 165NS_BL2U_BASE. 166 167Booting an EL3 payload 168---------------------- 169 170The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for 171the secondary CPUs holding pen to work properly. Unfortunately, its reset value 172is undefined on the FVP platform and the FVP platform code doesn't clear it. 173Therefore, one must modify the way the model is normally invoked in order to 174clear the mailbox at start-up. 175 176One way to do that is to create an 8-byte file containing all zero bytes using 177the following command: 178 179.. code:: shell 180 181 dd if=/dev/zero of=mailbox.dat bs=1 count=8 182 183and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) 184using the following model parameters: 185 186:: 187 188 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] 189 --data=mailbox.dat@0x04000000 [Foundation FVP] 190 191To provide the model with the EL3 payload image, the following methods may be 192used: 193 194#. If the EL3 payload is able to execute in place, it may be programmed into 195 flash memory. On Base Cortex and AEM FVPs, the following model parameter 196 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already 197 used for the FIP): 198 199 :: 200 201 -C bp.flashloader1.fname="<path-to>/<el3-payload>" 202 203 On Foundation FVP, there is no flash loader component and the EL3 payload 204 may be programmed anywhere in flash using method 3 below. 205 206#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 207 command may be used to load the EL3 payload ELF image over JTAG: 208 209 :: 210 211 load <path-to>/el3-payload.elf 212 213#. The EL3 payload may be pre-loaded in volatile memory using the following 214 model parameters: 215 216 :: 217 218 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] 219 --data="<path-to>/<el3-payload>"@address [Foundation FVP] 220 221 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address 222 used when building TF-A. 223 224Booting a preloaded kernel image (Base FVP) 225------------------------------------------- 226 227The following example uses a simplified boot flow by directly jumping from the 228TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be 229useful if both the kernel and the device tree blob (DTB) are already present in 230memory (like in FVP). 231 232For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at 233address ``0x82000000``, the firmware can be built like this: 234 235.. code:: shell 236 237 CROSS_COMPILE=aarch64-none-elf- \ 238 make PLAT=fvp DEBUG=1 \ 239 RESET_TO_BL31=1 \ 240 ARM_LINUX_KERNEL_AS_BL33=1 \ 241 PRELOADED_BL33_BASE=0x80080000 \ 242 ARM_PRELOADED_DTB_BASE=0x82000000 \ 243 all fip 244 245Now, it is needed to modify the DTB so that the kernel knows the address of the 246ramdisk. The following script generates a patched DTB from the provided one, 247assuming that the ramdisk is loaded at address ``0x84000000``. Note that this 248script assumes that the user is using a ramdisk image prepared for U-Boot, like 249the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` 250offset in ``INITRD_START`` has to be removed. 251 252.. code:: bash 253 254 #!/bin/bash 255 256 # Path to the input DTB 257 KERNEL_DTB=<path-to>/<fdt> 258 # Path to the output DTB 259 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> 260 # Base address of the ramdisk 261 INITRD_BASE=0x84000000 262 # Path to the ramdisk 263 INITRD=<path-to>/<ramdisk.img> 264 265 # Skip uboot header (64 bytes) 266 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) 267 INITRD_SIZE=$(stat -Lc %s ${INITRD}) 268 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) 269 270 CHOSEN_NODE=$(echo \ 271 "/ { \ 272 chosen { \ 273 linux,initrd-start = <${INITRD_START}>; \ 274 linux,initrd-end = <${INITRD_END}>; \ 275 }; \ 276 };") 277 278 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ 279 dtc -O dtb -o ${PATCHED_KERNEL_DTB} - 280 281And the FVP binary can be run with the following command: 282 283.. code:: shell 284 285 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 286 -C pctl.startup=0.0.0.0 \ 287 -C bp.secure_memory=1 \ 288 -C cluster0.NUM_CORES=4 \ 289 -C cluster1.NUM_CORES=4 \ 290 -C cache_state_modelled=1 \ 291 -C cluster0.cpu0.RVBAR=0x04001000 \ 292 -C cluster0.cpu1.RVBAR=0x04001000 \ 293 -C cluster0.cpu2.RVBAR=0x04001000 \ 294 -C cluster0.cpu3.RVBAR=0x04001000 \ 295 -C cluster1.cpu0.RVBAR=0x04001000 \ 296 -C cluster1.cpu1.RVBAR=0x04001000 \ 297 -C cluster1.cpu2.RVBAR=0x04001000 \ 298 -C cluster1.cpu3.RVBAR=0x04001000 \ 299 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ 300 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ 301 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 302 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 303 304Obtaining the Flattened Device Trees 305^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 306 307Depending on the FVP configuration and Linux configuration used, different 308FDT files are required. FDT source files for the Foundation and Base FVPs can 309be found in the TF-A source directory under ``fdts/``. The Foundation FVP has 310a subset of the Base FVP components. For example, the Foundation FVP lacks 311CLCD and MMC support, and has only one CPU cluster. 312 313.. note:: 314 It is not recommended to use the FDTs built along the kernel because not 315 all FDTs are available from there. 316 317The dynamic configuration capability is enabled in the firmware for FVPs. 318This means that the firmware can authenticate and load the FDT if present in 319FIP. A default FDT is packaged into FIP during the build based on 320the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` 321or ``FVP_HW_CONFIG_DTS`` build options (refer to 322:ref:`build_options_arm_fvp_platform` for details on the options). 323 324- ``fvp-base-gicv2-psci.dts`` 325 326 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs 327 without shifted affinities and with Base memory map configuration. 328 329- ``fvp-base-gicv3-psci.dts`` 330 331 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs 332 without shifted affinities and with Base memory map configuration and 333 Linux GICv3 support. 334 335- ``fvp-base-gicv3-psci-1t.dts`` 336 337 For use with models such as the AEMv8-RevC Base FVP with shifted affinities, 338 single threaded CPUs, Base memory map configuration and Linux GICv3 support. 339 340- ``fvp-base-gicv3-psci-dynamiq.dts`` 341 342 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, 343 single cluster, single threaded CPUs, Base memory map configuration and Linux 344 GICv3 support. 345 346- ``fvp-foundation-gicv2-psci.dts`` 347 348 For use with Foundation FVP with Base memory map configuration. 349 350- ``fvp-foundation-gicv3-psci.dts`` 351 352 (Default) For use with Foundation FVP with Base memory map configuration 353 and Linux GICv3 support. 354 355 356Running on the Foundation FVP with reset to BL1 entrypoint 357^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 358 359The following ``Foundation_Platform`` parameters should be used to boot Linux with 3604 CPUs using the AArch64 build of TF-A. 361 362.. code:: shell 363 364 <path-to>/Foundation_Platform \ 365 --cores=4 \ 366 --arm-v8.0 \ 367 --secure-memory \ 368 --visualization \ 369 --gicv3 \ 370 --data="<path-to>/<bl1-binary>"@0x0 \ 371 --data="<path-to>/<FIP-binary>"@0x08000000 \ 372 --data="<path-to>/<kernel-binary>"@0x80080000 \ 373 --data="<path-to>/<ramdisk-binary>"@0x84000000 374 375Notes: 376 377- BL1 is loaded at the start of the Trusted ROM. 378- The Firmware Image Package is loaded at the start of NOR FLASH0. 379- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address 380 is specified via the ``load-address`` property in the ``hw-config`` node of 381 `FW_CONFIG for FVP`_. 382- The default use-case for the Foundation FVP is to use the ``--gicv3`` option 383 and enable the GICv3 device in the model. Note that without this option, 384 the Foundation FVP defaults to legacy (Versatile Express) memory map which 385 is not supported by TF-A. 386- In order for TF-A to run correctly on the Foundation FVP, the architecture 387 versions must match. The Foundation FVP defaults to the highest v8.x 388 version it supports but the default build for TF-A is for v8.0. To avoid 389 issues either start the Foundation FVP to use v8.0 architecture using the 390 ``--arm-v8.0`` option, or build TF-A with an appropriate value for 391 ``ARM_ARCH_MINOR``. 392 393Running on the AEMv8 Base FVP with reset to BL1 entrypoint 394^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 395 396The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 397with 8 CPUs using the AArch64 build of TF-A. 398 399.. code:: shell 400 401 <path-to>/FVP_Base_RevC-2xAEMv8A \ 402 -C pctl.startup=0.0.0.0 \ 403 -C bp.secure_memory=1 \ 404 -C bp.tzc_400.diagnostics=1 \ 405 -C cluster0.NUM_CORES=4 \ 406 -C cluster1.NUM_CORES=4 \ 407 -C cache_state_modelled=1 \ 408 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 409 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 410 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 411 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 412 413.. note:: 414 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires 415 a specific DTS for all the CPUs to be loaded. 416 417Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint 418^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 419 420The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 421with 8 CPUs using the AArch32 build of TF-A. 422 423.. code:: shell 424 425 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 426 -C pctl.startup=0.0.0.0 \ 427 -C bp.secure_memory=1 \ 428 -C bp.tzc_400.diagnostics=1 \ 429 -C cluster0.NUM_CORES=4 \ 430 -C cluster1.NUM_CORES=4 \ 431 -C cache_state_modelled=1 \ 432 -C cluster0.cpu0.CONFIG64=0 \ 433 -C cluster0.cpu1.CONFIG64=0 \ 434 -C cluster0.cpu2.CONFIG64=0 \ 435 -C cluster0.cpu3.CONFIG64=0 \ 436 -C cluster1.cpu0.CONFIG64=0 \ 437 -C cluster1.cpu1.CONFIG64=0 \ 438 -C cluster1.cpu2.CONFIG64=0 \ 439 -C cluster1.cpu3.CONFIG64=0 \ 440 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 441 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 442 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 443 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 444 445Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint 446^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 447 448The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 449boot Linux with 8 CPUs using the AArch64 build of TF-A. 450 451.. code:: shell 452 453 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 454 -C pctl.startup=0.0.0.0 \ 455 -C bp.secure_memory=1 \ 456 -C bp.tzc_400.diagnostics=1 \ 457 -C cache_state_modelled=1 \ 458 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 459 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 460 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 461 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 462 463Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint 464^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 465 466The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 467boot Linux with 4 CPUs using the AArch32 build of TF-A. 468 469.. code:: shell 470 471 <path-to>/FVP_Base_Cortex-A32x4 \ 472 -C pctl.startup=0.0.0.0 \ 473 -C bp.secure_memory=1 \ 474 -C bp.tzc_400.diagnostics=1 \ 475 -C cache_state_modelled=1 \ 476 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 477 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 478 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 479 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 480 481 482Running on the AEMv8 Base FVP with reset to BL31 entrypoint 483^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 484 485The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 486with 8 CPUs using the AArch64 build of TF-A. 487 488.. code:: shell 489 490 <path-to>/FVP_Base_RevC-2xAEMv8A \ 491 -C pctl.startup=0.0.0.0 \ 492 -C bp.secure_memory=1 \ 493 -C bp.tzc_400.diagnostics=1 \ 494 -C cluster0.NUM_CORES=4 \ 495 -C cluster1.NUM_CORES=4 \ 496 -C cache_state_modelled=1 \ 497 -C cluster0.cpu0.RVBAR=0x04010000 \ 498 -C cluster0.cpu1.RVBAR=0x04010000 \ 499 -C cluster0.cpu2.RVBAR=0x04010000 \ 500 -C cluster0.cpu3.RVBAR=0x04010000 \ 501 -C cluster1.cpu0.RVBAR=0x04010000 \ 502 -C cluster1.cpu1.RVBAR=0x04010000 \ 503 -C cluster1.cpu2.RVBAR=0x04010000 \ 504 -C cluster1.cpu3.RVBAR=0x04010000 \ 505 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 506 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 507 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 508 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 509 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 510 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 511 512Notes: 513 514- Position Independent Executable (PIE) support is enabled in this 515 config allowing BL31 to be loaded at any valid address for execution. 516 517- Since a FIP is not loaded when using BL31 as reset entrypoint, the 518 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` 519 parameter is needed to load the individual bootloader images in memory. 520 BL32 image is only needed if BL31 has been built to expect a Secure-EL1 521 Payload. For the same reason, the FDT needs to be compiled from the DT source 522 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` 523 parameter. 524 525- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a 526 specific DTS for all the CPUs to be loaded. 527 528- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where 529 X and Y are the cluster and CPU numbers respectively, is used to set the 530 reset vector for each core. 531 532- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require 533 changing the value of 534 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of 535 ``BL32_BASE``. 536 537 538Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint 539^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 540 541The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 542with 8 CPUs using the AArch32 build of TF-A. 543 544.. code:: shell 545 546 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 547 -C pctl.startup=0.0.0.0 \ 548 -C bp.secure_memory=1 \ 549 -C bp.tzc_400.diagnostics=1 \ 550 -C cluster0.NUM_CORES=4 \ 551 -C cluster1.NUM_CORES=4 \ 552 -C cache_state_modelled=1 \ 553 -C cluster0.cpu0.CONFIG64=0 \ 554 -C cluster0.cpu1.CONFIG64=0 \ 555 -C cluster0.cpu2.CONFIG64=0 \ 556 -C cluster0.cpu3.CONFIG64=0 \ 557 -C cluster1.cpu0.CONFIG64=0 \ 558 -C cluster1.cpu1.CONFIG64=0 \ 559 -C cluster1.cpu2.CONFIG64=0 \ 560 -C cluster1.cpu3.CONFIG64=0 \ 561 -C cluster0.cpu0.RVBAR=0x04002000 \ 562 -C cluster0.cpu1.RVBAR=0x04002000 \ 563 -C cluster0.cpu2.RVBAR=0x04002000 \ 564 -C cluster0.cpu3.RVBAR=0x04002000 \ 565 -C cluster1.cpu0.RVBAR=0x04002000 \ 566 -C cluster1.cpu1.RVBAR=0x04002000 \ 567 -C cluster1.cpu2.RVBAR=0x04002000 \ 568 -C cluster1.cpu3.RVBAR=0x04002000 \ 569 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 570 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 571 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 572 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 573 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 574 575.. note:: 576 Position Independent Executable (PIE) support is enabled in this 577 config allowing SP_MIN to be loaded at any valid address for execution. 578 579Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint 580^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 581 582The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 583boot Linux with 8 CPUs using the AArch64 build of TF-A. 584 585.. code:: shell 586 587 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 588 -C pctl.startup=0.0.0.0 \ 589 -C bp.secure_memory=1 \ 590 -C bp.tzc_400.diagnostics=1 \ 591 -C cache_state_modelled=1 \ 592 -C cluster0.cpu0.RVBARADDR=0x04010000 \ 593 -C cluster0.cpu1.RVBARADDR=0x04010000 \ 594 -C cluster0.cpu2.RVBARADDR=0x04010000 \ 595 -C cluster0.cpu3.RVBARADDR=0x04010000 \ 596 -C cluster1.cpu0.RVBARADDR=0x04010000 \ 597 -C cluster1.cpu1.RVBARADDR=0x04010000 \ 598 -C cluster1.cpu2.RVBARADDR=0x04010000 \ 599 -C cluster1.cpu3.RVBARADDR=0x04010000 \ 600 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 601 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 602 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 603 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 604 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 605 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 606 607Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint 608^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 609 610The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 611boot Linux with 4 CPUs using the AArch32 build of TF-A. 612 613.. code:: shell 614 615 <path-to>/FVP_Base_Cortex-A32x4 \ 616 -C pctl.startup=0.0.0.0 \ 617 -C bp.secure_memory=1 \ 618 -C bp.tzc_400.diagnostics=1 \ 619 -C cache_state_modelled=1 \ 620 -C cluster0.cpu0.RVBARADDR=0x04002000 \ 621 -C cluster0.cpu1.RVBARADDR=0x04002000 \ 622 -C cluster0.cpu2.RVBARADDR=0x04002000 \ 623 -C cluster0.cpu3.RVBARADDR=0x04002000 \ 624 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 625 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 626 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 627 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 628 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 629 630-------------- 631 632*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 633 634.. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts 635.. _Arm's website: `FVP models`_ 636.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms 637.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01 638.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms 639