1Arm Fixed Virtual Platforms (FVP) 2================================= 3 4Fixed Virtual Platform (FVP) Support 5------------------------------------ 6 7This section lists the supported Arm |FVP| platforms. Please refer to the FVP 8documentation for a detailed description of the model parameter options. 9 10The latest version of the AArch64 build of TF-A has been tested on the following 11Arm FVPs without shifted affinities, and that do not support threaded CPU cores 12(64-bit host machine only). 13 14.. note:: 15 The FVP models used are Version 11.19 Build 14, unless otherwise stated. 16 17- ``Foundation_Platform`` 18- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21) 19- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21) 20- ``FVP_Base_AEMvA`` 21- ``FVP_Base_AEMvA-AEMvA`` 22- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38) 23- ``FVP_Base_Cortex-A35x4`` 24- ``FVP_Base_Cortex-A53x4`` 25- ``FVP_Base_Cortex-A55`` 26- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` 27- ``FVP_Base_Cortex-A55x4+Cortex-A76x2`` 28- ``FVP_Base_Cortex-A57x1-A53x1`` 29- ``FVP_Base_Cortex-A57x2-A53x4`` 30- ``FVP_Base_Cortex-A57x4`` 31- ``FVP_Base_Cortex-A57x4-A53x4`` 32- ``FVP_Base_Cortex-A65`` 33- ``FVP_Base_Cortex-A65AE`` 34- ``FVP_Base_Cortex-A710x4`` (Version 11.17/21) 35- ``FVP_Base_Cortex-A72x4`` 36- ``FVP_Base_Cortex-A72x4-A53x4`` 37- ``FVP_Base_Cortex-A73x4`` 38- ``FVP_Base_Cortex-A73x4-A53x4`` 39- ``FVP_Base_Cortex-A75`` 40- ``FVP_Base_Cortex-A76`` 41- ``FVP_Base_Cortex-A76AE`` 42- ``FVP_Base_Cortex-A77`` 43- ``FVP_Base_Cortex-A78`` 44- ``FVP_Base_Cortex-A78C`` 45- ``FVP_Base_Cortex-X2x4`` (Version 11.17/21) 46- ``FVP_Base_Neoverse-E1`` 47- ``FVP_Base_Neoverse-N1`` 48- ``FVP_Base_Neoverse-N2x4`` (Version 11.16/16) 49- ``FVP_Base_Neoverse-V1`` 50- ``FVP_Base_RevC-2xAEMvA`` 51- ``FVP_Morello`` (Version 0.11/33) 52- ``FVP_RD_E1_edge`` (Version 11.17/29) 53- ``FVP_RD_V1`` (Version 11.17/29) 54- ``FVP_TC0`` (Version 11.17/18) 55- ``FVP_TC1`` (Version 11.17/33) 56- ``FVP_TC2`` (Version 11.18/28) 57 58The latest version of the AArch32 build of TF-A has been tested on the 59following Arm FVPs without shifted affinities, and that do not support threaded 60CPU cores (64-bit host machine only). 61 62- ``FVP_Base_AEMvA`` 63- ``FVP_Base_AEMvA-AEMvA`` 64- ``FVP_Base_Cortex-A32x4`` 65 66.. note:: 67 The ``FVP_Base_RevC-2xAEMvA`` FVP only supports shifted affinities, which 68 is not compatible with legacy GIC configurations. Therefore this FVP does not 69 support these legacy GIC configurations. 70 71The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm 72FVP website`_. The Cortex-A models listed above are also available to download 73from `Arm's website`_. 74 75.. note:: 76 The build numbers quoted above are those reported by launching the FVP 77 with the ``--version`` parameter. 78 79.. note:: 80 Linaro provides a ramdisk image in prebuilt FVP configurations and full 81 file systems that can be downloaded separately. To run an FVP with a virtio 82 file system image an additional FVP configuration option 83 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be 84 used. 85 86.. note:: 87 The software will not work on Version 1.0 of the Foundation FVP. 88 The commands below would report an ``unhandled argument`` error in this case. 89 90.. note:: 91 FVPs can be launched with ``--cadi-server`` option such that a 92 CADI-compliant debugger (for example, Arm DS-5) can connect to and control 93 its execution. 94 95.. warning:: 96 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 97 the internal synchronisation timings changed compared to older versions of 98 the models. The models can be launched with ``-Q 100`` option if they are 99 required to match the run time characteristics of the older versions. 100 101All the above platforms have been tested with `Linaro Release 20.01`_. 102 103.. _build_options_arm_fvp_platform: 104 105Arm FVP Platform Specific Build Options 106--------------------------------------- 107 108- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 109 build the topology tree within TF-A. By default TF-A is configured for dual 110 cluster topology and this option can be used to override the default value. 111 112- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 113 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 114 explained in the options below: 115 116 - ``FVP_CCI`` : The CCI driver is selected. This is the default 117 if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 118 - ``FVP_CCN`` : The CCN driver is selected. This is the default 119 if ``FVP_CLUSTER_COUNT`` > 2. 120 121- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 122 a single cluster. This option defaults to 4. 123 124- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 125 in the system. This option defaults to 1. Note that the build option 126 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 127 128- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 129 130 - ``FVP_GICV2`` : The GICv2 only driver is selected 131 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 132 133- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 134 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 135 details on HW_CONFIG. By default, this is initialized to a sensible DTS 136 file in ``fdts/`` folder depending on other build options. But some cases, 137 like shifted affinity format for MPIDR, cannot be detected at build time 138 and this option is needed to specify the appropriate DTS file. 139 140- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 141 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 142 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 143 HW_CONFIG blob instead of the DTS file. This option is useful to override 144 the default HW_CONFIG selected by the build system. 145 146- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of 147 inactive/fused CPU cores as read-only. The default value of this option 148 is ``0``, which means the redistributor pages of all CPU cores are marked 149 as read and write. 150 151Booting Firmware Update images 152------------------------------ 153 154When Firmware Update (FWU) is enabled there are at least 2 new images 155that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the 156FWU FIP. 157 158The additional fip images must be loaded with: 159 160:: 161 162 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] 163 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] 164 165The address ns_bl1u_base_address is the value of NS_BL1U_BASE. 166In the same way, the address ns_bl2u_base_address is the value of 167NS_BL2U_BASE. 168 169Booting an EL3 payload 170---------------------- 171 172The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for 173the secondary CPUs holding pen to work properly. Unfortunately, its reset value 174is undefined on the FVP platform and the FVP platform code doesn't clear it. 175Therefore, one must modify the way the model is normally invoked in order to 176clear the mailbox at start-up. 177 178One way to do that is to create an 8-byte file containing all zero bytes using 179the following command: 180 181.. code:: shell 182 183 dd if=/dev/zero of=mailbox.dat bs=1 count=8 184 185and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) 186using the following model parameters: 187 188:: 189 190 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] 191 --data=mailbox.dat@0x04000000 [Foundation FVP] 192 193To provide the model with the EL3 payload image, the following methods may be 194used: 195 196#. If the EL3 payload is able to execute in place, it may be programmed into 197 flash memory. On Base Cortex and AEM FVPs, the following model parameter 198 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already 199 used for the FIP): 200 201 :: 202 203 -C bp.flashloader1.fname="<path-to>/<el3-payload>" 204 205 On Foundation FVP, there is no flash loader component and the EL3 payload 206 may be programmed anywhere in flash using method 3 below. 207 208#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 209 command may be used to load the EL3 payload ELF image over JTAG: 210 211 :: 212 213 load <path-to>/el3-payload.elf 214 215#. The EL3 payload may be pre-loaded in volatile memory using the following 216 model parameters: 217 218 :: 219 220 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] 221 --data="<path-to>/<el3-payload>"@address [Foundation FVP] 222 223 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address 224 used when building TF-A. 225 226Booting a preloaded kernel image (Base FVP) 227------------------------------------------- 228 229The following example uses a simplified boot flow by directly jumping from the 230TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be 231useful if both the kernel and the device tree blob (DTB) are already present in 232memory (like in FVP). 233 234For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at 235address ``0x82000000``, the firmware can be built like this: 236 237.. code:: shell 238 239 CROSS_COMPILE=aarch64-none-elf- \ 240 make PLAT=fvp DEBUG=1 \ 241 RESET_TO_BL31=1 \ 242 ARM_LINUX_KERNEL_AS_BL33=1 \ 243 PRELOADED_BL33_BASE=0x80080000 \ 244 ARM_PRELOADED_DTB_BASE=0x82000000 \ 245 all fip 246 247Now, it is needed to modify the DTB so that the kernel knows the address of the 248ramdisk. The following script generates a patched DTB from the provided one, 249assuming that the ramdisk is loaded at address ``0x84000000``. Note that this 250script assumes that the user is using a ramdisk image prepared for U-Boot, like 251the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` 252offset in ``INITRD_START`` has to be removed. 253 254.. code:: bash 255 256 #!/bin/bash 257 258 # Path to the input DTB 259 KERNEL_DTB=<path-to>/<fdt> 260 # Path to the output DTB 261 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> 262 # Base address of the ramdisk 263 INITRD_BASE=0x84000000 264 # Path to the ramdisk 265 INITRD=<path-to>/<ramdisk.img> 266 267 # Skip uboot header (64 bytes) 268 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) 269 INITRD_SIZE=$(stat -Lc %s ${INITRD}) 270 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) 271 272 CHOSEN_NODE=$(echo \ 273 "/ { \ 274 chosen { \ 275 linux,initrd-start = <${INITRD_START}>; \ 276 linux,initrd-end = <${INITRD_END}>; \ 277 }; \ 278 };") 279 280 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ 281 dtc -O dtb -o ${PATCHED_KERNEL_DTB} - 282 283And the FVP binary can be run with the following command: 284 285.. code:: shell 286 287 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 288 -C pctl.startup=0.0.0.0 \ 289 -C bp.secure_memory=1 \ 290 -C cluster0.NUM_CORES=4 \ 291 -C cluster1.NUM_CORES=4 \ 292 -C cache_state_modelled=1 \ 293 -C cluster0.cpu0.RVBAR=0x04001000 \ 294 -C cluster0.cpu1.RVBAR=0x04001000 \ 295 -C cluster0.cpu2.RVBAR=0x04001000 \ 296 -C cluster0.cpu3.RVBAR=0x04001000 \ 297 -C cluster1.cpu0.RVBAR=0x04001000 \ 298 -C cluster1.cpu1.RVBAR=0x04001000 \ 299 -C cluster1.cpu2.RVBAR=0x04001000 \ 300 -C cluster1.cpu3.RVBAR=0x04001000 \ 301 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ 302 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ 303 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 304 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 305 306Obtaining the Flattened Device Trees 307^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 308 309Depending on the FVP configuration and Linux configuration used, different 310FDT files are required. FDT source files for the Foundation and Base FVPs can 311be found in the TF-A source directory under ``fdts/``. The Foundation FVP has 312a subset of the Base FVP components. For example, the Foundation FVP lacks 313CLCD and MMC support, and has only one CPU cluster. 314 315.. note:: 316 It is not recommended to use the FDTs built along the kernel because not 317 all FDTs are available from there. 318 319The dynamic configuration capability is enabled in the firmware for FVPs. 320This means that the firmware can authenticate and load the FDT if present in 321FIP. A default FDT is packaged into FIP during the build based on 322the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` 323or ``FVP_HW_CONFIG_DTS`` build options (refer to 324:ref:`build_options_arm_fvp_platform` for details on the options). 325 326- ``fvp-base-gicv2-psci.dts`` 327 328 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs 329 without shifted affinities and with Base memory map configuration. 330 331- ``fvp-base-gicv3-psci.dts`` 332 333 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs 334 without shifted affinities and with Base memory map configuration and 335 Linux GICv3 support. 336 337- ``fvp-base-gicv3-psci-1t.dts`` 338 339 For use with models such as the AEMv8-RevC Base FVP with shifted affinities, 340 single threaded CPUs, Base memory map configuration and Linux GICv3 support. 341 342- ``fvp-base-gicv3-psci-dynamiq.dts`` 343 344 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, 345 single cluster, single threaded CPUs, Base memory map configuration and Linux 346 GICv3 support. 347 348- ``fvp-foundation-gicv2-psci.dts`` 349 350 For use with Foundation FVP with Base memory map configuration. 351 352- ``fvp-foundation-gicv3-psci.dts`` 353 354 (Default) For use with Foundation FVP with Base memory map configuration 355 and Linux GICv3 support. 356 357 358Running on the Foundation FVP with reset to BL1 entrypoint 359^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 360 361The following ``Foundation_Platform`` parameters should be used to boot Linux with 3624 CPUs using the AArch64 build of TF-A. 363 364.. code:: shell 365 366 <path-to>/Foundation_Platform \ 367 --cores=4 \ 368 --arm-v8.0 \ 369 --secure-memory \ 370 --visualization \ 371 --gicv3 \ 372 --data="<path-to>/<bl1-binary>"@0x0 \ 373 --data="<path-to>/<FIP-binary>"@0x08000000 \ 374 --data="<path-to>/<kernel-binary>"@0x80080000 \ 375 --data="<path-to>/<ramdisk-binary>"@0x84000000 376 377Notes: 378 379- BL1 is loaded at the start of the Trusted ROM. 380- The Firmware Image Package is loaded at the start of NOR FLASH0. 381- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address 382 is specified via the ``load-address`` property in the ``hw-config`` node of 383 `FW_CONFIG for FVP`_. 384- The default use-case for the Foundation FVP is to use the ``--gicv3`` option 385 and enable the GICv3 device in the model. Note that without this option, 386 the Foundation FVP defaults to legacy (Versatile Express) memory map which 387 is not supported by TF-A. 388- In order for TF-A to run correctly on the Foundation FVP, the architecture 389 versions must match. The Foundation FVP defaults to the highest v8.x 390 version it supports but the default build for TF-A is for v8.0. To avoid 391 issues either start the Foundation FVP to use v8.0 architecture using the 392 ``--arm-v8.0`` option, or build TF-A with an appropriate value for 393 ``ARM_ARCH_MINOR``. 394 395Running on the AEMv8 Base FVP with reset to BL1 entrypoint 396^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 397 398The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 399with 8 CPUs using the AArch64 build of TF-A. 400 401.. code:: shell 402 403 <path-to>/FVP_Base_RevC-2xAEMv8A \ 404 -C pctl.startup=0.0.0.0 \ 405 -C bp.secure_memory=1 \ 406 -C bp.tzc_400.diagnostics=1 \ 407 -C cluster0.NUM_CORES=4 \ 408 -C cluster1.NUM_CORES=4 \ 409 -C cache_state_modelled=1 \ 410 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 411 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 412 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 413 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 414 415.. note:: 416 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires 417 a specific DTS for all the CPUs to be loaded. 418 419Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint 420^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 421 422The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 423with 8 CPUs using the AArch32 build of TF-A. 424 425.. code:: shell 426 427 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 428 -C pctl.startup=0.0.0.0 \ 429 -C bp.secure_memory=1 \ 430 -C bp.tzc_400.diagnostics=1 \ 431 -C cluster0.NUM_CORES=4 \ 432 -C cluster1.NUM_CORES=4 \ 433 -C cache_state_modelled=1 \ 434 -C cluster0.cpu0.CONFIG64=0 \ 435 -C cluster0.cpu1.CONFIG64=0 \ 436 -C cluster0.cpu2.CONFIG64=0 \ 437 -C cluster0.cpu3.CONFIG64=0 \ 438 -C cluster1.cpu0.CONFIG64=0 \ 439 -C cluster1.cpu1.CONFIG64=0 \ 440 -C cluster1.cpu2.CONFIG64=0 \ 441 -C cluster1.cpu3.CONFIG64=0 \ 442 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 443 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 444 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 445 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 446 447Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint 448^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 449 450The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 451boot Linux with 8 CPUs using the AArch64 build of TF-A. 452 453.. code:: shell 454 455 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 456 -C pctl.startup=0.0.0.0 \ 457 -C bp.secure_memory=1 \ 458 -C bp.tzc_400.diagnostics=1 \ 459 -C cache_state_modelled=1 \ 460 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 461 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 462 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 463 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 464 465Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint 466^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 467 468The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 469boot Linux with 4 CPUs using the AArch32 build of TF-A. 470 471.. code:: shell 472 473 <path-to>/FVP_Base_Cortex-A32x4 \ 474 -C pctl.startup=0.0.0.0 \ 475 -C bp.secure_memory=1 \ 476 -C bp.tzc_400.diagnostics=1 \ 477 -C cache_state_modelled=1 \ 478 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 479 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 480 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 481 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 482 483 484Running on the AEMv8 Base FVP with reset to BL31 entrypoint 485^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 486 487The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 488with 8 CPUs using the AArch64 build of TF-A. 489 490.. code:: shell 491 492 <path-to>/FVP_Base_RevC-2xAEMv8A \ 493 -C pctl.startup=0.0.0.0 \ 494 -C bp.secure_memory=1 \ 495 -C bp.tzc_400.diagnostics=1 \ 496 -C cluster0.NUM_CORES=4 \ 497 -C cluster1.NUM_CORES=4 \ 498 -C cache_state_modelled=1 \ 499 -C cluster0.cpu0.RVBAR=0x04010000 \ 500 -C cluster0.cpu1.RVBAR=0x04010000 \ 501 -C cluster0.cpu2.RVBAR=0x04010000 \ 502 -C cluster0.cpu3.RVBAR=0x04010000 \ 503 -C cluster1.cpu0.RVBAR=0x04010000 \ 504 -C cluster1.cpu1.RVBAR=0x04010000 \ 505 -C cluster1.cpu2.RVBAR=0x04010000 \ 506 -C cluster1.cpu3.RVBAR=0x04010000 \ 507 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 508 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 509 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 510 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 511 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 512 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 513 514Notes: 515 516- Position Independent Executable (PIE) support is enabled in this 517 config allowing BL31 to be loaded at any valid address for execution. 518 519- Since a FIP is not loaded when using BL31 as reset entrypoint, the 520 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` 521 parameter is needed to load the individual bootloader images in memory. 522 BL32 image is only needed if BL31 has been built to expect a Secure-EL1 523 Payload. For the same reason, the FDT needs to be compiled from the DT source 524 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` 525 parameter. 526 527- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a 528 specific DTS for all the CPUs to be loaded. 529 530- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where 531 X and Y are the cluster and CPU numbers respectively, is used to set the 532 reset vector for each core. 533 534- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require 535 changing the value of 536 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of 537 ``BL32_BASE``. 538 539 540Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint 541^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 542 543The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 544with 8 CPUs using the AArch32 build of TF-A. 545 546.. code:: shell 547 548 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 549 -C pctl.startup=0.0.0.0 \ 550 -C bp.secure_memory=1 \ 551 -C bp.tzc_400.diagnostics=1 \ 552 -C cluster0.NUM_CORES=4 \ 553 -C cluster1.NUM_CORES=4 \ 554 -C cache_state_modelled=1 \ 555 -C cluster0.cpu0.CONFIG64=0 \ 556 -C cluster0.cpu1.CONFIG64=0 \ 557 -C cluster0.cpu2.CONFIG64=0 \ 558 -C cluster0.cpu3.CONFIG64=0 \ 559 -C cluster1.cpu0.CONFIG64=0 \ 560 -C cluster1.cpu1.CONFIG64=0 \ 561 -C cluster1.cpu2.CONFIG64=0 \ 562 -C cluster1.cpu3.CONFIG64=0 \ 563 -C cluster0.cpu0.RVBAR=0x04002000 \ 564 -C cluster0.cpu1.RVBAR=0x04002000 \ 565 -C cluster0.cpu2.RVBAR=0x04002000 \ 566 -C cluster0.cpu3.RVBAR=0x04002000 \ 567 -C cluster1.cpu0.RVBAR=0x04002000 \ 568 -C cluster1.cpu1.RVBAR=0x04002000 \ 569 -C cluster1.cpu2.RVBAR=0x04002000 \ 570 -C cluster1.cpu3.RVBAR=0x04002000 \ 571 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 572 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 573 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 574 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 575 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 576 577.. note:: 578 Position Independent Executable (PIE) support is enabled in this 579 config allowing SP_MIN to be loaded at any valid address for execution. 580 581Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint 582^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 583 584The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 585boot Linux with 8 CPUs using the AArch64 build of TF-A. 586 587.. code:: shell 588 589 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 590 -C pctl.startup=0.0.0.0 \ 591 -C bp.secure_memory=1 \ 592 -C bp.tzc_400.diagnostics=1 \ 593 -C cache_state_modelled=1 \ 594 -C cluster0.cpu0.RVBARADDR=0x04010000 \ 595 -C cluster0.cpu1.RVBARADDR=0x04010000 \ 596 -C cluster0.cpu2.RVBARADDR=0x04010000 \ 597 -C cluster0.cpu3.RVBARADDR=0x04010000 \ 598 -C cluster1.cpu0.RVBARADDR=0x04010000 \ 599 -C cluster1.cpu1.RVBARADDR=0x04010000 \ 600 -C cluster1.cpu2.RVBARADDR=0x04010000 \ 601 -C cluster1.cpu3.RVBARADDR=0x04010000 \ 602 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 603 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 604 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 605 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 606 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 607 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 608 609Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint 610^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 611 612The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 613boot Linux with 4 CPUs using the AArch32 build of TF-A. 614 615.. code:: shell 616 617 <path-to>/FVP_Base_Cortex-A32x4 \ 618 -C pctl.startup=0.0.0.0 \ 619 -C bp.secure_memory=1 \ 620 -C bp.tzc_400.diagnostics=1 \ 621 -C cache_state_modelled=1 \ 622 -C cluster0.cpu0.RVBARADDR=0x04002000 \ 623 -C cluster0.cpu1.RVBARADDR=0x04002000 \ 624 -C cluster0.cpu2.RVBARADDR=0x04002000 \ 625 -C cluster0.cpu3.RVBARADDR=0x04002000 \ 626 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 627 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 628 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 629 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 630 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 631 632-------------- 633 634*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* 635 636.. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts 637.. _Arm's website: `FVP models`_ 638.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms 639.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01 640.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms 641