1Arm Fixed Virtual Platforms (FVP) 2================================= 3 4Fixed Virtual Platform (FVP) Support 5------------------------------------ 6 7This section lists the supported Arm |FVP| platforms. Please refer to the FVP 8documentation for a detailed description of the model parameter options. 9 10The latest version of the AArch64 build of TF-A has been tested on the following 11Arm FVPs without shifted affinities, and that do not support threaded CPU cores 12(64-bit host machine only). 13 14.. note:: 15 The FVP models used are Version 11.9 Build 41, unless otherwise stated. 16 17- ``FVP_Base_AEMv8A-AEMv8A`` 18- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` 19- ``FVP_Base_RevC-2xAEMv8A`` 20- ``FVP_Base_Cortex-A32x4`` 21- ``FVP_Base_Cortex-A35x4`` 22- ``FVP_Base_Cortex-A53x4`` 23- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` 24- ``FVP_Base_Cortex-A55x4`` 25- ``FVP_Base_Cortex-A57x1-A53x1`` 26- ``FVP_Base_Cortex-A57x2-A53x4`` 27- ``FVP_Base_Cortex-A57x4-A53x4`` 28- ``FVP_Base_Cortex-A57x4`` 29- ``FVP_Base_Cortex-A65x4`` 30- ``FVP_Base_Cortex-A65AEx8`` 31- ``FVP_Base_Cortex-A72x4-A53x4`` 32- ``FVP_Base_Cortex-A72x4`` 33- ``FVP_Base_Cortex-A73x4-A53x4`` 34- ``FVP_Base_Cortex-A73x4`` 35- ``FVP_Base_Cortex-A75x4`` 36- ``FVP_Base_Cortex-A76x4`` 37- ``FVP_Base_Cortex-A76AEx4`` 38- ``FVP_Base_Cortex-A76AEx8`` 39- ``FVP_Base_Cortex-A77x4`` 40- ``FVP_Base_Neoverse-E1x1`` 41- ``FVP_Base_Neoverse-E1x2`` 42- ``FVP_Base_Neoverse-E1x4`` 43- ``FVP_Base_Neoverse-N1x4`` 44- ``FVP_Base_Zeusx4`` 45- ``FVP_CSS_SGI-575`` (Version 11.10 build 36) 46- ``FVP_CSS_SGM-775`` 47- ``FVP_RD_E1_edge`` (Version 11.10 build 36) 48- ``FVP_RD_N1_edge`` (Version 11.10 build 36) 49- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36) 50- ``Foundation_Platform`` 51 52The latest version of the AArch32 build of TF-A has been tested on the 53following Arm FVPs without shifted affinities, and that do not support threaded 54CPU cores (64-bit host machine only). 55 56- ``FVP_Base_AEMv8A-AEMv8A`` 57- ``FVP_Base_Cortex-A32x4`` 58 59.. note:: 60 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which 61 is not compatible with legacy GIC configurations. Therefore this FVP does not 62 support these legacy GIC configurations. 63 64The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm 65FVP website`_. The Cortex-A models listed above are also available to download 66from `Arm's website`_. 67 68.. note:: 69 The build numbers quoted above are those reported by launching the FVP 70 with the ``--version`` parameter. 71 72.. note:: 73 Linaro provides a ramdisk image in prebuilt FVP configurations and full 74 file systems that can be downloaded separately. To run an FVP with a virtio 75 file system image an additional FVP configuration option 76 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be 77 used. 78 79.. note:: 80 The software will not work on Version 1.0 of the Foundation FVP. 81 The commands below would report an ``unhandled argument`` error in this case. 82 83.. note:: 84 FVPs can be launched with ``--cadi-server`` option such that a 85 CADI-compliant debugger (for example, Arm DS-5) can connect to and control 86 its execution. 87 88.. warning:: 89 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 90 the internal synchronisation timings changed compared to older versions of 91 the models. The models can be launched with ``-Q 100`` option if they are 92 required to match the run time characteristics of the older versions. 93 94All the above platforms have been tested with `Linaro Release 19.06`_. 95 96.. _build_options_arm_fvp_platform: 97 98Arm FVP Platform Specific Build Options 99--------------------------------------- 100 101- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 102 build the topology tree within TF-A. By default TF-A is configured for dual 103 cluster topology and this option can be used to override the default value. 104 105- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 106 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 107 explained in the options below: 108 109 - ``FVP_CCI`` : The CCI driver is selected. This is the default 110 if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 111 - ``FVP_CCN`` : The CCN driver is selected. This is the default 112 if ``FVP_CLUSTER_COUNT`` > 2. 113 114- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 115 a single cluster. This option defaults to 4. 116 117- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 118 in the system. This option defaults to 1. Note that the build option 119 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 120 121- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 122 123 - ``FVP_GICV2`` : The GICv2 only driver is selected 124 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 125 126- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 127 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 128 details on HW_CONFIG. By default, this is initialized to a sensible DTS 129 file in ``fdts/`` folder depending on other build options. But some cases, 130 like shifted affinity format for MPIDR, cannot be detected at build time 131 and this option is needed to specify the appropriate DTS file. 132 133- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 134 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 135 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 136 HW_CONFIG blob instead of the DTS file. This option is useful to override 137 the default HW_CONFIG selected by the build system. 138 139Booting Firmware Update images 140------------------------------ 141 142When Firmware Update (FWU) is enabled there are at least 2 new images 143that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the 144FWU FIP. 145 146The additional fip images must be loaded with: 147 148:: 149 150 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] 151 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] 152 153The address ns_bl1u_base_address is the value of NS_BL1U_BASE. 154In the same way, the address ns_bl2u_base_address is the value of 155NS_BL2U_BASE. 156 157Booting an EL3 payload 158---------------------- 159 160The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for 161the secondary CPUs holding pen to work properly. Unfortunately, its reset value 162is undefined on the FVP platform and the FVP platform code doesn't clear it. 163Therefore, one must modify the way the model is normally invoked in order to 164clear the mailbox at start-up. 165 166One way to do that is to create an 8-byte file containing all zero bytes using 167the following command: 168 169.. code:: shell 170 171 dd if=/dev/zero of=mailbox.dat bs=1 count=8 172 173and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) 174using the following model parameters: 175 176:: 177 178 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] 179 --data=mailbox.dat@0x04000000 [Foundation FVP] 180 181To provide the model with the EL3 payload image, the following methods may be 182used: 183 184#. If the EL3 payload is able to execute in place, it may be programmed into 185 flash memory. On Base Cortex and AEM FVPs, the following model parameter 186 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already 187 used for the FIP): 188 189 :: 190 191 -C bp.flashloader1.fname="<path-to>/<el3-payload>" 192 193 On Foundation FVP, there is no flash loader component and the EL3 payload 194 may be programmed anywhere in flash using method 3 below. 195 196#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 197 command may be used to load the EL3 payload ELF image over JTAG: 198 199 :: 200 201 load <path-to>/el3-payload.elf 202 203#. The EL3 payload may be pre-loaded in volatile memory using the following 204 model parameters: 205 206 :: 207 208 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] 209 --data="<path-to>/<el3-payload>"@address [Foundation FVP] 210 211 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address 212 used when building TF-A. 213 214Booting a preloaded kernel image (Base FVP) 215------------------------------------------- 216 217The following example uses a simplified boot flow by directly jumping from the 218TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be 219useful if both the kernel and the device tree blob (DTB) are already present in 220memory (like in FVP). 221 222For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at 223address ``0x82000000``, the firmware can be built like this: 224 225.. code:: shell 226 227 CROSS_COMPILE=aarch64-none-elf- \ 228 make PLAT=fvp DEBUG=1 \ 229 RESET_TO_BL31=1 \ 230 ARM_LINUX_KERNEL_AS_BL33=1 \ 231 PRELOADED_BL33_BASE=0x80080000 \ 232 ARM_PRELOADED_DTB_BASE=0x82000000 \ 233 all fip 234 235Now, it is needed to modify the DTB so that the kernel knows the address of the 236ramdisk. The following script generates a patched DTB from the provided one, 237assuming that the ramdisk is loaded at address ``0x84000000``. Note that this 238script assumes that the user is using a ramdisk image prepared for U-Boot, like 239the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` 240offset in ``INITRD_START`` has to be removed. 241 242.. code:: bash 243 244 #!/bin/bash 245 246 # Path to the input DTB 247 KERNEL_DTB=<path-to>/<fdt> 248 # Path to the output DTB 249 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> 250 # Base address of the ramdisk 251 INITRD_BASE=0x84000000 252 # Path to the ramdisk 253 INITRD=<path-to>/<ramdisk.img> 254 255 # Skip uboot header (64 bytes) 256 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) 257 INITRD_SIZE=$(stat -Lc %s ${INITRD}) 258 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) 259 260 CHOSEN_NODE=$(echo \ 261 "/ { \ 262 chosen { \ 263 linux,initrd-start = <${INITRD_START}>; \ 264 linux,initrd-end = <${INITRD_END}>; \ 265 }; \ 266 };") 267 268 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ 269 dtc -O dtb -o ${PATCHED_KERNEL_DTB} - 270 271And the FVP binary can be run with the following command: 272 273.. code:: shell 274 275 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 276 -C pctl.startup=0.0.0.0 \ 277 -C bp.secure_memory=1 \ 278 -C cluster0.NUM_CORES=4 \ 279 -C cluster1.NUM_CORES=4 \ 280 -C cache_state_modelled=1 \ 281 -C cluster0.cpu0.RVBAR=0x04001000 \ 282 -C cluster0.cpu1.RVBAR=0x04001000 \ 283 -C cluster0.cpu2.RVBAR=0x04001000 \ 284 -C cluster0.cpu3.RVBAR=0x04001000 \ 285 -C cluster1.cpu0.RVBAR=0x04001000 \ 286 -C cluster1.cpu1.RVBAR=0x04001000 \ 287 -C cluster1.cpu2.RVBAR=0x04001000 \ 288 -C cluster1.cpu3.RVBAR=0x04001000 \ 289 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ 290 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ 291 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 292 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 293 294Obtaining the Flattened Device Trees 295^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 296 297Depending on the FVP configuration and Linux configuration used, different 298FDT files are required. FDT source files for the Foundation and Base FVPs can 299be found in the TF-A source directory under ``fdts/``. The Foundation FVP has 300a subset of the Base FVP components. For example, the Foundation FVP lacks 301CLCD and MMC support, and has only one CPU cluster. 302 303.. note:: 304 It is not recommended to use the FDTs built along the kernel because not 305 all FDTs are available from there. 306 307The dynamic configuration capability is enabled in the firmware for FVPs. 308This means that the firmware can authenticate and load the FDT if present in 309FIP. A default FDT is packaged into FIP during the build based on 310the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` 311or ``FVP_HW_CONFIG_DTS`` build options (refer to 312:ref:`build_options_arm_fvp_platform` for details on the options). 313 314- ``fvp-base-gicv2-psci.dts`` 315 316 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 317 affinities and with Base memory map configuration. 318 319- ``fvp-base-gicv2-psci-aarch32.dts`` 320 321 For use with models such as the Cortex-A32 Base FVPs without shifted 322 affinities and running Linux in AArch32 state with Base memory map 323 configuration. 324 325- ``fvp-base-gicv3-psci.dts`` 326 327 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 328 affinities and with Base memory map configuration and Linux GICv3 support. 329 330- ``fvp-base-gicv3-psci-1t.dts`` 331 332 For use with models such as the AEMv8-RevC Base FVP with shifted affinities, 333 single threaded CPUs, Base memory map configuration and Linux GICv3 support. 334 335- ``fvp-base-gicv3-psci-dynamiq.dts`` 336 337 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, 338 single cluster, single threaded CPUs, Base memory map configuration and Linux 339 GICv3 support. 340 341- ``fvp-base-gicv3-psci-aarch32.dts`` 342 343 For use with models such as the Cortex-A32 Base FVPs without shifted 344 affinities and running Linux in AArch32 state with Base memory map 345 configuration and Linux GICv3 support. 346 347- ``fvp-foundation-gicv2-psci.dts`` 348 349 For use with Foundation FVP with Base memory map configuration. 350 351- ``fvp-foundation-gicv3-psci.dts`` 352 353 (Default) For use with Foundation FVP with Base memory map configuration 354 and Linux GICv3 support. 355 356 357Running on the Foundation FVP with reset to BL1 entrypoint 358^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 359 360The following ``Foundation_Platform`` parameters should be used to boot Linux with 3614 CPUs using the AArch64 build of TF-A. 362 363.. code:: shell 364 365 <path-to>/Foundation_Platform \ 366 --cores=4 \ 367 --arm-v8.0 \ 368 --secure-memory \ 369 --visualization \ 370 --gicv3 \ 371 --data="<path-to>/<bl1-binary>"@0x0 \ 372 --data="<path-to>/<FIP-binary>"@0x08000000 \ 373 --data="<path-to>/<kernel-binary>"@0x80080000 \ 374 --data="<path-to>/<ramdisk-binary>"@0x84000000 375 376Notes: 377 378- BL1 is loaded at the start of the Trusted ROM. 379- The Firmware Image Package is loaded at the start of NOR FLASH0. 380- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address 381 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. 382- The default use-case for the Foundation FVP is to use the ``--gicv3`` option 383 and enable the GICv3 device in the model. Note that without this option, 384 the Foundation FVP defaults to legacy (Versatile Express) memory map which 385 is not supported by TF-A. 386- In order for TF-A to run correctly on the Foundation FVP, the architecture 387 versions must match. The Foundation FVP defaults to the highest v8.x 388 version it supports but the default build for TF-A is for v8.0. To avoid 389 issues either start the Foundation FVP to use v8.0 architecture using the 390 ``--arm-v8.0`` option, or build TF-A with an appropriate value for 391 ``ARM_ARCH_MINOR``. 392 393Running on the AEMv8 Base FVP with reset to BL1 entrypoint 394^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 395 396The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 397with 8 CPUs using the AArch64 build of TF-A. 398 399.. code:: shell 400 401 <path-to>/FVP_Base_RevC-2xAEMv8A \ 402 -C pctl.startup=0.0.0.0 \ 403 -C bp.secure_memory=1 \ 404 -C bp.tzc_400.diagnostics=1 \ 405 -C cluster0.NUM_CORES=4 \ 406 -C cluster1.NUM_CORES=4 \ 407 -C cache_state_modelled=1 \ 408 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 409 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 410 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 411 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 412 413.. note:: 414 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires 415 a specific DTS for all the CPUs to be loaded. 416 417Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint 418^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 419 420The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 421with 8 CPUs using the AArch32 build of TF-A. 422 423.. code:: shell 424 425 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 426 -C pctl.startup=0.0.0.0 \ 427 -C bp.secure_memory=1 \ 428 -C bp.tzc_400.diagnostics=1 \ 429 -C cluster0.NUM_CORES=4 \ 430 -C cluster1.NUM_CORES=4 \ 431 -C cache_state_modelled=1 \ 432 -C cluster0.cpu0.CONFIG64=0 \ 433 -C cluster0.cpu1.CONFIG64=0 \ 434 -C cluster0.cpu2.CONFIG64=0 \ 435 -C cluster0.cpu3.CONFIG64=0 \ 436 -C cluster1.cpu0.CONFIG64=0 \ 437 -C cluster1.cpu1.CONFIG64=0 \ 438 -C cluster1.cpu2.CONFIG64=0 \ 439 -C cluster1.cpu3.CONFIG64=0 \ 440 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 441 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 442 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 443 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 444 445Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint 446^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 447 448The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 449boot Linux with 8 CPUs using the AArch64 build of TF-A. 450 451.. code:: shell 452 453 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 454 -C pctl.startup=0.0.0.0 \ 455 -C bp.secure_memory=1 \ 456 -C bp.tzc_400.diagnostics=1 \ 457 -C cache_state_modelled=1 \ 458 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 459 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 460 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 461 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 462 463Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint 464^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 465 466The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 467boot Linux with 4 CPUs using the AArch32 build of TF-A. 468 469.. code:: shell 470 471 <path-to>/FVP_Base_Cortex-A32x4 \ 472 -C pctl.startup=0.0.0.0 \ 473 -C bp.secure_memory=1 \ 474 -C bp.tzc_400.diagnostics=1 \ 475 -C cache_state_modelled=1 \ 476 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 477 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 478 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 479 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 480 481 482Running on the AEMv8 Base FVP with reset to BL31 entrypoint 483^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 484 485The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 486with 8 CPUs using the AArch64 build of TF-A. 487 488.. code:: shell 489 490 <path-to>/FVP_Base_RevC-2xAEMv8A \ 491 -C pctl.startup=0.0.0.0 \ 492 -C bp.secure_memory=1 \ 493 -C bp.tzc_400.diagnostics=1 \ 494 -C cluster0.NUM_CORES=4 \ 495 -C cluster1.NUM_CORES=4 \ 496 -C cache_state_modelled=1 \ 497 -C cluster0.cpu0.RVBAR=0x04010000 \ 498 -C cluster0.cpu1.RVBAR=0x04010000 \ 499 -C cluster0.cpu2.RVBAR=0x04010000 \ 500 -C cluster0.cpu3.RVBAR=0x04010000 \ 501 -C cluster1.cpu0.RVBAR=0x04010000 \ 502 -C cluster1.cpu1.RVBAR=0x04010000 \ 503 -C cluster1.cpu2.RVBAR=0x04010000 \ 504 -C cluster1.cpu3.RVBAR=0x04010000 \ 505 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 506 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 507 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 508 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 509 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 510 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 511 512Notes: 513 514- If Position Independent Executable (PIE) support is enabled for BL31 515 in this config, it can be loaded at any valid address for execution. 516 517- Since a FIP is not loaded when using BL31 as reset entrypoint, the 518 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` 519 parameter is needed to load the individual bootloader images in memory. 520 BL32 image is only needed if BL31 has been built to expect a Secure-EL1 521 Payload. For the same reason, the FDT needs to be compiled from the DT source 522 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` 523 parameter. 524 525- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a 526 specific DTS for all the CPUs to be loaded. 527 528- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where 529 X and Y are the cluster and CPU numbers respectively, is used to set the 530 reset vector for each core. 531 532- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require 533 changing the value of 534 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of 535 ``BL32_BASE``. 536 537 538Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint 539^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 540 541The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 542with 8 CPUs using the AArch32 build of TF-A. 543 544.. code:: shell 545 546 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 547 -C pctl.startup=0.0.0.0 \ 548 -C bp.secure_memory=1 \ 549 -C bp.tzc_400.diagnostics=1 \ 550 -C cluster0.NUM_CORES=4 \ 551 -C cluster1.NUM_CORES=4 \ 552 -C cache_state_modelled=1 \ 553 -C cluster0.cpu0.CONFIG64=0 \ 554 -C cluster0.cpu1.CONFIG64=0 \ 555 -C cluster0.cpu2.CONFIG64=0 \ 556 -C cluster0.cpu3.CONFIG64=0 \ 557 -C cluster1.cpu0.CONFIG64=0 \ 558 -C cluster1.cpu1.CONFIG64=0 \ 559 -C cluster1.cpu2.CONFIG64=0 \ 560 -C cluster1.cpu3.CONFIG64=0 \ 561 -C cluster0.cpu0.RVBAR=0x04002000 \ 562 -C cluster0.cpu1.RVBAR=0x04002000 \ 563 -C cluster0.cpu2.RVBAR=0x04002000 \ 564 -C cluster0.cpu3.RVBAR=0x04002000 \ 565 -C cluster1.cpu0.RVBAR=0x04002000 \ 566 -C cluster1.cpu1.RVBAR=0x04002000 \ 567 -C cluster1.cpu2.RVBAR=0x04002000 \ 568 -C cluster1.cpu3.RVBAR=0x04002000 \ 569 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 570 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 571 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 572 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 573 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 574 575.. note:: 576 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``. 577 It should match the address programmed into the RVBAR register as well. 578 579Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint 580^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 581 582The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 583boot Linux with 8 CPUs using the AArch64 build of TF-A. 584 585.. code:: shell 586 587 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 588 -C pctl.startup=0.0.0.0 \ 589 -C bp.secure_memory=1 \ 590 -C bp.tzc_400.diagnostics=1 \ 591 -C cache_state_modelled=1 \ 592 -C cluster0.cpu0.RVBARADDR=0x04010000 \ 593 -C cluster0.cpu1.RVBARADDR=0x04010000 \ 594 -C cluster0.cpu2.RVBARADDR=0x04010000 \ 595 -C cluster0.cpu3.RVBARADDR=0x04010000 \ 596 -C cluster1.cpu0.RVBARADDR=0x04010000 \ 597 -C cluster1.cpu1.RVBARADDR=0x04010000 \ 598 -C cluster1.cpu2.RVBARADDR=0x04010000 \ 599 -C cluster1.cpu3.RVBARADDR=0x04010000 \ 600 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 601 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 602 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 603 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 604 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 605 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 606 607Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint 608^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 609 610The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 611boot Linux with 4 CPUs using the AArch32 build of TF-A. 612 613.. code:: shell 614 615 <path-to>/FVP_Base_Cortex-A32x4 \ 616 -C pctl.startup=0.0.0.0 \ 617 -C bp.secure_memory=1 \ 618 -C bp.tzc_400.diagnostics=1 \ 619 -C cache_state_modelled=1 \ 620 -C cluster0.cpu0.RVBARADDR=0x04002000 \ 621 -C cluster0.cpu1.RVBARADDR=0x04002000 \ 622 -C cluster0.cpu2.RVBARADDR=0x04002000 \ 623 -C cluster0.cpu3.RVBARADDR=0x04002000 \ 624 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 625 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 626 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 627 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 628 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 629 630-------------- 631 632*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* 633 634.. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts 635.. _Arm's website: `FVP models`_ 636.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms 637.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 638.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms 639