1Arm Fixed Virtual Platforms (FVP) 2================================= 3 4Fixed Virtual Platform (FVP) Support 5------------------------------------ 6 7This section lists the supported Arm |FVP| platforms. Please refer to the FVP 8documentation for a detailed description of the model parameter options. 9 10The latest version of the AArch64 build of TF-A has been tested on the following 11Arm FVPs without shifted affinities, and that do not support threaded CPU cores 12(64-bit host machine only). 13 14.. note:: 15 The FVP models used are Version 11.12 Build 38, unless otherwise stated. 16 17- ``FVP_Base_AEMvA`` 18- ``FVP_Base_AEMv8A-AEMv8A`` 19- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` 20- ``FVP_Base_RevC-2xAEMv8A`` 21- ``FVP_Base_Cortex-A32x4`` 22- ``FVP_Base_Cortex-A35x4`` 23- ``FVP_Base_Cortex-A53x4`` 24- ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` 25- ``FVP_Base_Cortex-A55x4`` 26- ``FVP_Base_Cortex-A57x1-A53x1`` 27- ``FVP_Base_Cortex-A57x2-A53x4`` 28- ``FVP_Base_Cortex-A57x4-A53x4`` 29- ``FVP_Base_Cortex-A57x4`` 30- ``FVP_Base_Cortex-A65x4`` 31- ``FVP_Base_Cortex-A65AEx8`` 32- ``FVP_Base_Cortex-A72x4-A53x4`` 33- ``FVP_Base_Cortex-A72x4`` 34- ``FVP_Base_Cortex-A73x4-A53x4`` 35- ``FVP_Base_Cortex-A73x4`` 36- ``FVP_Base_Cortex-A75x4`` 37- ``FVP_Base_Cortex-A76x4`` 38- ``FVP_Base_Cortex-A76AEx4`` 39- ``FVP_Base_Cortex-A76AEx8`` 40- ``FVP_Base_Cortex-A77x4`` 41- ``FVP_Base_Cortex-A78x4`` 42- ``FVP_Base_Neoverse-E1x1`` 43- ``FVP_Base_Neoverse-E1x2`` 44- ``FVP_Base_Neoverse-E1x4`` 45- ``FVP_Base_Neoverse-N1x4`` 46- ``FVP_Base_Neoverse-V1x4`` 47- ``FVP_CSS_SGI-575`` (Version 11.10 build 36) 48- ``FVP_CSS_SGM-775`` 49- ``FVP_RD_E1_edge`` (Version 11.9 build 41) 50- ``FVP_RD_N1_edge`` (Version 11.10 build 36) 51- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36) 52- ``FVP_RD_Daniel`` (Version 11.13 build 10) 53- ``FVP_RD_N2`` (Version 11.13 build 10) 54- ``FVP_TC0`` (Version 0.0 build 6114) 55- ``Foundation_Platform`` 56 57The latest version of the AArch32 build of TF-A has been tested on the 58following Arm FVPs without shifted affinities, and that do not support threaded 59CPU cores (64-bit host machine only). 60 61- ``FVP_Base_AEMvA`` 62- ``FVP_Base_AEMv8A-AEMv8A`` 63- ``FVP_Base_Cortex-A32x4`` 64 65.. note:: 66 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which 67 is not compatible with legacy GIC configurations. Therefore this FVP does not 68 support these legacy GIC configurations. 69 70The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm 71FVP website`_. The Cortex-A models listed above are also available to download 72from `Arm's website`_. 73 74.. note:: 75 The build numbers quoted above are those reported by launching the FVP 76 with the ``--version`` parameter. 77 78.. note:: 79 Linaro provides a ramdisk image in prebuilt FVP configurations and full 80 file systems that can be downloaded separately. To run an FVP with a virtio 81 file system image an additional FVP configuration option 82 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be 83 used. 84 85.. note:: 86 The software will not work on Version 1.0 of the Foundation FVP. 87 The commands below would report an ``unhandled argument`` error in this case. 88 89.. note:: 90 FVPs can be launched with ``--cadi-server`` option such that a 91 CADI-compliant debugger (for example, Arm DS-5) can connect to and control 92 its execution. 93 94.. warning:: 95 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 96 the internal synchronisation timings changed compared to older versions of 97 the models. The models can be launched with ``-Q 100`` option if they are 98 required to match the run time characteristics of the older versions. 99 100All the above platforms have been tested with `Linaro Release 19.06`_. 101 102.. _build_options_arm_fvp_platform: 103 104Arm FVP Platform Specific Build Options 105--------------------------------------- 106 107- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 108 build the topology tree within TF-A. By default TF-A is configured for dual 109 cluster topology and this option can be used to override the default value. 110 111- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 112 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 113 explained in the options below: 114 115 - ``FVP_CCI`` : The CCI driver is selected. This is the default 116 if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 117 - ``FVP_CCN`` : The CCN driver is selected. This is the default 118 if ``FVP_CLUSTER_COUNT`` > 2. 119 120- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 121 a single cluster. This option defaults to 4. 122 123- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 124 in the system. This option defaults to 1. Note that the build option 125 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 126 127- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 128 129 - ``FVP_GICV2`` : The GICv2 only driver is selected 130 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 131 132- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 133 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 134 details on HW_CONFIG. By default, this is initialized to a sensible DTS 135 file in ``fdts/`` folder depending on other build options. But some cases, 136 like shifted affinity format for MPIDR, cannot be detected at build time 137 and this option is needed to specify the appropriate DTS file. 138 139- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 140 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 141 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 142 HW_CONFIG blob instead of the DTS file. This option is useful to override 143 the default HW_CONFIG selected by the build system. 144 145Booting Firmware Update images 146------------------------------ 147 148When Firmware Update (FWU) is enabled there are at least 2 new images 149that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the 150FWU FIP. 151 152The additional fip images must be loaded with: 153 154:: 155 156 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] 157 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] 158 159The address ns_bl1u_base_address is the value of NS_BL1U_BASE. 160In the same way, the address ns_bl2u_base_address is the value of 161NS_BL2U_BASE. 162 163Booting an EL3 payload 164---------------------- 165 166The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for 167the secondary CPUs holding pen to work properly. Unfortunately, its reset value 168is undefined on the FVP platform and the FVP platform code doesn't clear it. 169Therefore, one must modify the way the model is normally invoked in order to 170clear the mailbox at start-up. 171 172One way to do that is to create an 8-byte file containing all zero bytes using 173the following command: 174 175.. code:: shell 176 177 dd if=/dev/zero of=mailbox.dat bs=1 count=8 178 179and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) 180using the following model parameters: 181 182:: 183 184 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] 185 --data=mailbox.dat@0x04000000 [Foundation FVP] 186 187To provide the model with the EL3 payload image, the following methods may be 188used: 189 190#. If the EL3 payload is able to execute in place, it may be programmed into 191 flash memory. On Base Cortex and AEM FVPs, the following model parameter 192 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already 193 used for the FIP): 194 195 :: 196 197 -C bp.flashloader1.fname="<path-to>/<el3-payload>" 198 199 On Foundation FVP, there is no flash loader component and the EL3 payload 200 may be programmed anywhere in flash using method 3 below. 201 202#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 203 command may be used to load the EL3 payload ELF image over JTAG: 204 205 :: 206 207 load <path-to>/el3-payload.elf 208 209#. The EL3 payload may be pre-loaded in volatile memory using the following 210 model parameters: 211 212 :: 213 214 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] 215 --data="<path-to>/<el3-payload>"@address [Foundation FVP] 216 217 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address 218 used when building TF-A. 219 220Booting a preloaded kernel image (Base FVP) 221------------------------------------------- 222 223The following example uses a simplified boot flow by directly jumping from the 224TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be 225useful if both the kernel and the device tree blob (DTB) are already present in 226memory (like in FVP). 227 228For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at 229address ``0x82000000``, the firmware can be built like this: 230 231.. code:: shell 232 233 CROSS_COMPILE=aarch64-none-elf- \ 234 make PLAT=fvp DEBUG=1 \ 235 RESET_TO_BL31=1 \ 236 ARM_LINUX_KERNEL_AS_BL33=1 \ 237 PRELOADED_BL33_BASE=0x80080000 \ 238 ARM_PRELOADED_DTB_BASE=0x82000000 \ 239 all fip 240 241Now, it is needed to modify the DTB so that the kernel knows the address of the 242ramdisk. The following script generates a patched DTB from the provided one, 243assuming that the ramdisk is loaded at address ``0x84000000``. Note that this 244script assumes that the user is using a ramdisk image prepared for U-Boot, like 245the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` 246offset in ``INITRD_START`` has to be removed. 247 248.. code:: bash 249 250 #!/bin/bash 251 252 # Path to the input DTB 253 KERNEL_DTB=<path-to>/<fdt> 254 # Path to the output DTB 255 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> 256 # Base address of the ramdisk 257 INITRD_BASE=0x84000000 258 # Path to the ramdisk 259 INITRD=<path-to>/<ramdisk.img> 260 261 # Skip uboot header (64 bytes) 262 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) 263 INITRD_SIZE=$(stat -Lc %s ${INITRD}) 264 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) 265 266 CHOSEN_NODE=$(echo \ 267 "/ { \ 268 chosen { \ 269 linux,initrd-start = <${INITRD_START}>; \ 270 linux,initrd-end = <${INITRD_END}>; \ 271 }; \ 272 };") 273 274 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ 275 dtc -O dtb -o ${PATCHED_KERNEL_DTB} - 276 277And the FVP binary can be run with the following command: 278 279.. code:: shell 280 281 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 282 -C pctl.startup=0.0.0.0 \ 283 -C bp.secure_memory=1 \ 284 -C cluster0.NUM_CORES=4 \ 285 -C cluster1.NUM_CORES=4 \ 286 -C cache_state_modelled=1 \ 287 -C cluster0.cpu0.RVBAR=0x04001000 \ 288 -C cluster0.cpu1.RVBAR=0x04001000 \ 289 -C cluster0.cpu2.RVBAR=0x04001000 \ 290 -C cluster0.cpu3.RVBAR=0x04001000 \ 291 -C cluster1.cpu0.RVBAR=0x04001000 \ 292 -C cluster1.cpu1.RVBAR=0x04001000 \ 293 -C cluster1.cpu2.RVBAR=0x04001000 \ 294 -C cluster1.cpu3.RVBAR=0x04001000 \ 295 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ 296 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ 297 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 298 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 299 300Obtaining the Flattened Device Trees 301^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 302 303Depending on the FVP configuration and Linux configuration used, different 304FDT files are required. FDT source files for the Foundation and Base FVPs can 305be found in the TF-A source directory under ``fdts/``. The Foundation FVP has 306a subset of the Base FVP components. For example, the Foundation FVP lacks 307CLCD and MMC support, and has only one CPU cluster. 308 309.. note:: 310 It is not recommended to use the FDTs built along the kernel because not 311 all FDTs are available from there. 312 313The dynamic configuration capability is enabled in the firmware for FVPs. 314This means that the firmware can authenticate and load the FDT if present in 315FIP. A default FDT is packaged into FIP during the build based on 316the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` 317or ``FVP_HW_CONFIG_DTS`` build options (refer to 318:ref:`build_options_arm_fvp_platform` for details on the options). 319 320- ``fvp-base-gicv2-psci.dts`` 321 322 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 323 affinities and with Base memory map configuration. 324 325- ``fvp-base-gicv2-psci-aarch32.dts`` 326 327 For use with models such as the Cortex-A32 Base FVPs without shifted 328 affinities and running Linux in AArch32 state with Base memory map 329 configuration. 330 331- ``fvp-base-gicv3-psci.dts`` 332 333 For use with models such as the Cortex-A57-A53 Base FVPs without shifted 334 affinities and with Base memory map configuration and Linux GICv3 support. 335 336- ``fvp-base-gicv3-psci-1t.dts`` 337 338 For use with models such as the AEMv8-RevC Base FVP with shifted affinities, 339 single threaded CPUs, Base memory map configuration and Linux GICv3 support. 340 341- ``fvp-base-gicv3-psci-dynamiq.dts`` 342 343 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, 344 single cluster, single threaded CPUs, Base memory map configuration and Linux 345 GICv3 support. 346 347- ``fvp-base-gicv3-psci-aarch32.dts`` 348 349 For use with models such as the Cortex-A32 Base FVPs without shifted 350 affinities and running Linux in AArch32 state with Base memory map 351 configuration and Linux GICv3 support. 352 353- ``fvp-foundation-gicv2-psci.dts`` 354 355 For use with Foundation FVP with Base memory map configuration. 356 357- ``fvp-foundation-gicv3-psci.dts`` 358 359 (Default) For use with Foundation FVP with Base memory map configuration 360 and Linux GICv3 support. 361 362 363Running on the Foundation FVP with reset to BL1 entrypoint 364^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 365 366The following ``Foundation_Platform`` parameters should be used to boot Linux with 3674 CPUs using the AArch64 build of TF-A. 368 369.. code:: shell 370 371 <path-to>/Foundation_Platform \ 372 --cores=4 \ 373 --arm-v8.0 \ 374 --secure-memory \ 375 --visualization \ 376 --gicv3 \ 377 --data="<path-to>/<bl1-binary>"@0x0 \ 378 --data="<path-to>/<FIP-binary>"@0x08000000 \ 379 --data="<path-to>/<kernel-binary>"@0x80080000 \ 380 --data="<path-to>/<ramdisk-binary>"@0x84000000 381 382Notes: 383 384- BL1 is loaded at the start of the Trusted ROM. 385- The Firmware Image Package is loaded at the start of NOR FLASH0. 386- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address 387 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. 388- The default use-case for the Foundation FVP is to use the ``--gicv3`` option 389 and enable the GICv3 device in the model. Note that without this option, 390 the Foundation FVP defaults to legacy (Versatile Express) memory map which 391 is not supported by TF-A. 392- In order for TF-A to run correctly on the Foundation FVP, the architecture 393 versions must match. The Foundation FVP defaults to the highest v8.x 394 version it supports but the default build for TF-A is for v8.0. To avoid 395 issues either start the Foundation FVP to use v8.0 architecture using the 396 ``--arm-v8.0`` option, or build TF-A with an appropriate value for 397 ``ARM_ARCH_MINOR``. 398 399Running on the AEMv8 Base FVP with reset to BL1 entrypoint 400^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 401 402The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 403with 8 CPUs using the AArch64 build of TF-A. 404 405.. code:: shell 406 407 <path-to>/FVP_Base_RevC-2xAEMv8A \ 408 -C pctl.startup=0.0.0.0 \ 409 -C bp.secure_memory=1 \ 410 -C bp.tzc_400.diagnostics=1 \ 411 -C cluster0.NUM_CORES=4 \ 412 -C cluster1.NUM_CORES=4 \ 413 -C cache_state_modelled=1 \ 414 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 415 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 416 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 417 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 418 419.. note:: 420 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires 421 a specific DTS for all the CPUs to be loaded. 422 423Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint 424^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 425 426The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 427with 8 CPUs using the AArch32 build of TF-A. 428 429.. code:: shell 430 431 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 432 -C pctl.startup=0.0.0.0 \ 433 -C bp.secure_memory=1 \ 434 -C bp.tzc_400.diagnostics=1 \ 435 -C cluster0.NUM_CORES=4 \ 436 -C cluster1.NUM_CORES=4 \ 437 -C cache_state_modelled=1 \ 438 -C cluster0.cpu0.CONFIG64=0 \ 439 -C cluster0.cpu1.CONFIG64=0 \ 440 -C cluster0.cpu2.CONFIG64=0 \ 441 -C cluster0.cpu3.CONFIG64=0 \ 442 -C cluster1.cpu0.CONFIG64=0 \ 443 -C cluster1.cpu1.CONFIG64=0 \ 444 -C cluster1.cpu2.CONFIG64=0 \ 445 -C cluster1.cpu3.CONFIG64=0 \ 446 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 447 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 448 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 449 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 450 451Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint 452^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 453 454The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 455boot Linux with 8 CPUs using the AArch64 build of TF-A. 456 457.. code:: shell 458 459 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 460 -C pctl.startup=0.0.0.0 \ 461 -C bp.secure_memory=1 \ 462 -C bp.tzc_400.diagnostics=1 \ 463 -C cache_state_modelled=1 \ 464 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 465 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 466 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 467 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 468 469Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint 470^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 471 472The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 473boot Linux with 4 CPUs using the AArch32 build of TF-A. 474 475.. code:: shell 476 477 <path-to>/FVP_Base_Cortex-A32x4 \ 478 -C pctl.startup=0.0.0.0 \ 479 -C bp.secure_memory=1 \ 480 -C bp.tzc_400.diagnostics=1 \ 481 -C cache_state_modelled=1 \ 482 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 483 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 484 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 485 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 486 487 488Running on the AEMv8 Base FVP with reset to BL31 entrypoint 489^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 490 491The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 492with 8 CPUs using the AArch64 build of TF-A. 493 494.. code:: shell 495 496 <path-to>/FVP_Base_RevC-2xAEMv8A \ 497 -C pctl.startup=0.0.0.0 \ 498 -C bp.secure_memory=1 \ 499 -C bp.tzc_400.diagnostics=1 \ 500 -C cluster0.NUM_CORES=4 \ 501 -C cluster1.NUM_CORES=4 \ 502 -C cache_state_modelled=1 \ 503 -C cluster0.cpu0.RVBAR=0x04010000 \ 504 -C cluster0.cpu1.RVBAR=0x04010000 \ 505 -C cluster0.cpu2.RVBAR=0x04010000 \ 506 -C cluster0.cpu3.RVBAR=0x04010000 \ 507 -C cluster1.cpu0.RVBAR=0x04010000 \ 508 -C cluster1.cpu1.RVBAR=0x04010000 \ 509 -C cluster1.cpu2.RVBAR=0x04010000 \ 510 -C cluster1.cpu3.RVBAR=0x04010000 \ 511 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 512 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 513 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 514 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 515 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 516 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 517 518Notes: 519 520- If Position Independent Executable (PIE) support is enabled for BL31 521 in this config, it can be loaded at any valid address for execution. 522 523- Since a FIP is not loaded when using BL31 as reset entrypoint, the 524 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` 525 parameter is needed to load the individual bootloader images in memory. 526 BL32 image is only needed if BL31 has been built to expect a Secure-EL1 527 Payload. For the same reason, the FDT needs to be compiled from the DT source 528 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` 529 parameter. 530 531- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a 532 specific DTS for all the CPUs to be loaded. 533 534- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where 535 X and Y are the cluster and CPU numbers respectively, is used to set the 536 reset vector for each core. 537 538- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require 539 changing the value of 540 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of 541 ``BL32_BASE``. 542 543 544Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint 545^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 546 547The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 548with 8 CPUs using the AArch32 build of TF-A. 549 550.. code:: shell 551 552 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 553 -C pctl.startup=0.0.0.0 \ 554 -C bp.secure_memory=1 \ 555 -C bp.tzc_400.diagnostics=1 \ 556 -C cluster0.NUM_CORES=4 \ 557 -C cluster1.NUM_CORES=4 \ 558 -C cache_state_modelled=1 \ 559 -C cluster0.cpu0.CONFIG64=0 \ 560 -C cluster0.cpu1.CONFIG64=0 \ 561 -C cluster0.cpu2.CONFIG64=0 \ 562 -C cluster0.cpu3.CONFIG64=0 \ 563 -C cluster1.cpu0.CONFIG64=0 \ 564 -C cluster1.cpu1.CONFIG64=0 \ 565 -C cluster1.cpu2.CONFIG64=0 \ 566 -C cluster1.cpu3.CONFIG64=0 \ 567 -C cluster0.cpu0.RVBAR=0x04002000 \ 568 -C cluster0.cpu1.RVBAR=0x04002000 \ 569 -C cluster0.cpu2.RVBAR=0x04002000 \ 570 -C cluster0.cpu3.RVBAR=0x04002000 \ 571 -C cluster1.cpu0.RVBAR=0x04002000 \ 572 -C cluster1.cpu1.RVBAR=0x04002000 \ 573 -C cluster1.cpu2.RVBAR=0x04002000 \ 574 -C cluster1.cpu3.RVBAR=0x04002000 \ 575 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 576 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 577 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 578 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 579 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 580 581.. note:: 582 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``. 583 It should match the address programmed into the RVBAR register as well. 584 585Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint 586^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 587 588The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 589boot Linux with 8 CPUs using the AArch64 build of TF-A. 590 591.. code:: shell 592 593 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 594 -C pctl.startup=0.0.0.0 \ 595 -C bp.secure_memory=1 \ 596 -C bp.tzc_400.diagnostics=1 \ 597 -C cache_state_modelled=1 \ 598 -C cluster0.cpu0.RVBARADDR=0x04010000 \ 599 -C cluster0.cpu1.RVBARADDR=0x04010000 \ 600 -C cluster0.cpu2.RVBARADDR=0x04010000 \ 601 -C cluster0.cpu3.RVBARADDR=0x04010000 \ 602 -C cluster1.cpu0.RVBARADDR=0x04010000 \ 603 -C cluster1.cpu1.RVBARADDR=0x04010000 \ 604 -C cluster1.cpu2.RVBARADDR=0x04010000 \ 605 -C cluster1.cpu3.RVBARADDR=0x04010000 \ 606 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 607 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 608 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 609 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 610 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 611 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 612 613Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint 614^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 615 616The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 617boot Linux with 4 CPUs using the AArch32 build of TF-A. 618 619.. code:: shell 620 621 <path-to>/FVP_Base_Cortex-A32x4 \ 622 -C pctl.startup=0.0.0.0 \ 623 -C bp.secure_memory=1 \ 624 -C bp.tzc_400.diagnostics=1 \ 625 -C cache_state_modelled=1 \ 626 -C cluster0.cpu0.RVBARADDR=0x04002000 \ 627 -C cluster0.cpu1.RVBARADDR=0x04002000 \ 628 -C cluster0.cpu2.RVBARADDR=0x04002000 \ 629 -C cluster0.cpu3.RVBARADDR=0x04002000 \ 630 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 631 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 632 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 633 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 634 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 635 636-------------- 637 638*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* 639 640.. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts 641.. _Arm's website: `FVP models`_ 642.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms 643.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 644.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms 645