xref: /rk3399_ARM-atf/docs/plat/arm/fvp/fvp-support.rst (revision c54076934987b50258c719fd414db10d8c64f8b2)
1*c5407693SSandrine BailleuxFixed Virtual Platform (FVP) Support
2*c5407693SSandrine Bailleux------------------------------------
3*c5407693SSandrine Bailleux
4*c5407693SSandrine BailleuxThis section lists the supported Arm |FVP| platforms. Please refer to the FVP
5*c5407693SSandrine Bailleuxdocumentation for a detailed description of the model parameter options.
6*c5407693SSandrine Bailleux
7*c5407693SSandrine BailleuxThe latest version of the AArch64 build of TF-A has been tested on the following
8*c5407693SSandrine BailleuxArm FVPs without shifted affinities, and that do not support threaded CPU cores
9*c5407693SSandrine Bailleux(64-bit host machine only).
10*c5407693SSandrine Bailleux
11*c5407693SSandrine Bailleux.. note::
12*c5407693SSandrine Bailleux   The FVP models used are Version 11.22 Build 14, unless otherwise stated.
13*c5407693SSandrine Bailleux
14*c5407693SSandrine Bailleux-  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21)
15*c5407693SSandrine Bailleux-  ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21)
16*c5407693SSandrine Bailleux-  ``FVP_Base_AEMvA``
17*c5407693SSandrine Bailleux-  ``FVP_Base_AEMvA-AEMvA``
18*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A32x4`` (Version 11.12/38)
19*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A35x4``
20*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A53x4``
21*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A55``
22*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
23*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A55x4+Cortex-A76x2``
24*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A57x1-A53x1``
25*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A57x2-A53x4``
26*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A57x4``
27*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A57x4-A53x4``
28*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A65``
29*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A65AE``
30*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A710x4`` (Version 11.17/21)
31*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A72x4``
32*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A72x4-A53x4``
33*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A73x4``
34*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A73x4-A53x4``
35*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A75``
36*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A76``
37*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A76AE``
38*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A77``
39*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A78``
40*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A78AE``
41*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A78C``
42*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-X2x4`` (Version 11.17/21)
43*c5407693SSandrine Bailleux-  ``FVP_Base_Neoverse-E1``
44*c5407693SSandrine Bailleux-  ``FVP_Base_Neoverse-N1``
45*c5407693SSandrine Bailleux-  ``FVP_Base_Neoverse-V1``
46*c5407693SSandrine Bailleux-  ``FVP_Base_RevC-2xAEMv8A``
47*c5407693SSandrine Bailleux-  ``FVP_BaseR_AEMv8R``
48*c5407693SSandrine Bailleux-  ``FVP_Morello`` (Version 0.11/33)
49*c5407693SSandrine Bailleux-  ``FVP_RD_V1``
50*c5407693SSandrine Bailleux-  ``FVP_TC1``
51*c5407693SSandrine Bailleux-  ``FVP_TC2`` (Version 11.23/17)
52*c5407693SSandrine Bailleux
53*c5407693SSandrine BailleuxThe latest version of the AArch32 build of TF-A has been tested on the
54*c5407693SSandrine Bailleuxfollowing Arm FVPs without shifted affinities, and that do not support threaded
55*c5407693SSandrine BailleuxCPU cores (64-bit host machine only).
56*c5407693SSandrine Bailleux
57*c5407693SSandrine Bailleux-  ``FVP_Base_AEMvA``
58*c5407693SSandrine Bailleux-  ``FVP_Base_AEMvA-AEMvA``
59*c5407693SSandrine Bailleux-  ``FVP_Base_Cortex-A32x4``
60*c5407693SSandrine Bailleux
61*c5407693SSandrine Bailleux.. note::
62*c5407693SSandrine Bailleux   The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
63*c5407693SSandrine Bailleux   is not compatible with legacy GIC configurations. Therefore this FVP does not
64*c5407693SSandrine Bailleux   support these legacy GIC configurations.
65*c5407693SSandrine Bailleux
66*c5407693SSandrine BailleuxThe *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
67*c5407693SSandrine BailleuxFVP website`_. The Cortex-A models listed above are also available to download
68*c5407693SSandrine Bailleuxfrom `Arm's website`_.
69*c5407693SSandrine Bailleux
70*c5407693SSandrine Bailleux.. note::
71*c5407693SSandrine Bailleux   The build numbers quoted above are those reported by launching the FVP
72*c5407693SSandrine Bailleux   with the ``--version`` parameter.
73*c5407693SSandrine Bailleux
74*c5407693SSandrine Bailleux.. note::
75*c5407693SSandrine Bailleux   Linaro provides a ramdisk image in prebuilt FVP configurations and full
76*c5407693SSandrine Bailleux   file systems that can be downloaded separately. To run an FVP with a virtio
77*c5407693SSandrine Bailleux   file system image an additional FVP configuration option
78*c5407693SSandrine Bailleux   ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
79*c5407693SSandrine Bailleux   used.
80*c5407693SSandrine Bailleux
81*c5407693SSandrine Bailleux.. note::
82*c5407693SSandrine Bailleux   The software will not work on Version 1.0 of the Foundation FVP.
83*c5407693SSandrine Bailleux   The commands below would report an ``unhandled argument`` error in this case.
84*c5407693SSandrine Bailleux
85*c5407693SSandrine Bailleux.. note::
86*c5407693SSandrine Bailleux   FVPs can be launched with ``--cadi-server`` option such that a
87*c5407693SSandrine Bailleux   CADI-compliant debugger (for example, Arm DS-5) can connect to and control
88*c5407693SSandrine Bailleux   its execution.
89*c5407693SSandrine Bailleux
90*c5407693SSandrine Bailleux.. warning::
91*c5407693SSandrine Bailleux   Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
92*c5407693SSandrine Bailleux   the internal synchronisation timings changed compared to older versions of
93*c5407693SSandrine Bailleux   the models. The models can be launched with ``-Q 100`` option if they are
94*c5407693SSandrine Bailleux   required to match the run time characteristics of the older versions.
95*c5407693SSandrine Bailleux
96*c5407693SSandrine BailleuxAll the above platforms have been tested with `Linaro Release 20.01`_.
97*c5407693SSandrine Bailleux
98*c5407693SSandrine Bailleux--------------
99*c5407693SSandrine Bailleux
100*c5407693SSandrine Bailleux*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
101*c5407693SSandrine Bailleux
102*c5407693SSandrine Bailleux.. _Arm's website: `FVP models`_
103*c5407693SSandrine Bailleux.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
104*c5407693SSandrine Bailleux.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
105*c5407693SSandrine Bailleux.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
106