xref: /rk3399_ARM-atf/docs/plat/arm/fvp/fvp-specific-configs.rst (revision 1a219805187d0fe1194e4d0214313cbbe3783f2e)
1c5407693SSandrine BailleuxBooting Firmware Update images
2c5407693SSandrine Bailleux------------------------------
3c5407693SSandrine Bailleux
4c5407693SSandrine BailleuxWhen Firmware Update (FWU) is enabled there are at least 2 new images
5c5407693SSandrine Bailleuxthat have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
6c5407693SSandrine BailleuxFWU FIP.
7c5407693SSandrine Bailleux
8c5407693SSandrine BailleuxThe additional fip images must be loaded with:
9c5407693SSandrine Bailleux
10c5407693SSandrine Bailleux::
11c5407693SSandrine Bailleux
12c5407693SSandrine Bailleux    --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000	[ns_bl1u_base_address]
13c5407693SSandrine Bailleux    --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000	[ns_bl2u_base_address]
14c5407693SSandrine Bailleux
15c5407693SSandrine BailleuxThe address ns_bl1u_base_address is the value of NS_BL1U_BASE.
16c5407693SSandrine BailleuxIn the same way, the address ns_bl2u_base_address is the value of
17c5407693SSandrine BailleuxNS_BL2U_BASE.
18c5407693SSandrine Bailleux
19c5407693SSandrine BailleuxBooting an EL3 payload
20c5407693SSandrine Bailleux----------------------
21c5407693SSandrine Bailleux
22c5407693SSandrine BailleuxThe EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
23c5407693SSandrine Bailleuxthe secondary CPUs holding pen to work properly. Unfortunately, its reset value
24c5407693SSandrine Bailleuxis undefined on the FVP platform and the FVP platform code doesn't clear it.
25c5407693SSandrine BailleuxTherefore, one must modify the way the model is normally invoked in order to
26c5407693SSandrine Bailleuxclear the mailbox at start-up.
27c5407693SSandrine Bailleux
28c5407693SSandrine BailleuxOne way to do that is to create an 8-byte file containing all zero bytes using
29c5407693SSandrine Bailleuxthe following command:
30c5407693SSandrine Bailleux
31c5407693SSandrine Bailleux.. code:: shell
32c5407693SSandrine Bailleux
33c5407693SSandrine Bailleux    dd if=/dev/zero of=mailbox.dat bs=1 count=8
34c5407693SSandrine Bailleux
35c5407693SSandrine Bailleuxand pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
36c5407693SSandrine Bailleuxusing the following model parameters:
37c5407693SSandrine Bailleux
38c5407693SSandrine Bailleux::
39c5407693SSandrine Bailleux
40c5407693SSandrine Bailleux    --data cluster0.cpu0=mailbox.dat@0x04000000   [Base FVPs]
41c5407693SSandrine Bailleux    --data=mailbox.dat@0x04000000                 [Foundation FVP]
42c5407693SSandrine Bailleux
43c5407693SSandrine BailleuxTo provide the model with the EL3 payload image, the following methods may be
44c5407693SSandrine Bailleuxused:
45c5407693SSandrine Bailleux
46c5407693SSandrine Bailleux#. If the EL3 payload is able to execute in place, it may be programmed into
47c5407693SSandrine Bailleux   flash memory. On Base Cortex and AEM FVPs, the following model parameter
48c5407693SSandrine Bailleux   loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
49c5407693SSandrine Bailleux   used for the FIP):
50c5407693SSandrine Bailleux
51c5407693SSandrine Bailleux   ::
52c5407693SSandrine Bailleux
53c5407693SSandrine Bailleux       -C bp.flashloader1.fname="<path-to>/<el3-payload>"
54c5407693SSandrine Bailleux
55c5407693SSandrine Bailleux   On Foundation FVP, there is no flash loader component and the EL3 payload
56c5407693SSandrine Bailleux   may be programmed anywhere in flash using method 3 below.
57c5407693SSandrine Bailleux
58c5407693SSandrine Bailleux#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
59c5407693SSandrine Bailleux   command may be used to load the EL3 payload ELF image over JTAG:
60c5407693SSandrine Bailleux
61c5407693SSandrine Bailleux   ::
62c5407693SSandrine Bailleux
63c5407693SSandrine Bailleux       load <path-to>/el3-payload.elf
64c5407693SSandrine Bailleux
65c5407693SSandrine Bailleux#. The EL3 payload may be pre-loaded in volatile memory using the following
66c5407693SSandrine Bailleux   model parameters:
67c5407693SSandrine Bailleux
68c5407693SSandrine Bailleux   ::
69c5407693SSandrine Bailleux
70c5407693SSandrine Bailleux       --data cluster0.cpu0="<path-to>/el3-payload>"@address   [Base FVPs]
71c5407693SSandrine Bailleux       --data="<path-to>/<el3-payload>"@address                [Foundation FVP]
72c5407693SSandrine Bailleux
73c5407693SSandrine Bailleux   The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
74c5407693SSandrine Bailleux   used when building TF-A.
75c5407693SSandrine Bailleux
76*1a219805SSalman NabiBooting a preloaded kernel image
77*1a219805SSalman Nabi--------------------------------
78c5407693SSandrine Bailleux
79*1a219805SSalman NabiTF-A can boot a Linux kernel, which uses a ramdisk as a filesystem. The
80*1a219805SSalman Nabirequired initrd properties are injected in to the device tree blob (DTB) at
81*1a219805SSalman Nabibuild time.
82c5407693SSandrine Bailleux
83*1a219805SSalman NabiPreloaded kernel image - Normal flow
84*1a219805SSalman Nabi^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
85*1a219805SSalman Nabi
86*1a219805SSalman NabiThe following example uses a simplified boot flow to boot a Linux kernel
87*1a219805SSalman Nabiusing TF-A. This can be useful if the kernel is already present in memory
88*1a219805SSalman Nabi(like in FVP).
89*1a219805SSalman Nabi
90*1a219805SSalman NabiFor example, if the kernel is loaded at ``0x80080000`` the firmware can be
91*1a219805SSalman Nabibuilt like this:
92c5407693SSandrine Bailleux
93c5407693SSandrine Bailleux.. code:: shell
94c5407693SSandrine Bailleux
95c5407693SSandrine Bailleux    make PLAT=fvp DEBUG=1             \
96c5407693SSandrine Bailleux    ARM_LINUX_KERNEL_AS_BL33=1        \
97c5407693SSandrine Bailleux    PRELOADED_BL33_BASE=0x80080000    \
98*1a219805SSalman Nabi    INITRD_SIZE=0x8000000             \
99c5407693SSandrine Bailleux    all fip
100c5407693SSandrine Bailleux
101*1a219805SSalman NabiThe options ``INITRD_SIZE`` or ``INITRD_PATH`` triggers the insertion of initrd
102*1a219805SSalman Nabiproperties in to the DTB. ``INITRD_BASE`` is also required but a default value
103*1a219805SSalman Nabiis set by the FVP platform.
104c5407693SSandrine Bailleux
105*1a219805SSalman NabiThe options available here are:
106c5407693SSandrine Bailleux
107*1a219805SSalman Nabi    ::
108*1a219805SSalman Nabi        INITRD_BASE: Set the initrd base address in memory. Defaults to 0x90000000 in FVP.
109*1a219805SSalman Nabi        INITRD_SIZE: Set the initrd size in dec or hex format. Hex format must precede with '0x'.
110*1a219805SSalman Nabi        INITRD_PATH: Provide an initrd path for the build time to determine its exact size.
111c5407693SSandrine Bailleux
112*1a219805SSalman NabiUsers can provide either ``INITRD_SIZE`` or ``INITRD_PATH`` to set the initrd
113*1a219805SSalman Nabisize value. ``INITRD_SIZE`` takes prioty over ``INITRD_PATH``.
114c5407693SSandrine Bailleux
115*1a219805SSalman NabiNow the FVP binary can be run with the following command:
116c5407693SSandrine Bailleux
117c5407693SSandrine Bailleux.. code:: shell
118c5407693SSandrine Bailleux
119c5407693SSandrine Bailleux    <path-to>/FVP_Base_AEMv8A-AEMv8A                            \
120*1a219805SSalman Nabi    -C bp.secureflashloader.fname=<path-to>/bl1.bin             \
121*1a219805SSalman Nabi    -C bp.flashloader0.fname=<path-to>/fip.bin                  \
122*1a219805SSalman Nabi    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
123*1a219805SSalman Nabi    --data cluster0.cpu0="<path-to>/<initrd.bin>"@0x90000000
124*1a219805SSalman Nabi
125*1a219805SSalman Nabi.. note::
126*1a219805SSalman Nabi    Providing a higher value for an initrd size than the actual size of the file
127*1a219805SSalman Nabi    is supported but it will trigger a non-breaking "Initramfs unpacking failed"
128*1a219805SSalman Nabi    error by the kernel at runtime. This error can be ignored because initrd's
129*1a219805SSalman Nabi    can be stacked one after another, when the kernel unpacks the first initrd it
130*1a219805SSalman Nabi    looks for another in the extra space which it won't find, hence the error.
131*1a219805SSalman Nabi
132*1a219805SSalman NabiBooting a preloaded kernel image - Reset to BL31 (Base FVP)
133*1a219805SSalman Nabi^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
134*1a219805SSalman Nabi
135*1a219805SSalman NabiWe can also boot a Linux kernel by jumping directly to BL31 ``RESET_TO_BL31=1``.
136*1a219805SSalman NabiThis requires preloading a DTB into memory. We can inject the initrd start and
137*1a219805SSalman Nabiend properties into the DTB (HW_CONFIG) at build time which is then stored by
138*1a219805SSalman NabiTF-A in ``build/fvp/<build-type>/fdts/`` directory.
139*1a219805SSalman Nabi
140*1a219805SSalman NabiFor example, we can build the firmware as:
141*1a219805SSalman Nabi
142*1a219805SSalman Nabi.. code:: shell
143*1a219805SSalman Nabi
144*1a219805SSalman Nabi    make PLAT=fvp DEBUG=1                   \
145*1a219805SSalman Nabi    RESET_TO_BL31=1                         \
146*1a219805SSalman Nabi    ARM_LINUX_KERNEL_AS_BL33=1              \
147*1a219805SSalman Nabi    PRELOADED_BL33_BASE=0x80080000          \
148*1a219805SSalman Nabi    ARM_PRELOADED_DTB_BASE=0x87F00000       \
149*1a219805SSalman Nabi    INITRD_BASE=0x88000000                  \
150*1a219805SSalman Nabi    INITRD_PATH=<path-to>/initrd.bin
151*1a219805SSalman Nabi
152*1a219805SSalman NabiNow we can run the binary as:
153*1a219805SSalman Nabi
154*1a219805SSalman Nabi.. code:: shell
155*1a219805SSalman Nabi
156*1a219805SSalman Nabi    <path-to>/FVP_Base_AEMv8A-AEMv8A                               \
157c5407693SSandrine Bailleux    -C cluster0.NUM_CORES=4                                        \
158c5407693SSandrine Bailleux    -C cluster0.cpu0.RVBAR=0x04001000                              \
159c5407693SSandrine Bailleux    -C cluster0.cpu1.RVBAR=0x04001000                              \
160c5407693SSandrine Bailleux    -C cluster0.cpu2.RVBAR=0x04001000                              \
161c5407693SSandrine Bailleux    -C cluster0.cpu3.RVBAR=0x04001000                              \
162c5407693SSandrine Bailleux    --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000           \
163c5407693SSandrine Bailleux    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000    \
164*1a219805SSalman Nabi    --data cluster0.cpu0="<path-to>/<initrd.bin>"@0x88000000       \
165*1a219805SSalman Nabi    --data cluster0.cpu0="<path-to>/fdts/fvp-base-gicv3-psci.dtb"@87F00000
166c5407693SSandrine Bailleux
167c5407693SSandrine BailleuxObtaining the Flattened Device Trees
168c5407693SSandrine Bailleux^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
169c5407693SSandrine Bailleux
170c5407693SSandrine BailleuxDepending on the FVP configuration and Linux configuration used, different
171c5407693SSandrine BailleuxFDT files are required. FDT source files for the Foundation and Base FVPs can
172c5407693SSandrine Bailleuxbe found in the TF-A source directory under ``fdts/``. The Foundation FVP has
173c5407693SSandrine Bailleuxa subset of the Base FVP components. For example, the Foundation FVP lacks
174c5407693SSandrine BailleuxCLCD and MMC support, and has only one CPU cluster.
175c5407693SSandrine Bailleux
176c5407693SSandrine Bailleux.. note::
177c5407693SSandrine Bailleux   It is not recommended to use the FDTs built along the kernel because not
178c5407693SSandrine Bailleux   all FDTs are available from there.
179c5407693SSandrine Bailleux
180c5407693SSandrine BailleuxThe dynamic configuration capability is enabled in the firmware for FVPs.
181c5407693SSandrine BailleuxThis means that the firmware can authenticate and load the FDT if present in
182c5407693SSandrine BailleuxFIP. A default FDT is packaged into FIP during the build based on
183c5407693SSandrine Bailleuxthe build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
184c5407693SSandrine Bailleuxor ``FVP_HW_CONFIG_DTS`` build options (refer to
185c5407693SSandrine Bailleux:ref:`build_options_arm_fvp_platform` for details on the options).
186c5407693SSandrine Bailleux
187c5407693SSandrine Bailleux-  ``fvp-base-gicv2-psci.dts``
188c5407693SSandrine Bailleux
189c5407693SSandrine Bailleux   For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
190c5407693SSandrine Bailleux   without shifted affinities and with Base memory map configuration.
191c5407693SSandrine Bailleux
192c5407693SSandrine Bailleux-  ``fvp-base-gicv3-psci.dts``
193c5407693SSandrine Bailleux
194c5407693SSandrine Bailleux   For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
195c5407693SSandrine Bailleux   without shifted affinities and with Base memory map configuration and
196c5407693SSandrine Bailleux   Linux GICv3 support.
197c5407693SSandrine Bailleux
198c5407693SSandrine Bailleux-  ``fvp-base-gicv3-psci-1t.dts``
199c5407693SSandrine Bailleux
200c5407693SSandrine Bailleux   For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
201c5407693SSandrine Bailleux   single threaded CPUs, Base memory map configuration and Linux GICv3 support.
202c5407693SSandrine Bailleux
203c5407693SSandrine Bailleux-  ``fvp-base-gicv3-psci-dynamiq.dts``
204c5407693SSandrine Bailleux
205c5407693SSandrine Bailleux   For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
206c5407693SSandrine Bailleux   single cluster, single threaded CPUs, Base memory map configuration and Linux
207c5407693SSandrine Bailleux   GICv3 support.
208c5407693SSandrine Bailleux
209c5407693SSandrine Bailleux-  ``fvp-foundation-gicv2-psci.dts``
210c5407693SSandrine Bailleux
211c5407693SSandrine Bailleux   For use with Foundation FVP with Base memory map configuration.
212c5407693SSandrine Bailleux
213c5407693SSandrine Bailleux-  ``fvp-foundation-gicv3-psci.dts``
214c5407693SSandrine Bailleux
215c5407693SSandrine Bailleux   (Default) For use with Foundation FVP with Base memory map configuration
216c5407693SSandrine Bailleux   and Linux GICv3 support.
217c5407693SSandrine Bailleux
218c5407693SSandrine Bailleux--------------
219c5407693SSandrine Bailleux
220c5407693SSandrine Bailleux*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
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