1Running on the Cortex-A32 Base FVP (AArch32) 2============================================ 3 4With reset to BL1 entrypoint 5^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 6 7The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 8boot Linux with 4 CPUs using the AArch32 build of TF-A. 9 10.. code:: shell 11 12 <path-to>/FVP_Base_Cortex-A32x4 \ 13 -C pctl.startup=0.0.0.0 \ 14 -C bp.secure_memory=1 \ 15 -C bp.tzc_400.diagnostics=1 \ 16 -C cache_state_modelled=1 \ 17 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 18 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 19 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 20 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 21 22With reset to SP_MIN entrypoint 23^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 24 25The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to 26boot Linux with 4 CPUs using the AArch32 build of TF-A. 27 28.. code:: shell 29 30 <path-to>/FVP_Base_Cortex-A32x4 \ 31 -C pctl.startup=0.0.0.0 \ 32 -C bp.secure_memory=1 \ 33 -C bp.tzc_400.diagnostics=1 \ 34 -C cache_state_modelled=1 \ 35 -C cluster0.cpu0.RVBARADDR=0x04002000 \ 36 -C cluster0.cpu1.RVBARADDR=0x04002000 \ 37 -C cluster0.cpu2.RVBARADDR=0x04002000 \ 38 -C cluster0.cpu3.RVBARADDR=0x04002000 \ 39 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 40 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 41 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 42 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 43 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 44 45-------------- 46 47*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 48