1*c5407693SSandrine Bailleux.. _build_options_arm_fvp_platform: 2*c5407693SSandrine Bailleux 3*c5407693SSandrine BailleuxArm FVP Platform Specific Build Options 4*c5407693SSandrine Bailleux--------------------------------------- 5*c5407693SSandrine Bailleux 6*c5407693SSandrine Bailleux- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to 7*c5407693SSandrine Bailleux build the topology tree within TF-A. By default TF-A is configured for dual 8*c5407693SSandrine Bailleux cluster topology and this option can be used to override the default value. 9*c5407693SSandrine Bailleux 10*c5407693SSandrine Bailleux- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The 11*c5407693SSandrine Bailleux default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as 12*c5407693SSandrine Bailleux explained in the options below: 13*c5407693SSandrine Bailleux 14*c5407693SSandrine Bailleux - ``FVP_CCI`` : The CCI driver is selected. This is the default 15*c5407693SSandrine Bailleux if 0 < ``FVP_CLUSTER_COUNT`` <= 2. 16*c5407693SSandrine Bailleux - ``FVP_CCN`` : The CCN driver is selected. This is the default 17*c5407693SSandrine Bailleux if ``FVP_CLUSTER_COUNT`` > 2. 18*c5407693SSandrine Bailleux 19*c5407693SSandrine Bailleux- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in 20*c5407693SSandrine Bailleux a single cluster. This option defaults to 4. 21*c5407693SSandrine Bailleux 22*c5407693SSandrine Bailleux- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU 23*c5407693SSandrine Bailleux in the system. This option defaults to 1. Note that the build option 24*c5407693SSandrine Bailleux ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. 25*c5407693SSandrine Bailleux 26*c5407693SSandrine Bailleux- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: 27*c5407693SSandrine Bailleux 28*c5407693SSandrine Bailleux - ``FVP_GICV2`` : The GICv2 only driver is selected 29*c5407693SSandrine Bailleux - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) 30*c5407693SSandrine Bailleux 31*c5407693SSandrine Bailleux- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled 32*c5407693SSandrine Bailleux to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for 33*c5407693SSandrine Bailleux details on HW_CONFIG. By default, this is initialized to a sensible DTS 34*c5407693SSandrine Bailleux file in ``fdts/`` folder depending on other build options. But some cases, 35*c5407693SSandrine Bailleux like shifted affinity format for MPIDR, cannot be detected at build time 36*c5407693SSandrine Bailleux and this option is needed to specify the appropriate DTS file. 37*c5407693SSandrine Bailleux 38*c5407693SSandrine Bailleux- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in 39*c5407693SSandrine Bailleux FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is 40*c5407693SSandrine Bailleux similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the 41*c5407693SSandrine Bailleux HW_CONFIG blob instead of the DTS file. This option is useful to override 42*c5407693SSandrine Bailleux the default HW_CONFIG selected by the build system. 43*c5407693SSandrine Bailleux 44*c5407693SSandrine Bailleux- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of 45*c5407693SSandrine Bailleux inactive/fused CPU cores as read-only. The default value of this option 46*c5407693SSandrine Bailleux is ``0``, which means the redistributor pages of all CPU cores are marked 47*c5407693SSandrine Bailleux as read and write. 48*c5407693SSandrine Bailleux 49*c5407693SSandrine Bailleux-------------- 50*c5407693SSandrine Bailleux 51*c5407693SSandrine Bailleux*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 52