1Arm Development Platform Build Options 2====================================== 3 4Arm Platform Build Options 5-------------------------- 6 7- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured 8 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load 9 BL31 in TZC secured DRAM. If TSP is present, then setting this option also 10 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build 11 flag. 12 13- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>`` 14 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The 15 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which 16 should match the frame used by the Non-Secure image (normally the Linux 17 kernel). Default is true (access to the frame is allowed). 18 19- ``ARM_FW_CONFIG_LOAD_ENABLE``: Boolean option to enable the loading of 20 FW_CONFIG device trees from the Firmware Image Package (FIP). When enabled, 21 BL2 calls the platform specific function `arm_bl2_el3_plat_config_load`. 22 This function is responsible for loading, parsing, and validating the 23 FW_CONFIG device trees from the FIP. The option depends on RESET_TO_BL2. 24 25- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog. 26 By default, Arm platforms use a watchdog to trigger a system reset in case 27 an error is encountered during the boot process (for example, when an image 28 could not be loaded or authenticated). The watchdog is enabled in the early 29 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The 30 Trusted Watchdog may be disabled at build time for testing or development 31 purposes. 32 33- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to 34 have specific values at boot. This boolean option allows the Trusted Firmware 35 to have a Linux kernel image as BL33 by preparing the registers to these 36 values before jumping to BL33. This option defaults to 0 (disabled). For 37 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when 38 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set 39 to the location of a device tree blob (DTB) already loaded in memory. The 40 Linux Image address must be specified using the ``PRELOADED_BL33_BASE`` 41 option. 42 43- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to 44 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag 45 is set, the functions which deal with MPIDR assume that the ``MT`` bit in 46 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of 47 this flag is 0. Note that this option is not used on FVP platforms. 48 49- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding 50 for the construction of composite state-ID in the power-state parameter. 51 The existing PSCI clients currently do not support this encoding of 52 State-ID yet. Hence this flag is used to configure whether to use the 53 recommended State-ID encoding or not. The default value of this flag is 0, 54 in which case the platform is configured to expect NULL in the State-ID 55 field of power-state parameter. 56 57- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the 58 location of the ROTPK returned by the function ``plat_get_rotpk_info()`` 59 for Arm platforms. Depending on the selected option, the proper private key 60 must be specified using the ``ROT_KEY`` option when building the Trusted 61 Firmware. This private key will be used by the certificate generation tool 62 to sign the BL2 and Trusted Key certificates. Available options for 63 ``ARM_ROTPK_LOCATION`` are: 64 65 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage 66 registers. 67 - ``devel_rsa`` : return a development public key hash embedded in the BL1 68 and BL2 binaries. This hash corresponds to the development private key 69 ``plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem``. 70 The hashing algorithm is selected by ``HASH_ALG``; sha256 is used if 71 ``HASH_ALG`` is not specified. A different RSA key can be specified by setting 72 ``ROT_KEY``, there are 3k and 4k RSA keys in ``plat/arm/board/common/rotpk/``. 73 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1 74 and BL2 binaries. This hash corresponds to the development private key 75 ``plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem`` unless a different key 76 is specified with ``ROT_KEY``, such as the 384 bit key in the same directory. 77 he hashing algorithm is selected by ``HASH_ALG``; sha256 is used if ``HASH_ALG`` 78 is not specified. 79 - ``devel_full_dev_rsa_key`` : return a development public key embedded in 80 the BL1 and BL2 binaries. This key corresponds to the RSA private 81 key ``plat/arm/board/common/rotpk/arm_rotprivk.pem`` by default, but can 82 be changed by setting ``ROT_KEY``, there are 3k and 4k RSA keys in 83 ``plat/arm/board/common/rotpk/``. 84 - ``devel_full_dev_ecdsa_key`` : return a development public key embedded in 85 the BL1 and BL2 binaries. This key corresponds to the EC private key 86 ``plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem``, unless a different 87 ECDSA key is specified by ``ROT_KEY``, such as the 384 bit key in the same directory. 88 89- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options: 90 91 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled) 92 - ``tdram`` : Trusted DRAM (if available) 93 - ``dram`` : Secure region in DRAM (default option when TBB is enabled, 94 configured by the TrustZone controller) 95 96- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1 97 of the translation tables library instead of version 2. It is set to 0 by 98 default, which selects version 2. 99 100- ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of 101 the various partitions present in the GPT image. This support is available 102 only for the BL2 component, and it is disabled by default. 103 The following diagram shows the view of the FIP partition inside the GPT 104 image: 105 106 |FIP in a GPT image| 107 108For a better understanding of these options, the Arm development platform memory 109map is explained in the :ref:`Firmware Design`. 110 111.. _build_options_arm_css_platform: 112 113Arm CSS Platform-Specific Build Options 114--------------------------------------- 115 116- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version 117 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards 118 compatible change to the MTL protocol, used for AP/SCP communication. 119 TF-A no longer supports earlier SCP versions. If this option is set to 1 120 then TF-A will detect if an earlier version is in use. Default is 1. 121 122- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and 123 SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded 124 during boot. Default is 1. 125 126- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers 127 instead of SCPI/BOM driver for communicating with the SCP during power 128 management operations and for SCP RAM Firmware transfer. If this option 129 is set to 1, then SCMI/SDS drivers will be used. Default is 0. 130 131- ``CSS_SYSTEM_GRACEFUL_RESET``: Build option to enable graceful powerdown of 132 CPU core on reset. This build option can be used on CSS platforms that 133 require all the CPUs to execute the CPU specific power down sequence to 134 complete a warm reboot sequence in which only the CPUs are power cycled. 135 136Arm FVP Build Options 137--------------------- 138 139- ``FVP_TRUSTED_SRAM_SIZE``: Size (in kilobytes) of the Trusted SRAM region to 140 utilize when building for the FVP platform. This option defaults to 256 with 141 build option ENABLE_RME=0 and 384 for ENABLE_RME=1. 142 143Arm Juno Build Options 144---------------------- 145 146- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 147 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 148 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 149 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 150 images. 151 152Arm Neoverse RD Platform Build Options 153-------------------------------------- 154 155 - ``NRD_CHIP_COUNT``: Configures the number of chips on a Neoverse RD platform 156 which supports multi-chip operation. If ``NRD_CHIP_COUNT`` is set to any 157 valid value greater than 1, the platform code performs required configuration 158 to support multi-chip operation. 159 160- ``NRD_PLATFORM_VARIANT``: Selects the variant of a Neoverse RD platform. A 161 particular Neoverse RD platform may have multiple variants which may differ in 162 core count, cluster count or other peripherals. This build option is used to 163 select the appropriate platform variant for the build. The range of valid 164 values is platform specific. 165 166-------------- 167 168.. |FIP in a GPT image| image:: ../../resources/diagrams/FIP_in_a_GPT_image.png 169 170*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 171
