1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 26 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 27 ``aarch64``. 28 29- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 30 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 31 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 32 :ref:`Firmware Design`. 33 34- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 35 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 36 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 37 38- ``BL2``: This is an optional build option which specifies the path to BL2 39 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 40 built. 41 42- ``BL2U``: This is an optional build option which specifies the path to 43 BL2U image. In this case, the BL2U in TF-A will not be built. 44 45- ``BL2_AT_EL3``: This is an optional build option that enables the use of 46 BL2 at EL3 execution level. 47 48- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 49 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 50 the RW sections in RAM, while leaving the RO sections in place. This option 51 enable this use-case. For now, this option is only supported when BL2_AT_EL3 52 is set to '1'. 53 54- ``BL31``: This is an optional build option which specifies the path to 55 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 56 be built. 57 58- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 59 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 60 this file name will be used to save the key. 61 62- ``BL32``: This is an optional build option which specifies the path to 63 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 64 be built. 65 66- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 67 Trusted OS Extra1 image for the ``fip`` target. 68 69- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 70 Trusted OS Extra2 image for the ``fip`` target. 71 72- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 73 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 74 this file name will be used to save the key. 75 76- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 77 ``fip`` target in case TF-A BL2 is used. 78 79- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 80 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 81 this file name will be used to save the key. 82 83- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 84 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 85 If enabled, it is needed to use a compiler that supports the option 86 ``-mbranch-protection``. Selects the branch protection features to use: 87- 0: Default value turns off all types of branch protection 88- 1: Enables all types of branch protection features 89- 2: Return address signing to its standard level 90- 3: Extend the signing to include leaf functions 91 92 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 93 and resulting PAuth/BTI features. 94 95 +-------+--------------+-------+-----+ 96 | Value | GCC option | PAuth | BTI | 97 +=======+==============+=======+=====+ 98 | 0 | none | N | N | 99 +-------+--------------+-------+-----+ 100 | 1 | standard | Y | Y | 101 +-------+--------------+-------+-----+ 102 | 2 | pac-ret | Y | N | 103 +-------+--------------+-------+-----+ 104 | 3 | pac-ret+leaf | Y | N | 105 +-------+--------------+-------+-----+ 106 107 This option defaults to 0 and this is an experimental feature. 108 Note that Pointer Authentication is enabled for Non-secure world 109 irrespective of the value of this option if the CPU supports it. 110 111- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 112 compilation of each build. It must be set to a C string (including quotes 113 where applicable). Defaults to a string that contains the time and date of 114 the compilation. 115 116- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 117 build to be uniquely identified. Defaults to the current git commit id. 118 119- ``CFLAGS``: Extra user options appended on the compiler's command line in 120 addition to the options set by the build system. 121 122- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 123 release several CPUs out of reset. It can take either 0 (several CPUs may be 124 brought up) or 1 (only one CPU will ever be brought up during cold reset). 125 Default is 0. If the platform always brings up a single CPU, there is no 126 need to distinguish between primary and secondary CPUs and the boot path can 127 be optimised. The ``plat_is_my_cpu_primary()`` and 128 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 129 to be implemented in this case. 130 131- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 132 register state when an unexpected exception occurs during execution of 133 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 134 this is only enabled for a debug build of the firmware. 135 136- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 137 certificate generation tool to create new keys in case no valid keys are 138 present or specified. Allowed options are '0' or '1'. Default is '1'. 139 140- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 141 the AArch32 system registers to be included when saving and restoring the 142 CPU context. The option must be set to 0 for AArch64-only platforms (that 143 is on hardware that does not implement AArch32, or at least not at EL1 and 144 higher ELs). Default value is 1. 145 146- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 147 registers to be included when saving and restoring the CPU context. Default 148 is 0. 149 150- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 151 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 152 registers to be included when saving and restoring the CPU context as 153 part of world switch. Default value is 0 and this is an experimental feature. 154 Note that Pointer Authentication is enabled for Non-secure world irrespective 155 of the value of this flag if the CPU supports it. 156 157- ``DEBUG``: Chooses between a debug and release build. It can take either 0 158 (release) or 1 (debug) as values. 0 is the default. 159 160- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 161 of the binary image. If set to 1, then only the ELF image is built. 162 0 is the default. 163 164- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 165 Board Boot authentication at runtime. This option is meant to be enabled only 166 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 167 flag has to be enabled. 0 is the default. 168 169- ``E``: Boolean option to make warnings into errors. Default is 1. 170 171- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 172 the normal boot flow. It must specify the entry point address of the EL3 173 payload. Please refer to the "Booting an EL3 payload" section for more 174 details. 175 176- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 177 This is an optional architectural feature available on v8.4 onwards. Some 178 v8.2 implementations also implement an AMU and this option can be used to 179 enable this feature on those systems as well. Default is 0. 180 181- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 182 are compiled out. For debug builds, this option defaults to 1, and calls to 183 ``assert()`` are left in place. For release builds, this option defaults to 0 184 and calls to ``assert()`` function are compiled out. This option can be set 185 independently of ``DEBUG``. It can also be used to hide any auxiliary code 186 that is only required for the assertion and does not fit in the assertion 187 itself. 188 189- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace 190 dumps or not. It is supported in both AArch64 and AArch32. However, in 191 AArch32 the format of the frame records are not defined in the AAPCS and they 192 are defined by the implementation. This implementation of backtrace only 193 supports the format used by GCC when T32 interworking is disabled. For this 194 reason enabling this option in AArch32 will force the compiler to only 195 generate A32 code. This option is enabled by default only in AArch64 debug 196 builds, but this behaviour can be overridden in each platform's Makefile or 197 in the build command line. 198 199- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 200 feature. MPAM is an optional Armv8.4 extension that enables various memory 201 system components and resources to define partitions; software running at 202 various ELs can assign themselves to desired partition to control their 203 performance aspects. 204 205 When this option is set to ``1``, EL3 allows lower ELs to access their own 206 MPAM registers without trapping into EL3. This option doesn't make use of 207 partitioning in EL3, however. Platform initialisation code should configure 208 and use partitions in EL3 as required. This option defaults to ``0``. 209 210- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 211 support within generic code in TF-A. This option is currently only supported 212 in BL31. Default is 0. 213 214- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 215 Measurement Framework(PMF). Default is 0. 216 217- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 218 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 219 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 220 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 221 software. 222 223- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 224 instrumentation which injects timestamp collection points into TF-A to 225 allow runtime performance to be measured. Currently, only PSCI is 226 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 227 as well. Default is 0. 228 229- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 230 extensions. This is an optional architectural feature for AArch64. 231 The default is 1 but is automatically disabled when the target architecture 232 is AArch32. 233 234- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM). 235 Refer to :ref:`Secure Partition Manager` for more details about 236 this feature. Default is 0. 237 238- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 239 (SVE) for the Non-secure world only. SVE is an optional architectural feature 240 for AArch64. Note that when SVE is enabled for the Non-secure world, access 241 to SIMD and floating-point functionality from the Secure world is disabled. 242 This is to avoid corruption of the Non-secure world data in the Z-registers 243 which are aliased by the SIMD and FP registers. The build option is not 244 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 245 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 246 1. The default is 1 but is automatically disabled when the target 247 architecture is AArch32. 248 249- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 250 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 251 default value is set to "none". "strong" is the recommended stack protection 252 level if this feature is desired. "none" disables the stack protection. For 253 all values other than "none", the ``plat_get_stack_protector_canary()`` 254 platform hook needs to be implemented. The value is passed as the last 255 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 256 257- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 258 deprecated platform APIs, helper functions or drivers within Trusted 259 Firmware as error. It can take the value 1 (flag the use of deprecated 260 APIs as error) or 0. The default is 0. 261 262- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 263 targeted at EL3. When set ``0`` (default), no exceptions are expected or 264 handled at EL3, and a panic will result. This is supported only for AArch64 265 builds. 266 267- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 268 injection from lower ELs, and this build option enables lower ELs to use 269 Error Records accessed via System Registers to inject faults. This is 270 applicable only to AArch64 builds. 271 272 This feature is intended for testing purposes only, and is advisable to keep 273 disabled for production images. 274 275- ``FIP_NAME``: This is an optional build option which specifies the FIP 276 filename for the ``fip`` target. Default is ``fip.bin``. 277 278- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 279 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 280 281- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 282 tool to create certificates as per the Chain of Trust described in 283 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 284 include the certificates in the FIP and FWU_FIP. Default value is '0'. 285 286 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 287 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 288 the corresponding certificates, and to include those certificates in the 289 FIP and FWU_FIP. 290 291 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 292 images will not include support for Trusted Board Boot. The FIP will still 293 include the corresponding certificates. This FIP can be used to verify the 294 Chain of Trust on the host machine through other mechanisms. 295 296 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 297 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 298 will not include the corresponding certificates, causing a boot failure. 299 300- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 301 inherent support for specific EL3 type interrupts. Setting this build option 302 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 303 by `platform abstraction layer`__ and `Interrupt Management Framework`__. 304 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 305 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 306 the Secure Payload interrupts needs to be synchronously handed over to Secure 307 EL1 for handling. The default value of this option is ``0``, which means the 308 Group 0 interrupts are assumed to be handled by Secure EL1. 309 310 .. __: `platform-interrupt-controller-API.rst` 311 .. __: `interrupt-framework-design.rst` 312 313- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 314 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 315 ``0`` (default), these exceptions will be trapped in the current exception 316 level (or in EL1 if the current exception level is EL0). 317 318- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 319 software operations are required for CPUs to enter and exit coherency. 320 However, newer systems exist where CPUs' entry to and exit from coherency 321 is managed in hardware. Such systems require software to only initiate these 322 operations, and the rest is managed in hardware, minimizing active software 323 management. In such systems, this boolean option enables TF-A to carry out 324 build and run-time optimizations during boot and power management operations. 325 This option defaults to 0 and if it is enabled, then it implies 326 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 327 328 If this flag is disabled while the platform which TF-A is compiled for 329 includes cores that manage coherency in hardware, then a compilation error is 330 generated. This is based on the fact that a system cannot have, at the same 331 time, cores that manage coherency in hardware and cores that don't. In other 332 words, a platform cannot have, at the same time, cores that require 333 ``HW_ASSISTED_COHERENCY=1`` and cores that require 334 ``HW_ASSISTED_COHERENCY=0``. 335 336 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 337 translation library (xlat tables v2) must be used; version 1 of translation 338 library is not supported. 339 340- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 341 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 342 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 343 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 344 images. 345 346- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 347 used for generating the PKCS keys and subsequent signing of the certificate. 348 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 349 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 350 compliant and is retained only for compatibility. The default value of this 351 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 352 353- ``HASH_ALG``: This build flag enables the user to select the secure hash 354 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 355 The default value of this flag is ``sha256``. 356 357- ``LDFLAGS``: Extra user options appended to the linkers' command line in 358 addition to the one set by the build system. 359 360- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 361 output compiled into the build. This should be one of the following: 362 363 :: 364 365 0 (LOG_LEVEL_NONE) 366 10 (LOG_LEVEL_ERROR) 367 20 (LOG_LEVEL_NOTICE) 368 30 (LOG_LEVEL_WARNING) 369 40 (LOG_LEVEL_INFO) 370 50 (LOG_LEVEL_VERBOSE) 371 372 All log output up to and including the selected log level is compiled into 373 the build. The default value is 40 in debug builds and 20 in release builds. 374 375- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 376 specifies the file that contains the Non-Trusted World private key in PEM 377 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 378 379- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 380 optional. It is only needed if the platform makefile specifies that it 381 is required in order to build the ``fwu_fip`` target. 382 383- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 384 contents upon world switch. It can take either 0 (don't save and restore) or 385 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 386 wants the timer registers to be saved and restored. 387 388- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 389 for the BL image. It can be either 0 (include) or 1 (remove). The default 390 value is 0. 391 392- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 393 the underlying hardware is not a full PL011 UART but a minimally compliant 394 generic UART, which is a subset of the PL011. The driver will not access 395 any register that is not part of the SBSA generic UART specification. 396 Default value is 0 (a full PL011 compliant UART is present). 397 398- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 399 must be subdirectory of any depth under ``plat/``, and must contain a 400 platform makefile named ``platform.mk``. For example, to build TF-A for the 401 Arm Juno board, select PLAT=juno. 402 403- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 404 instead of the normal boot flow. When defined, it must specify the entry 405 point address for the preloaded BL33 image. This option is incompatible with 406 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 407 over ``PRELOADED_BL33_BASE``. 408 409- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 410 vector address can be programmed or is fixed on the platform. It can take 411 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 412 programmable reset address, it is expected that a CPU will start executing 413 code directly at the right address, both on a cold and warm reset. In this 414 case, there is no need to identify the entrypoint on boot and the boot path 415 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 416 does not need to be implemented in this case. 417 418- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 419 possible for the PSCI power-state parameter: original and extended State-ID 420 formats. This flag if set to 1, configures the generic PSCI layer to use the 421 extended format. The default value of this flag is 0, which means by default 422 the original power-state format is used by the PSCI implementation. This flag 423 should be specified by the platform makefile and it governs the return value 424 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 425 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 426 set to 1 as well. 427 428- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 429 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 430 or later CPUs. 431 432 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 433 set to ``1``. 434 435 This option is disabled by default. 436 437- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 438 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 439 entrypoint) or 1 (CPU reset to BL31 entrypoint). 440 The default value is 0. 441 442- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 443 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 444 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 445 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 446 447- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 448 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this 449 file name will be used to save the key. 450 451- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 452 certificate generation tool to save the keys used to establish the Chain of 453 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 454 455- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 456 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 457 target. 458 459- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 460 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 461 this file name will be used to save the key. 462 463- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 464 optional. It is only needed if the platform makefile specifies that it 465 is required in order to build the ``fwu_fip`` target. 466 467- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 468 Delegated Exception Interface to BL31 image. This defaults to ``0``. 469 470 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 471 set to ``1``. 472 473- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 474 isolated on separate memory pages. This is a trade-off between security and 475 memory usage. See "Isolating code and read-only data on separate memory 476 pages" section in :ref:`Firmware Design`. This flag is disabled by default and 477 affects all BL images. 478 479- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 480 This build option is only valid if ``ARCH=aarch64``. The value should be 481 the path to the directory containing the SPD source, relative to 482 ``services/spd/``; the directory is expected to contain a makefile called 483 ``<spd-value>.mk``. 484 485- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 486 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 487 execution in BL1 just before handing over to BL31. At this point, all 488 firmware images have been loaded in memory, and the MMU and caches are 489 turned off. Refer to the "Debugging options" section for more details. 490 491- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 492 secure interrupts (caught through the FIQ line). Platforms can enable 493 this directive if they need to handle such interruption. When enabled, 494 the FIQ are handled in monitor mode and non secure world is not allowed 495 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 496 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 497 498- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 499 Boot feature. When set to '1', BL1 and BL2 images include support to load 500 and verify the certificates and images in a FIP, and BL1 includes support 501 for the Firmware Update. The default value is '0'. Generation and inclusion 502 of certificates in the FIP and FWU_FIP depends upon the value of the 503 ``GENERATE_COT`` option. 504 505 .. warning:: 506 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 507 already exist in disk, they will be overwritten without further notice. 508 509- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 510 specifies the file that contains the Trusted World private key in PEM 511 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 512 513- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 514 synchronous, (see "Initializing a BL32 Image" section in 515 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 516 synchronous method) or 1 (BL32 is initialized using asynchronous method). 517 Default is 0. 518 519- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 520 routing model which routes non-secure interrupts asynchronously from TSP 521 to EL3 causing immediate preemption of TSP. The EL3 is responsible 522 for saving and restoring the TSP context in this routing model. The 523 default routing model (when the value is 0) is to route non-secure 524 interrupts to TSP allowing it to save its context and hand over 525 synchronously to EL3 via an SMC. 526 527 .. note:: 528 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 529 must also be set to ``1``. 530 531- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 532 linker. When the ``LINKER`` build variable points to the armlink linker, 533 this flag is enabled automatically. To enable support for armlink, platforms 534 will have to provide a scatter file for the BL image. Currently, Tegra 535 platforms use the armlink support to compile BL3-1 images. 536 537- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 538 memory region in the BL memory map or not (see "Use of Coherent memory in 539 TF-A" section in :ref:`Firmware Design`). It can take the value 1 540 (Coherent memory region is included) or 0 (Coherent memory region is 541 excluded). Default is 1. 542 543- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 544 This feature creates a library of functions to be placed in ROM and thus 545 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 546 is 0. 547 548- ``V``: Verbose build. If assigned anything other than 0, the build commands 549 are printed. Default is 0. 550 551- ``VERSION_STRING``: String used in the log output for each TF-A image. 552 Defaults to a string formed by concatenating the version number, build type 553 and build string. 554 555- ``W``: Warning level. Some compiler warning options of interest have been 556 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 557 each level enabling more warning options. Default is 0. 558 559- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 560 the CPU after warm boot. This is applicable for platforms which do not 561 require interconnect programming to enable cache coherency (eg: single 562 cluster platforms). If this option is enabled, then warm boot path 563 enables D-caches immediately after enabling MMU. This option defaults to 0. 564 565Debugging options 566----------------- 567 568To compile a debug version and make the build more verbose use 569 570.. code:: shell 571 572 make PLAT=<platform> DEBUG=1 V=1 all 573 574AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 575example DS-5) might not support this and may need an older version of DWARF 576symbols to be emitted by GCC. This can be achieved by using the 577``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 578version to 2 is recommended for DS-5 versions older than 5.16. 579 580When debugging logic problems it might also be useful to disable all compiler 581optimizations by using ``-O0``. 582 583.. warning:: 584 Using ``-O0`` could cause output images to be larger and base addresses 585 might need to be recalculated (see the **Memory layout on Arm development 586 platforms** section in the :ref:`Firmware Design`). 587 588Extra debug options can be passed to the build system by setting ``CFLAGS`` or 589``LDFLAGS``: 590 591.. code:: shell 592 593 CFLAGS='-O0 -gdwarf-2' \ 594 make PLAT=<platform> DEBUG=1 V=1 all 595 596Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 597ignored as the linker is called directly. 598 599It is also possible to introduce an infinite loop to help in debugging the 600post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 601``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 602section. In this case, the developer may take control of the target using a 603debugger when indicated by the console output. When using DS-5, the following 604commands can be used: 605 606:: 607 608 # Stop target execution 609 interrupt 610 611 # 612 # Prepare your debugging environment, e.g. set breakpoints 613 # 614 615 # Jump over the debug loop 616 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 617 618 # Resume execution 619 continue 620 621-------------- 622 623*Copyright (c) 2019, Arm Limited. All rights reserved.* 624