1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``RMM``: This is an optional build option used when ``ENABLE_RME`` is set. 103 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 104 is not specified, TF-A builds the TRP to load and run at R-EL2. 105 106- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 107 ``fip`` target in case TF-A BL2 is used. 108 109- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 110 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 111 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 112 113- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 114 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 115 If enabled, it is needed to use a compiler that supports the option 116 ``-mbranch-protection``. The value of the ``-march`` (via ``ARM_ARCH_MINOR`` 117 and ``ARM_ARCH_MAJOR``) option will control which instructions will be 118 emitted (HINT space or not). Selects the branch protection features to use: 119- 0: Default value turns off all types of branch protection (FEAT_STATE_DISABLED) 120- 1: Enables all types of branch protection features 121- 2: Return address signing to its standard level 122- 3: Extend the signing to include leaf functions 123- 4: Turn on branch target identification mechanism 124- 5: Enables all types of branch protection features, only if present in 125 hardware (FEAT_STATE_CHECK). 126 127 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 128 and resulting PAuth/BTI features. 129 130 +-------+--------------+-------+-----+ 131 | Value | GCC option | PAuth | BTI | 132 +=======+==============+=======+=====+ 133 | 0 | none | N | N | 134 +-------+--------------+-------+-----+ 135 | 1 | standard | Y | Y | 136 +-------+--------------+-------+-----+ 137 | 2 | pac-ret | Y | N | 138 +-------+--------------+-------+-----+ 139 | 3 | pac-ret+leaf | Y | N | 140 +-------+--------------+-------+-----+ 141 | 4 | bti | N | Y | 142 +-------+--------------+-------+-----+ 143 | 5 | dynamic | Y | Y | 144 +-------+--------------+-------+-----+ 145 146 This option defaults to 0. 147 Note that Pointer Authentication is enabled for Non-secure world 148 irrespective of the value of this option if the CPU supports it. 149 150- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 151 compilation of each build. It must be set to a C string (including quotes 152 where applicable). Defaults to a string that contains the time and date of 153 the compilation. 154 155- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 156 build to be uniquely identified. Defaults to the current git commit id. 157 158- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 159 160- ``CFLAGS``: Extra user options appended on the compiler's command line in 161 addition to the options set by the build system. 162 163- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 164 release several CPUs out of reset. It can take either 0 (several CPUs may be 165 brought up) or 1 (only one CPU will ever be brought up during cold reset). 166 Default is 0. If the platform always brings up a single CPU, there is no 167 need to distinguish between primary and secondary CPUs and the boot path can 168 be optimised. The ``plat_is_my_cpu_primary()`` and 169 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 170 to be implemented in this case. 171 172- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 173 Defaults to ``tbbr``. 174 175- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 176 register state when an unexpected exception occurs during execution of 177 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 178 this is only enabled for a debug build of the firmware. 179 180- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 181 certificate generation tool to create new keys in case no valid keys are 182 present or specified. Allowed options are '0' or '1'. Default is '1'. 183 184- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 185 the AArch32 system registers to be included when saving and restoring the 186 CPU context. The option must be set to 0 for AArch64-only platforms (that 187 is on hardware that does not implement AArch32, or at least not at EL1 and 188 higher ELs). Default value is 1. 189 190- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 191 registers to be included when saving and restoring the CPU context. Default 192 is 0. 193 194- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 195 Memory System Resource Partitioning and Monitoring (MPAM) 196 registers to be included when saving and restoring the CPU context. 197 Default is '0'. 198 199- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 200 registers to be saved/restored when entering/exiting an EL2 execution 201 context. This flag can take values 0 to 2, to align with the 202 ``ENABLE_FEAT`` mechanism. Default value is 0. 203 204- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 205 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 206 to be included when saving and restoring the CPU context as part of world 207 switch. Automatically enabled when ``BRANCH_PROTECTION`` is enabled. This flag 208 can take values 0 to 2, to align with ``ENABLE_FEAT`` mechanism. Default value 209 is 0. 210 211 Note that Pointer Authentication is enabled for Non-secure world irrespective 212 of the value of this flag if the CPU supports it. Alternatively, when 213 ``BRANCH_PROTECTION`` is enabled, this flag is superseded. 214 215- ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the 216 SVE registers to be included when saving and restoring the CPU context. Note 217 that this build option requires ``ENABLE_SVE_FOR_SWD`` to be enabled. In 218 general, it is recommended to perform SVE context management in lower ELs 219 and skip in EL3 due to the additional cost of maintaining large data 220 structures to track the SVE state. Hence, the default value is 0. 221 222- ``DEBUG``: Chooses between a debug and release build. It can take either 0 223 (release) or 1 (debug) as values. 0 is the default. 224 225- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 226 authenticated decryption algorithm to be used to decrypt firmware/s during 227 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 228 this flag is ``none`` to disable firmware decryption which is an optional 229 feature as per TBBR. 230 231- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 232 of the binary image. If set to 1, then only the ELF image is built. 233 0 is the default. 234 235- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 236 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 237 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 238 mechanism. Default is ``0``. 239 240- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 241 Board Boot authentication at runtime. This option is meant to be enabled only 242 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 243 flag has to be enabled. 0 is the default. 244 245- ``E``: Boolean option to make warnings into errors. Default is 1. 246 247 When specifying higher warnings levels (``W=1`` and higher), this option 248 defaults to 0. This is done to encourage contributors to use them, as they 249 are expected to produce warnings that would otherwise fail the build. New 250 contributions are still expected to build with ``W=0`` and ``E=1`` (the 251 default). 252 253- ``EARLY_CONSOLE``: This option is used to enable early traces before default 254 console is properly setup. It introduces EARLY_* traces macros, that will 255 use the non-EARLY traces macros if the flag is enabled, or do nothing 256 otherwise. To use this feature, platforms will have to create the function 257 plat_setup_early_console(). 258 Default is 0 (disabled) 259 260- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 261 the normal boot flow. It must specify the entry point address of the EL3 262 payload. Please refer to the "Booting an EL3 payload" section for more 263 details. 264 265- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 266 (also known as group 1 counters). These are implementation-defined counters, 267 and as such require additional platform configuration. Default is 0. 268 269- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 270 are compiled out. For debug builds, this option defaults to 1, and calls to 271 ``assert()`` are left in place. For release builds, this option defaults to 0 272 and calls to ``assert()`` function are compiled out. This option can be set 273 independently of ``DEBUG``. It can also be used to hide any auxiliary code 274 that is only required for the assertion and does not fit in the assertion 275 itself. 276 277- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 278 dumps or not. It is supported in both AArch64 and AArch32. However, in 279 AArch32 the format of the frame records are not defined in the AAPCS and they 280 are defined by the implementation. This implementation of backtrace only 281 supports the format used by GCC when T32 interworking is disabled. For this 282 reason enabling this option in AArch32 will force the compiler to only 283 generate A32 code. This option is enabled by default only in AArch64 debug 284 builds, but this behaviour can be overridden in each platform's Makefile or 285 in the build command line. 286 287- ``ENABLE_FEAT`` 288 The Arm architecture defines several architecture extension features, 289 named FEAT_xxx in the architecure manual. Some of those features require 290 setup code in higher exception levels, other features might be used by TF-A 291 code itself. 292 Most of the feature flags defined in the TF-A build system permit to take 293 the values 0, 1 or 2, with the following meaning: 294 295 :: 296 297 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 298 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 299 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 300 301 When setting the flag to 0, the feature is disabled during compilation, 302 and the compiler's optimisation stage and the linker will try to remove 303 as much of this code as possible. 304 If it is defined to 1, the code will use the feature unconditionally, so the 305 CPU is expected to support that feature. The FEATURE_DETECTION debug 306 feature, if enabled, will verify this. 307 If the feature flag is set to 2, support for the feature will be compiled 308 in, but its existence will be checked at runtime, so it works on CPUs with 309 or without the feature. This is mostly useful for platforms which either 310 support multiple different CPUs, or where the CPU is configured at runtime, 311 like in emulators. 312 313- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 314 extensions. This flag can take the values 0 to 2, to align with the 315 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 316 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 317 and this option can be used to enable this feature on those systems as well. 318 This flag can take the values 0 to 2, the default is 0. 319 320- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 321 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 322 onwards. This flag can take the values 0 to 2, to align with the 323 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 324 325- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 326 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 327 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 328 optional feature available on Arm v8.0 onwards. This flag can take values 329 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 330 Default value is ``0``. 331 332- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 333 extension. This feature is supported in AArch64 state only and is an optional 334 feature available in Arm v8.0 implementations. 335 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 336 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 337 mechanism. Default value is ``0``. 338 339- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 340 extension which allows the ability to implement more than 16 breakpoints 341 and/or watchpoints. This feature is mandatory from v8.9 and is optional 342 from v8.8. This flag can take the values of 0 to 2, to align with the 343 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 344 345- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 346 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 347 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 348 and upwards. This flag can take the values 0 to 2, to align with the 349 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 350 351- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 352 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 353 Physical Offset register) during EL2 to EL3 context save/restore operations. 354 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 355 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 356 mechanism. Default value is ``0``. 357 358- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point 359 Mode Register feature, allowing access to the FPMR register. FPMR register 360 controls the behaviors of FP8 instructions. It is an optional architectural 361 feature from v9.2 and upwards. This flag can take value of 0 to 2, to align 362 with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 363 364- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 365 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 366 Read Trap Register) during EL2 to EL3 context save/restore operations. 367 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 368 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 369 mechanism. Default value is ``0``. 370 371- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 372 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 373 during EL2 to EL3 context save/restore operations. 374 Its an optional architectural feature and is available from v8.8 and upwards. 375 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 376 mechanism. Default value is ``0``. 377 378- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 379 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 380 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 381 mandatory architectural feature and is enabled from v8.7 and upwards. This 382 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 383 mechanism. Default value is ``0``. 384 385- ``ENABLE_FEAT_MOPS``: Numeric value to enable FEAT_MOPS (Standardization 386 of memory operations) when INIT_UNUSED_NS_EL2=1. 387 This feature is mandatory from v8.8 and enabling of FEAT_MOPS does not 388 require any settings from EL3 as the controls are present in EL2 registers 389 (HCRX_EL2.{MSCEn,MCE2} and SCTLR_EL2.MSCEn) and in most configurations 390 we expect EL2 to be present. But in case of INIT_UNUSED_NS_EL2=1 , 391 EL3 should configure the EL2 registers. This flag 392 can take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 393 Default value is ``0``. 394 395- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 396 if the platform wants to use this feature and MTE2 is enabled at ELX. 397 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 398 mechanism. Default value is ``0``. 399 400- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 401 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 402 permission fault for any privileged data access from EL1/EL2 to virtual 403 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 404 mandatory architectural feature and is enabled from v8.1 and upwards. This 405 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 406 mechanism. Default value is ``0``. 407 408- ``ENABLE_FEAT_PAUTH_LR``: Numeric value to enable the ``FEAT_PAUTH_LR`` 409 extension. ``FEAT_PAUTH_LR`` is an optional feature available from Arm v9.4 410 onwards. This feature requires PAUTH to be enabled via the 411 ``BRANCH_PROTECTION`` flag. This flag can take the values 0 to 2, to align 412 with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 413 414- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 415 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 416 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 417 mechanism. Default value is ``0``. 418 419- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 420 extension. This feature is only supported in AArch64 state. This flag can 421 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 422 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 423 Armv8.5 onwards. 424 425- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 426 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 427 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 428 later CPUs. It is enabled from v8.5 and upwards and if needed can be 429 overidden from platforms explicitly. 430 431- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 432 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 433 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 434 mechanism. Default is ``0``. 435 436- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 437 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 438 available on Arm v8.6. This flag can take values 0 to 2, to align with the 439 ``ENABLE_FEAT`` mechanism. Default is ``0``. 440 441 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 442 delayed by the amount of value in ``TWED_DELAY``. 443 444- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 445 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 446 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 447 architectural feature and is enabled from v8.1 and upwards. It can take 448 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 449 Default value is ``0``. 450 451- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 452 allow access to TCR2_EL2 (extended translation control) from EL2 as 453 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 454 mandatory architectural feature and is enabled from v8.9 and upwards. This 455 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 456 mechanism. Default value is ``0``. 457 458- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 459 at EL2 and below, and context switch relevant registers. This flag 460 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 461 mechanism. Default value is ``0``. 462 463- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 464 at EL2 and below, and context switch relevant registers. This flag 465 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 466 mechanism. Default value is ``0``. 467 468- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 469 at EL2 and below, and context switch relevant registers. This flag 470 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 471 mechanism. Default value is ``0``. 472 473- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 474 at EL2 and below, and context switch relevant registers. This flag 475 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 476 mechanism. Default value is ``0``. 477 478- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 479 allow use of Guarded Control Stack from EL2 as well as adding the GCS 480 registers to the EL2 context save/restore operations. This flag can take 481 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 482 Default value is ``0``. 483 484 - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU 485 interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually 486 exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported. 487 Default value is ``0``. 488 489- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE 490 (Translation Hardening Extension) at EL2 and below, setting the bit 491 SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1 492 registers and context switch them. 493 Its an optional architectural feature and is available from v8.8 and upwards. 494 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 495 mechanism. Default value is ``0``. 496 497- ``ENABLE_FEAT_SCTLR2``: Numeric value to enable support for FEAT_SCTLR2 498 (Extension to SCTLR_ELx) at EL2 and below, setting the bit 499 SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and 500 context switch them. This feature is OPTIONAL from Armv8.0 implementations 501 and mandatory in Armv8.9 implementations. 502 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 503 mechanism. Default value is ``0``. 504 505- ``ENABLE_FEAT_D128``: Numeric value to enable support for FEAT_D128 506 at EL2 and below, setting the bit SCT_EL3.D128En in EL3 to allow access to 507 128 bit version of system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, 508 TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and 509 RCWSMASK_EL1. Its an optional architectural feature and is available from 510 9.3 and upwards. 511 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 512 mechanism. Default value is ``0``. 513 514- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 515 support in GCC for TF-A. This option is currently only supported for 516 AArch64. Default is 0. 517 518- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 519 feature. MPAM is an optional Armv8.4 extension that enables various memory 520 system components and resources to define partitions; software running at 521 various ELs can assign themselves to desired partition to control their 522 performance aspects. 523 524 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 525 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 526 access their own MPAM registers without trapping into EL3. This option 527 doesn't make use of partitioning in EL3, however. Platform initialisation 528 code should configure and use partitions in EL3 as required. This option 529 defaults to ``2`` since MPAM is enabled by default for NS world only. 530 The flag is automatically disabled when the target 531 architecture is AArch32. 532 533- ``ENABLE_FEAT_LS64_ACCDATA``: Numeric value to enable access and save and 534 restore the ACCDATA_EL1 system register, at EL2 and below. This flag can 535 take the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 536 Default value is ``0``. 537 538- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 539 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 540 firmware to detect and limit high activity events to assist in SoC processor 541 power domain dynamic power budgeting and limit the triggering of whole-rail 542 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 543 544 - ``FEAT_PABANDON``: Boolean option to enable support for powerdown abandon on 545 Arm cores that support it (currently Gelas and Travis). Extends the PSCI 546 implementation to expect waking up after the terminal ``wfi``. Currently, 547 introduces a performance penalty. Once this is removed, this option will be 548 removed and the feature will be enabled by default. Defaults to ``0``. 549 550- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 551 support within generic code in TF-A. This option is currently only supported 552 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 553 in BL32 (SP_min) for AARCH32. Default is 0. 554 555- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 556 Measurement Framework(PMF). Default is 0. 557 558- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 559 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 560 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 561 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 562 software. 563 564- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 565 instrumentation which injects timestamp collection points into TF-A to 566 allow runtime performance to be measured. Currently, only PSCI is 567 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 568 as well. Default is 0. 569 570- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 571 extensions. This is an optional architectural feature for AArch64. 572 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 573 mechanism. The default is 2 but is automatically disabled when the target 574 architecture is AArch32. 575 576- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 577 (SVE) for the Non-secure world only. SVE is an optional architectural feature 578 for AArch64. This flag can take the values 0 to 2, to align with the 579 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be used on 580 systems that have SPM_MM enabled. The default value is 2. 581 582 Note that when SVE is enabled for the Non-secure world, access 583 to SVE, SIMD and floating-point functionality from the Secure world is 584 independently controlled by build option ``ENABLE_SVE_FOR_SWD``. When enabling 585 ``CTX_INCLUDE_FPREGS`` and ``ENABLE_SVE_FOR_NS`` together, it is mandatory to 586 enable ``CTX_INCLUDE_SVE_REGS``. This is to avoid corruption of the Non-secure 587 world data in the Z-registers which are aliased by the SIMD and FP registers. 588 589- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE and FPU/SIMD functionality 590 for the Secure world. SVE is an optional architectural feature for AArch64. 591 The default is 0 and it is automatically disabled when the target architecture 592 is AArch32. 593 594 .. note:: 595 This build flag requires ``ENABLE_SVE_FOR_NS`` to be enabled. When enabling 596 ``ENABLE_SVE_FOR_SWD``, a developer must carefully consider whether 597 ``CTX_INCLUDE_SVE_REGS`` is also needed. 598 599- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 600 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 601 default value is set to "none". "strong" is the recommended stack protection 602 level if this feature is desired. "none" disables the stack protection. For 603 all values other than "none", the ``plat_get_stack_protector_canary()`` 604 platform hook needs to be implemented. The value is passed as the last 605 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 606 607- ``ENABLE_ERRATA_ALL``: This option is used only for testing purposes, Boolean 608 option to enable the workarounds for all errata that TF-A implements. Normally 609 they should be explicitly enabled depending on each platform's needs. Not 610 recommended for release builds. This option is default set to 0. 611 612- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 613 flag depends on ``DECRYPTION_SUPPORT`` build flag. 614 615- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 616 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 617 618- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 619 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 620 on ``DECRYPTION_SUPPORT`` build flag. 621 622- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 623 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 624 build flag. 625 626- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 627 deprecated platform APIs, helper functions or drivers within Trusted 628 Firmware as error. It can take the value 1 (flag the use of deprecated 629 APIs as error) or 0. The default is 0. 630 631- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 632 configure an Arm® Ethos™-N NPU. To use this service the target platform's 633 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 634 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 635 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 636 637- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 638 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 639 ``TRUSTED_BOARD_BOOT`` to be enabled. 640 641- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 642 (```ethosn.bin```). This firmware image will be included in the FIP and 643 loaded at runtime. 644 645- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 646 targeted at EL3. When set ``0`` (default), no exceptions are expected or 647 handled at EL3, and a panic will result. The exception to this rule is when 648 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 649 occuring during normal world execution, are trapped to EL3. Any exception 650 trapped during secure world execution are trapped to the SPMC. This is 651 supported only for AArch64 builds. 652 653- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 654 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 655 Default value is 40 (LOG_LEVEL_INFO). 656 657- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 658 injection from lower ELs, and this build option enables lower ELs to use 659 Error Records accessed via System Registers to inject faults. This is 660 applicable only to AArch64 builds. 661 662 This feature is intended for testing purposes only, and is advisable to keep 663 disabled for production images. 664 665- ``FIP_NAME``: This is an optional build option which specifies the FIP 666 filename for the ``fip`` target. Default is ``fip.bin``. 667 668- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 669 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 670 671- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 672 673 :: 674 675 0: Encryption is done with Secret Symmetric Key (SSK) which is common 676 for a class of devices. 677 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 678 unique per device. 679 680 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 681 682- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 683 tool to create certificates as per the Chain of Trust described in 684 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 685 include the certificates in the FIP and FWU_FIP. Default value is '0'. 686 687 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 688 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 689 the corresponding certificates, and to include those certificates in the 690 FIP and FWU_FIP. 691 692 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 693 images will not include support for Trusted Board Boot. The FIP will still 694 include the corresponding certificates. This FIP can be used to verify the 695 Chain of Trust on the host machine through other mechanisms. 696 697 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 698 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 699 will not include the corresponding certificates, causing a boot failure. 700 701- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 702 inherent support for specific EL3 type interrupts. Setting this build option 703 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 704 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 705 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 706 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 707 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 708 the Secure Payload interrupts needs to be synchronously handed over to Secure 709 EL1 for handling. The default value of this option is ``0``, which means the 710 Group 0 interrupts are assumed to be handled by Secure EL1. 711 712- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 713 Interrupts, resulting from errors in NS world, will be always trapped in 714 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 715 will be trapped in the current exception level (or in EL1 if the current 716 exception level is EL0). 717 718- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 719 software operations are required for CPUs to enter and exit coherency. 720 However, newer systems exist where CPUs' entry to and exit from coherency 721 is managed in hardware. Such systems require software to only initiate these 722 operations, and the rest is managed in hardware, minimizing active software 723 management. In such systems, this boolean option enables TF-A to carry out 724 build and run-time optimizations during boot and power management operations. 725 This option defaults to 0 and if it is enabled, then it implies 726 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 727 728 If this flag is disabled while the platform which TF-A is compiled for 729 includes cores that manage coherency in hardware, then a compilation error is 730 generated. This is based on the fact that a system cannot have, at the same 731 time, cores that manage coherency in hardware and cores that don't. In other 732 words, a platform cannot have, at the same time, cores that require 733 ``HW_ASSISTED_COHERENCY=1`` and cores that require 734 ``HW_ASSISTED_COHERENCY=0``. 735 736 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 737 translation library (xlat tables v2) must be used; version 1 of translation 738 library is not supported. 739 740- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 741 implementation defined system register accesses from lower ELs. Default 742 value is ``0``. 743 744- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 745 bottom, higher addresses at the top. This build flag can be set to '1' to 746 invert this behavior. Lower addresses will be printed at the top and higher 747 addresses at the bottom. 748 749- ``INIT_UNUSED_NS_EL2``: This build flag guards code that disables EL2 750 safely in scenario where NS-EL2 is present but unused. This flag is set to 0 751 by default. Platforms without NS-EL2 in use must enable this flag. 752 753- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 754 used for generating the PKCS keys and subsequent signing of the certificate. 755 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 756 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 757 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 758 compatibility. The default value of this flag is ``rsa`` which is the TBBR 759 compliant PKCS#1 RSA 2.1 scheme. 760 761- ``KEY_SIZE``: This build flag enables the user to select the key size for 762 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 763 depend on the chosen algorithm and the cryptographic module. 764 765 +---------------------------+------------------------------------+ 766 | KEY_ALG | Possible key sizes | 767 +===========================+====================================+ 768 | rsa | 1024 , 2048 (default), 3072, 4096 | 769 +---------------------------+------------------------------------+ 770 | ecdsa | 256 (default), 384 | 771 +---------------------------+------------------------------------+ 772 | ecdsa-brainpool-regular | 256 (default) | 773 +---------------------------+------------------------------------+ 774 | ecdsa-brainpool-twisted | 256 (default) | 775 +---------------------------+------------------------------------+ 776 777- ``HASH_ALG``: This build flag enables the user to select the secure hash 778 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 779 The default value of this flag is ``sha256``. 780 781- ``LDFLAGS``: Extra user options appended to the linkers' command line in 782 addition to the one set by the build system. 783 784- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 785 output compiled into the build. This should be one of the following: 786 787 :: 788 789 0 (LOG_LEVEL_NONE) 790 10 (LOG_LEVEL_ERROR) 791 20 (LOG_LEVEL_NOTICE) 792 30 (LOG_LEVEL_WARNING) 793 40 (LOG_LEVEL_INFO) 794 50 (LOG_LEVEL_VERBOSE) 795 796 All log output up to and including the selected log level is compiled into 797 the build. The default value is 40 in debug builds and 20 in release builds. 798 799- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 800 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 801 provide trust that the code taking the measurements and recording them has 802 not been tampered with. 803 804 This option defaults to 0. 805 806- ``DISCRETE_TPM``: Boolean flag to include support for a Discrete TPM. 807 808 This option defaults to 0. 809 810- ``TPM_INTERFACE``: When ``DISCRETE_TPM=1``, this is a required flag to 811 select the TPM interface. Currently only one interface is supported: 812 813 :: 814 815 FIFO_SPI 816 817- ``MBOOT_TPM_HASH_ALG``: Build flag to select the TPM hash algorithm used during 818 Measured Boot. Currently only accepts ``sha256`` as a valid algorithm. 819 820- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 821 options to the compiler. An example usage: 822 823 .. code:: make 824 825 MARCH_DIRECTIVE := -march=armv8.5-a 826 827- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 828 options to the compiler currently supporting only of the options. 829 GCC documentation: 830 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 831 832 An example usage: 833 834 .. code:: make 835 836 HARDEN_SLS := 1 837 838 This option defaults to 0. 839 840- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 841 specifies a file that contains the Non-Trusted World private key in PEM 842 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 843 will be used to save the key. 844 845- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 846 optional. It is only needed if the platform makefile specifies that it 847 is required in order to build the ``fwu_fip`` target. 848 849- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 850 contents upon world switch. It can take either 0 (don't save and restore) or 851 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 852 wants the timer registers to be saved and restored. 853 854- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 855 for the BL image. It can be either 0 (include) or 1 (remove). The default 856 value is 0. 857 858- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 859 the underlying hardware is not a full PL011 UART but a minimally compliant 860 generic UART, which is a subset of the PL011. The driver will not access 861 any register that is not part of the SBSA generic UART specification. 862 Default value is 0 (a full PL011 compliant UART is present). 863 864- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 865 must be subdirectory of any depth under ``plat/``, and must contain a 866 platform makefile named ``platform.mk``. For example, to build TF-A for the 867 Arm Juno board, select PLAT=juno. 868 869- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 870 each core as well as the global context. The data includes the memory used 871 by each world and each privileged exception level. This build option is 872 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 873 874- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 875 instead of the normal boot flow. When defined, it must specify the entry 876 point address for the preloaded BL33 image. This option is incompatible with 877 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 878 over ``PRELOADED_BL33_BASE``. 879 880- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 881 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 882 registers when the cluster goes through a power cycle. This is disabled by 883 default and platforms that require this feature have to enable them. 884 885- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 886 vector address can be programmed or is fixed on the platform. It can take 887 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 888 programmable reset address, it is expected that a CPU will start executing 889 code directly at the right address, both on a cold and warm reset. In this 890 case, there is no need to identify the entrypoint on boot and the boot path 891 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 892 does not need to be implemented in this case. 893 894- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 895 possible for the PSCI power-state parameter: original and extended State-ID 896 formats. This flag if set to 1, configures the generic PSCI layer to use the 897 extended format. The default value of this flag is 0, which means by default 898 the original power-state format is used by the PSCI implementation. This flag 899 should be specified by the platform makefile and it governs the return value 900 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 901 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 902 set to 1 as well. 903 904- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 905 OS-initiated mode. This option defaults to 0. 906 907- ``ARCH_FEATURE_AVAILABILITY``: Boolean flag to enable support for the 908 optional SMCCC_ARCH_FEATURE_AVAILABILITY call. This option implicitly 909 interacts with IMPDEF_SYSREG_TRAP and software emulation. This option 910 defaults to 0. 911 912- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 913 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 914 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 915 NOTE: This flag enables use of IESB capability to reduce entry latency into 916 EL3 even when RAS error handling is not performed on the platform. Hence this 917 flag is recommended to be turned on Armv8.2 and later CPUs. 918 919- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 920 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 921 entrypoint) or 1 (CPU reset to BL31 entrypoint). 922 The default value is 0. 923 924- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 925 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 926 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 927 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 928 929- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 930- blocks) covered by a single bit of the bitlock structure during RME GPT 931- operations. The lower the block size, the better opportunity for 932- parallelising GPT operations but at the cost of more bits being needed 933- for the bitlock structure. This numeric parameter can take the values 934- from 0 to 512 and must be a power of 2. The value of 0 is special and 935- and it chooses a single spinlock for all GPT L1 table entries. Default 936- value is 1 which corresponds to block size of 512MB per bit of bitlock 937- structure. 938 939- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 940 supported contiguous blocks in GPT Library. This parameter can take the 941 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 942 descriptors. Default value is 512. 943 944- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 945 file that contains the ROT private key in PEM format or a PKCS11 URI and 946 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 947 accepted and it will be used to save the key. 948 949- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 950 certificate generation tool to save the keys used to establish the Chain of 951 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 952 953- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 954 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 955 target. 956 957- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 958 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 959 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 960 961- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 962 optional. It is only needed if the platform makefile specifies that it 963 is required in order to build the ``fwu_fip`` target. 964 965- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 966 Delegated Exception Interface to BL31 image. This defaults to ``0``. 967 968 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 969 set to ``1``. 970 971- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 972 isolated on separate memory pages. This is a trade-off between security and 973 memory usage. See "Isolating code and read-only data on separate memory 974 pages" section in :ref:`Firmware Design`. This flag is disabled by default 975 and affects all BL images. 976 977- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 978 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 979 allocated in RAM discontiguous from the loaded firmware image. When set, the 980 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 981 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 982 sections are placed in RAM immediately following the loaded firmware image. 983 984- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 985 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 986 discontiguous from loaded firmware images. When set, the platform need to 987 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 988 flag is disabled by default and NOLOAD sections are placed in RAM immediately 989 following the loaded firmware image. 990 991- ``SEPARATE_SIMD_SECTION``: Setting this option to ``1`` allows the SIMD context 992 data structures to be put in a dedicated memory region as decided by platform 993 integrator. Default value is ``0`` which means the SIMD context is put in BSS 994 section of EL3 firmware. 995 996- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 997 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 998 UEFI+ACPI this can provide a certain amount of OS forward compatibility 999 with newer platforms that aren't ECAM compliant. 1000 1001- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 1002 This build option is only valid if ``ARCH=aarch64``. The value should be 1003 the path to the directory containing the SPD source, relative to 1004 ``services/spd/``; the directory is expected to contain a makefile called 1005 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 1006 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 1007 cannot be enabled when the ``SPM_MM`` option is enabled. 1008 1009- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 1010 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 1011 execution in BL1 just before handing over to BL31. At this point, all 1012 firmware images have been loaded in memory, and the MMU and caches are 1013 turned off. Refer to the "Debugging options" section for more details. 1014 1015- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 1016 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1017 component runs at the EL3 exception level. The default value is ``0`` ( 1018 disabled). This configuration supports pre-Armv8.4 platforms (aka not 1019 implementing the ``FEAT_SEL2`` extension). 1020 1021- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 1022 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 1023 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 1024 1025- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 1026 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 1027 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 1028 mechanism should be used. 1029 1030- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 1031 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1032 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 1033 extension. This is the default when enabling the SPM Dispatcher. When 1034 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 1035 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 1036 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 1037 extension). 1038 1039- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 1040 Partition Manager (SPM) implementation. The default value is ``0`` 1041 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 1042 enabled (``SPD=spmd``). 1043 1044- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 1045 description of secure partitions. The build system will parse this file and 1046 package all secure partition blobs into the FIP. This file is not 1047 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 1048 1049- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 1050 secure interrupts (caught through the FIQ line). Platforms can enable 1051 this directive if they need to handle such interruption. When enabled, 1052 the FIQ are handled in monitor mode and non secure world is not allowed 1053 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 1054 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 1055 1056- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 1057 Platforms can configure this if they need to lower the hardware 1058 limit, for example due to asymmetric configuration or limitations of 1059 software run at lower ELs. The default is the architectural maximum 1060 of 2048 which should be suitable for most configurations, the 1061 hardware will limit the effective VL to the maximum physically supported 1062 VL. 1063 1064- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 1065 Random Number Generator Interface to BL31 image. This defaults to ``0``. 1066 1067- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 1068 Boot feature. When set to '1', BL1 and BL2 images include support to load 1069 and verify the certificates and images in a FIP, and BL1 includes support 1070 for the Firmware Update. The default value is '0'. Generation and inclusion 1071 of certificates in the FIP and FWU_FIP depends upon the value of the 1072 ``GENERATE_COT`` option. 1073 1074 .. warning:: 1075 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 1076 already exist in disk, they will be overwritten without further notice. 1077 1078- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 1079 specifies a file that contains the Trusted World private key in PEM 1080 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 1081 it will be used to save the key. 1082 1083- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 1084 synchronous, (see "Initializing a BL32 Image" section in 1085 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 1086 synchronous method) or 1 (BL32 is initialized using asynchronous method). 1087 Default is 0. 1088 1089- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 1090 routing model which routes non-secure interrupts asynchronously from TSP 1091 to EL3 causing immediate preemption of TSP. The EL3 is responsible 1092 for saving and restoring the TSP context in this routing model. The 1093 default routing model (when the value is 0) is to route non-secure 1094 interrupts to TSP allowing it to save its context and hand over 1095 synchronously to EL3 via an SMC. 1096 1097 .. note:: 1098 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 1099 must also be set to ``1``. 1100 1101- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 1102 internal-trusted-storage) as SP in tb_fw_config device tree. 1103 1104- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1105 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1106 this delay. It can take values in the range (0-15). Default value is ``0`` 1107 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1108 Platforms need to explicitly update this value based on their requirements. 1109 1110- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1111 linker. When the ``LINKER`` build variable points to the armlink linker, 1112 this flag is enabled automatically. To enable support for armlink, platforms 1113 will have to provide a scatter file for the BL image. Currently, Tegra 1114 platforms use the armlink support to compile BL3-1 images. 1115 1116- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1117 memory region in the BL memory map or not (see "Use of Coherent memory in 1118 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1119 (Coherent memory region is included) or 0 (Coherent memory region is 1120 excluded). Default is 1. 1121 1122- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1123 firmware configuration framework. This will move the io_policies into a 1124 configuration device tree, instead of static structure in the code base. 1125 1126- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1127 at runtime using fconf. If this flag is enabled, COT descriptors are 1128 statically captured in tb_fw_config file in the form of device tree nodes 1129 and properties. Currently, COT descriptors used by BL2 are moved to the 1130 device tree and COT descriptors used by BL1 are retained in the code 1131 base statically. 1132 1133- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1134 runtime using firmware configuration framework. The platform specific SDEI 1135 shared and private events configuration is retrieved from device tree rather 1136 than static C structures at compile time. This is only supported if 1137 SDEI_SUPPORT build flag is enabled. 1138 1139- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1140 and Group1 secure interrupts using the firmware configuration framework. The 1141 platform specific secure interrupt property descriptor is retrieved from 1142 device tree in runtime rather than depending on static C structure at compile 1143 time. 1144 1145- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1146 This feature creates a library of functions to be placed in ROM and thus 1147 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1148 is 0. 1149 1150- ``V``: Verbose build. If assigned anything other than 0, the build commands 1151 are printed. Default is 0. 1152 1153- ``VERSION_STRING``: String used in the log output for each TF-A image. 1154 Defaults to a string formed by concatenating the version number, build type 1155 and build string. 1156 1157- ``W``: Warning level. Some compiler warning options of interest have been 1158 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1159 each level enabling more warning options. Default is 0. 1160 1161 This option is closely related to the ``E`` option, which enables 1162 ``-Werror``. 1163 1164 - ``W=0`` (default) 1165 1166 Enables a wide assortment of warnings, most notably ``-Wall`` and 1167 ``-Wextra``, as well as various bad practices and things that are likely to 1168 result in errors. Includes some compiler specific flags. No warnings are 1169 expected at this level for any build. 1170 1171 - ``W=1`` 1172 1173 Enables warnings we want the generic build to include but are too time 1174 consuming to fix at the moment. It re-enables warnings taken out for 1175 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1176 to eventually be merged into ``W=0``. Some warnings are expected on some 1177 builds, but new contributions should not introduce new ones. 1178 1179 - ``W=2`` (recommended) 1180 1181 Enables warnings we want the generic build to include but cannot be enabled 1182 due to external libraries. This level is expected to eventually be merged 1183 into ``W=0``. Lots of warnings are expected, primarily from external 1184 libraries like zlib and compiler-rt, but new controbutions should not 1185 introduce new ones. 1186 1187 - ``W=3`` 1188 1189 Enables warnings that are informative but not necessary and generally too 1190 verbose and frequently ignored. A very large number of warnings are 1191 expected. 1192 1193 The exact set of warning flags depends on the compiler and TF-A warning 1194 level, however they are all succinctly set in the top-level Makefile. Please 1195 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1196 individual flags. 1197 1198- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1199 the CPU after warm boot. This is applicable for platforms which do not 1200 require interconnect programming to enable cache coherency (eg: single 1201 cluster platforms). If this option is enabled, then warm boot path 1202 enables D-caches immediately after enabling MMU. This option defaults to 0. 1203 1204- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1205 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1206 The default value of this flag is ``0``. 1207 1208 ``AT`` speculative errata workaround disables stage1 page table walk for 1209 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1210 produces either the correct result or failure without TLB allocation. 1211 1212 This boolean option enables errata for all below CPUs. 1213 1214 +---------+--------------+-------------------------+ 1215 | Errata | CPU | Workaround Define | 1216 +=========+==============+=========================+ 1217 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1218 +---------+--------------+-------------------------+ 1219 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1220 +---------+--------------+-------------------------+ 1221 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1222 +---------+--------------+-------------------------+ 1223 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1224 +---------+--------------+-------------------------+ 1225 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1226 +---------+--------------+-------------------------+ 1227 1228 .. note:: 1229 This option is enabled by build only if platform sets any of above defines 1230 mentioned in ’Workaround Define' column in the table. 1231 If this option is enabled for the EL3 software then EL2 software also must 1232 implement this workaround due to the behaviour of the errata mentioned 1233 in new SDEN document which will get published soon. 1234 1235- ``ERRATA_SME_POWER_DOWN``: Boolean option to disable SME (PSTATE.{ZA,SM}=0) 1236 before power down and downgrade a suspend to power down request to a normal 1237 suspend request. This is necessary when software running at lower ELs requests 1238 power down without first clearing these bits. On affected cores, the CME 1239 connected to it will reject its power down request. The default value is 0. 1240 1241- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1242 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1243 This flag is disabled by default. 1244 1245- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1246 host machine where a custom installation of OpenSSL is located, which is used 1247 to build the certificate generation, firmware encryption and FIP tools. If 1248 this option is not set, the default OS installation will be used. 1249 1250- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1251 functions that wait for an arbitrary time length (udelay and mdelay). The 1252 default value is 0. 1253 1254- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1255 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1256 optional architectural feature for AArch64. This flag can take the values 1257 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1258 and it is automatically disabled when the target architecture is AArch32. 1259 1260- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1261 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1262 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1263 feature for AArch64. This flag can take the values 0 to 2, to align with the 1264 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1265 disabled when the target architecture is AArch32. 1266 1267- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1268 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1269 but unused). This feature is available if trace unit such as ETMv4.x, and 1270 ETE(extending ETM feature) is implemented. This flag can take the values 1271 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1272 1273- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1274 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1275 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1276 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1277 1278- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1279 ``plat_can_cmo`` which will return zero if cache management operations should 1280 be skipped and non-zero otherwise. By default, this option is disabled which 1281 means platform hook won't be checked and CMOs will always be performed when 1282 related functions are called. 1283 1284- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1285 firmware interface for the BL31 image. By default its disabled (``0``). 1286 1287- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1288 errata mitigation for platforms with a non-arm interconnect using the errata 1289 ABI. By default its disabled (``0``). 1290 1291- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1292 driver(s). By default it is disabled (``0``) because it constitutes an attack 1293 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1294 This option should only be enabled on a need basis if there is a use case for 1295 reading characters from the console. 1296 1297GIC driver options 1298-------------------- 1299 1300The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is 1301a numeric option that can take the following values: 1302 1303 - ``0``: generic GIC driver not enabled. Any support is entirely in platform 1304 code. Strongly discouraged for GIC based interrupt controllers. 1305 1306 - ``1``: enable the use of the generic GIC driver but do not include any files 1307 or function definitions. It is then the platform's responsibility to provide 1308 these. This is useful if the platform either has a custom GIC implementation 1309 or an alternative interrupt controller design. Use of this option is strongly 1310 discouraged for standard GIC implementations. 1311 1312 - ``2``: use the GICv2 driver 1313 1314 - ``3``: use the GICv3 driver. See the next section on how to further configure 1315 it. Use this option for GICv4 implementations. 1316 - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``. 1317 1318 For GIC driver versions other than ``1``, deciding when to save and restore GIC 1319 context on a power domain state transition, as well as any GIC actions outside 1320 of the PSCI library's visibility are the platform's responsibility. The driver 1321 provides implementations of all necessary subroutines, they only need to be 1322 called as appropriate. 1323 1324GICv3 driver options 1325~~~~~~~~~~~~~~~~~~~~ 1326 1327``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The 1328old (deprecated) way of included them is using the directive: 1329``include drivers/arm/gic/v3/gicv3.mk`` 1330 1331The driver can be configured with the following options set in the platform 1332makefile: 1333 1334- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1335 Enabling this option will add runtime detection support for the 1336 GIC-600, so is safe to select even for a GIC500 implementation. 1337 This option defaults to 0. 1338 1339- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1340 for GIC-600 AE. Enabling this option will introduce support to initialize 1341 the FMU. Platforms should call the init function during boot to enable the 1342 FMU and its safety mechanisms. This option defaults to 0. 1343 1344- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1345 functionality. This option defaults to 0 1346 1347- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1348 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1349 functions. This is required for FVP platform which need to simulate GIC save 1350 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1351 1352- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1353 This option defaults to 0. 1354 1355- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1356 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1357 1358Debugging options 1359----------------- 1360 1361To compile a debug version and make the build more verbose use 1362 1363.. code:: shell 1364 1365 make PLAT=<platform> DEBUG=1 V=1 all 1366 1367AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1368(for example Arm-DS) might not support this and may need an older version of 1369DWARF symbols to be emitted by GCC. This can be achieved by using the 1370``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1371the version to 4 is recommended for Arm-DS. 1372 1373When debugging logic problems it might also be useful to disable all compiler 1374optimizations by using ``-O0``. 1375 1376.. warning:: 1377 Using ``-O0`` could cause output images to be larger and base addresses 1378 might need to be recalculated (see the **Memory layout on Arm development 1379 platforms** section in the :ref:`Firmware Design`). 1380 1381Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1382``LDFLAGS``: 1383 1384.. code:: shell 1385 1386 CFLAGS='-O0 -gdwarf-2' \ 1387 make PLAT=<platform> DEBUG=1 V=1 all 1388 1389Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1390ignored as the linker is called directly. 1391 1392It is also possible to introduce an infinite loop to help in debugging the 1393post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1394``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1395section. In this case, the developer may take control of the target using a 1396debugger when indicated by the console output. When using Arm-DS, the following 1397commands can be used: 1398 1399:: 1400 1401 # Stop target execution 1402 interrupt 1403 1404 # 1405 # Prepare your debugging environment, e.g. set breakpoints 1406 # 1407 1408 # Jump over the debug loop 1409 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1410 1411 # Resume execution 1412 continue 1413 1414.. _build_options_experimental: 1415 1416Experimental build options 1417--------------------------- 1418 1419Common build options 1420~~~~~~~~~~~~~~~~~~~~ 1421 1422- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1423 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1424 set to ``1`` then measurements and additional metadata collected during the 1425 measured boot process are sent to the DICE Protection Environment for storage 1426 and processing. A certificate chain, which represents the boot state of the 1427 device, can be queried from the DPE. 1428 1429- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1430 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1431 the measurements and recording them as per `PSA DRTM specification`_. For 1432 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1433 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1434 should have mechanism to authenticate BL31. This option defaults to 0. 1435 1436- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1437 Management Extension. This flag can take the values 0 to 2, to align with 1438 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1439 1440- ``ENABLE_FEAT_MEC``: Numeric value to enable support for the ARMv9.2 Memory 1441 Encryption Contexts (MEC). This flag can take the values 0 to 2, to align 1442 with the ``ENABLE_FEAT`` mechanism. MEC supports multiple encryption 1443 contexts for Realm security state and only one encryption context for the 1444 rest of the security states. Default value is 0. 1445 1446- ``RMMD_ENABLE_EL3_TOKEN_SIGN``: Numeric value to enable support for singing 1447 realm attestation token signing requests in EL3. This flag can take the 1448 values 0 and 1. The default value is ``0``. When set to ``1``, this option 1449 enables additional RMMD SMCs to push and pop requests for signing to 1450 EL3 along with platform hooks that must be implemented to service those 1451 requests and responses. 1452 1453- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1454 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1455 registers so are enabled together. Using this option without 1456 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1457 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1458 superset of SVE. SME is an optional architectural feature for AArch64. 1459 At this time, this build option cannot be used on systems that have 1460 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1461 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1462 mechanism. Default is 0. 1463 1464- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1465 version 2 (SME2) for the non-secure world only. SME2 is an optional 1466 architectural feature for AArch64. 1467 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1468 accesses will still be trapped. This flag can take the values 0 to 2, to 1469 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1470 1471- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1472 Extension for secure world. Used along with SVE and FPU/SIMD. 1473 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1474 Default is 0. 1475 1476- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1477 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1478 for logical partitions in EL3, managed by the SPMD as defined in the 1479 FF-A v1.2 specification. This flag is disabled by default. This flag 1480 must not be used if ``SPMC_AT_EL3`` is enabled. 1481 1482- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1483 verification mechanism. This is a debug feature that compares the 1484 architectural features enabled through the feature specific build flags 1485 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1486 and reports any discrepancies. 1487 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1488 1489 It is expected that this feature is only used for flexible platforms like 1490 software emulators, or for hardware platforms at bringup time, to verify 1491 that the configured feature set matches the CPU. 1492 The ``FEATURE_DETECTION`` macro is disabled by default. 1493 1494- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1495 The platform will use PSA compliant Crypto APIs during authentication and 1496 image measurement process by enabling this option. It uses APIs defined as 1497 per the `PSA Crypto API specification`_. This feature is only supported if 1498 using MbedTLS 3.x version. It is disabled (``0``) by default. 1499 1500- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1501 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1502 This defaults to ``0``. Current implementation follows the Firmware Handoff 1503 specification v0.9. 1504 1505- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1506 interface through BL31 as a SiP SMC function. 1507 Default is disabled (0). 1508 1509- ``HOB_LIST``: Setting this to ``1`` enables support for passing boot 1510 information using HOB defined in `Platform Initialization specification`_. 1511 This defaults to ``0``. 1512 1513- ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC 1514 handler code to handle SMC calls from the Architecture Compliance Suite. The 1515 handler is intentionally empty to reserve the SMC section and allow 1516 project-specific implementations in future ACS use cases. 1517 1518Firmware update options 1519~~~~~~~~~~~~~~~~~~~~~~~ 1520 1521- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1522 `PSA FW update specification`_. The default value is 0. 1523 PSA firmware update implementation has few limitations, such as: 1524 1525 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1526 be updated, then it should be done through another platform-defined 1527 mechanism. 1528 1529 - It assumes the platform's hardware supports CRC32 instructions. 1530 1531- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1532 in defining the firmware update metadata structure. This flag is by default 1533 set to '2'. 1534 1535- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1536 firmware bank. Each firmware bank must have the same number of images as per 1537 the `PSA FW update specification`_. 1538 This flag is used in defining the firmware update metadata structure. This 1539 flag is by default set to '1'. 1540 1541- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1542 metadata contains image description. The default value is 1. 1543 1544 The version 2 of the FWU metadata allows for an opaque metadata 1545 structure where a platform can choose to not include the firmware 1546 store description in the metadata structure. This option indicates 1547 if the firmware store description, which provides information on 1548 the updatable images is part of the structure. 1549 1550-------------- 1551 1552*Copyright (c) 2019-2025, Arm Limited. All rights reserved.* 1553 1554.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1555.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1556.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1557.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1558.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1559.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1560.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1561.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html 1562