1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``RMM``: This is an optional build option used when ``ENABLE_RME`` is set. 103 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 104 is not specified, TF-A builds the TRP to load and run at R-EL2. 105 106- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 107 ``fip`` target in case TF-A BL2 is used. 108 109- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 110 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 111 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 112 113- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 114 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 115 If enabled, it is needed to use a compiler that supports the option 116 ``-mbranch-protection``. Selects the branch protection features to use: 117- 0: Default value turns off all types of branch protection 118- 1: Enables all types of branch protection features 119- 2: Return address signing to its standard level 120- 3: Extend the signing to include leaf functions 121- 4: Turn on branch target identification mechanism 122 123 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 124 and resulting PAuth/BTI features. 125 126 +-------+--------------+-------+-----+ 127 | Value | GCC option | PAuth | BTI | 128 +=======+==============+=======+=====+ 129 | 0 | none | N | N | 130 +-------+--------------+-------+-----+ 131 | 1 | standard | Y | Y | 132 +-------+--------------+-------+-----+ 133 | 2 | pac-ret | Y | N | 134 +-------+--------------+-------+-----+ 135 | 3 | pac-ret+leaf | Y | N | 136 +-------+--------------+-------+-----+ 137 | 4 | bti | N | Y | 138 +-------+--------------+-------+-----+ 139 140 This option defaults to 0. 141 Note that Pointer Authentication is enabled for Non-secure world 142 irrespective of the value of this option if the CPU supports it. 143 144- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 145 compilation of each build. It must be set to a C string (including quotes 146 where applicable). Defaults to a string that contains the time and date of 147 the compilation. 148 149- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 150 build to be uniquely identified. Defaults to the current git commit id. 151 152- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 153 154- ``CFLAGS``: Extra user options appended on the compiler's command line in 155 addition to the options set by the build system. 156 157- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 158 release several CPUs out of reset. It can take either 0 (several CPUs may be 159 brought up) or 1 (only one CPU will ever be brought up during cold reset). 160 Default is 0. If the platform always brings up a single CPU, there is no 161 need to distinguish between primary and secondary CPUs and the boot path can 162 be optimised. The ``plat_is_my_cpu_primary()`` and 163 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 164 to be implemented in this case. 165 166- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 167 Defaults to ``tbbr``. 168 169- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 170 register state when an unexpected exception occurs during execution of 171 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 172 this is only enabled for a debug build of the firmware. 173 174- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 175 certificate generation tool to create new keys in case no valid keys are 176 present or specified. Allowed options are '0' or '1'. Default is '1'. 177 178- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 179 the AArch32 system registers to be included when saving and restoring the 180 CPU context. The option must be set to 0 for AArch64-only platforms (that 181 is on hardware that does not implement AArch32, or at least not at EL1 and 182 higher ELs). Default value is 1. 183 184- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 185 registers to be included when saving and restoring the CPU context. Default 186 is 0. 187 188- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 189 Memory System Resource Partitioning and Monitoring (MPAM) 190 registers to be included when saving and restoring the CPU context. 191 Default is '0'. 192 193- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 194 registers to be saved/restored when entering/exiting an EL2 execution 195 context. This flag can take values 0 to 2, to align with the 196 ``ENABLE_FEAT`` mechanism. Default value is 0. 197 198- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 199 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 200 to be included when saving and restoring the CPU context as part of world 201 switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT`` 202 mechanism. Default value is 0. 203 204 Note that Pointer Authentication is enabled for Non-secure world irrespective 205 of the value of this flag if the CPU supports it. 206 207- ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the 208 SVE registers to be included when saving and restoring the CPU context. Note 209 that this build option requires ``ENABLE_SVE_FOR_SWD`` to be enabled. In 210 general, it is recommended to perform SVE context management in lower ELs 211 and skip in EL3 due to the additional cost of maintaining large data 212 structures to track the SVE state. Hence, the default value is 0. 213 214- ``DEBUG``: Chooses between a debug and release build. It can take either 0 215 (release) or 1 (debug) as values. 0 is the default. 216 217- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 218 authenticated decryption algorithm to be used to decrypt firmware/s during 219 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 220 this flag is ``none`` to disable firmware decryption which is an optional 221 feature as per TBBR. 222 223- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 224 of the binary image. If set to 1, then only the ELF image is built. 225 0 is the default. 226 227- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 228 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 229 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 230 mechanism. Default is ``0``. 231 232- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 233 Board Boot authentication at runtime. This option is meant to be enabled only 234 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 235 flag has to be enabled. 0 is the default. 236 237- ``E``: Boolean option to make warnings into errors. Default is 1. 238 239 When specifying higher warnings levels (``W=1`` and higher), this option 240 defaults to 0. This is done to encourage contributors to use them, as they 241 are expected to produce warnings that would otherwise fail the build. New 242 contributions are still expected to build with ``W=0`` and ``E=1`` (the 243 default). 244 245- ``EARLY_CONSOLE``: This option is used to enable early traces before default 246 console is properly setup. It introduces EARLY_* traces macros, that will 247 use the non-EARLY traces macros if the flag is enabled, or do nothing 248 otherwise. To use this feature, platforms will have to create the function 249 plat_setup_early_console(). 250 Default is 0 (disabled) 251 252- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 253 the normal boot flow. It must specify the entry point address of the EL3 254 payload. Please refer to the "Booting an EL3 payload" section for more 255 details. 256 257- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 258 (also known as group 1 counters). These are implementation-defined counters, 259 and as such require additional platform configuration. Default is 0. 260 261- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 262 allows platforms with auxiliary counters to describe them via the 263 ``HW_CONFIG`` device tree blob. Default is 0. 264 265- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 266 are compiled out. For debug builds, this option defaults to 1, and calls to 267 ``assert()`` are left in place. For release builds, this option defaults to 0 268 and calls to ``assert()`` function are compiled out. This option can be set 269 independently of ``DEBUG``. It can also be used to hide any auxiliary code 270 that is only required for the assertion and does not fit in the assertion 271 itself. 272 273- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 274 dumps or not. It is supported in both AArch64 and AArch32. However, in 275 AArch32 the format of the frame records are not defined in the AAPCS and they 276 are defined by the implementation. This implementation of backtrace only 277 supports the format used by GCC when T32 interworking is disabled. For this 278 reason enabling this option in AArch32 will force the compiler to only 279 generate A32 code. This option is enabled by default only in AArch64 debug 280 builds, but this behaviour can be overridden in each platform's Makefile or 281 in the build command line. 282 283- ``ENABLE_FEAT`` 284 The Arm architecture defines several architecture extension features, 285 named FEAT_xxx in the architecure manual. Some of those features require 286 setup code in higher exception levels, other features might be used by TF-A 287 code itself. 288 Most of the feature flags defined in the TF-A build system permit to take 289 the values 0, 1 or 2, with the following meaning: 290 291 :: 292 293 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 294 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 295 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 296 297 When setting the flag to 0, the feature is disabled during compilation, 298 and the compiler's optimisation stage and the linker will try to remove 299 as much of this code as possible. 300 If it is defined to 1, the code will use the feature unconditionally, so the 301 CPU is expected to support that feature. The FEATURE_DETECTION debug 302 feature, if enabled, will verify this. 303 If the feature flag is set to 2, support for the feature will be compiled 304 in, but its existence will be checked at runtime, so it works on CPUs with 305 or without the feature. This is mostly useful for platforms which either 306 support multiple different CPUs, or where the CPU is configured at runtime, 307 like in emulators. 308 309- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 310 extensions. This flag can take the values 0 to 2, to align with the 311 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 312 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 313 and this option can be used to enable this feature on those systems as well. 314 This flag can take the values 0 to 2, the default is 0. 315 316- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 317 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 318 onwards. This flag can take the values 0 to 2, to align with the 319 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 320 321- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 322 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 323 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 324 optional feature available on Arm v8.0 onwards. This flag can take values 325 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 326 Default value is ``0``. 327 328- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 329 extension. This feature is supported in AArch64 state only and is an optional 330 feature available in Arm v8.0 implementations. 331 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 332 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 333 mechanism. Default value is ``0``. 334 335- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 336 extension which allows the ability to implement more than 16 breakpoints 337 and/or watchpoints. This feature is mandatory from v8.9 and is optional 338 from v8.8. This flag can take the values of 0 to 2, to align with the 339 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 340 341- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 342 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 343 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 344 and upwards. This flag can take the values 0 to 2, to align with the 345 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 346 347- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 348 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 349 Physical Offset register) during EL2 to EL3 context save/restore operations. 350 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 351 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 352 mechanism. Default value is ``0``. 353 354- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point 355 Mode Register feature, allowing access to the FPMR register. FPMR register 356 controls the behaviors of FP8 instructions. It is an optional architectural 357 feature from v9.2 and upwards. This flag can take value of 0 to 2, to align 358 with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 359 360- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 361 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 362 Read Trap Register) during EL2 to EL3 context save/restore operations. 363 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 364 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 365 mechanism. Default value is ``0``. 366 367- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 368 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 369 during EL2 to EL3 context save/restore operations. 370 Its an optional architectural feature and is available from v8.8 and upwards. 371 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 372 mechanism. Default value is ``0``. 373 374- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 375 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 376 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 377 mandatory architectural feature and is enabled from v8.7 and upwards. This 378 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 379 mechanism. Default value is ``0``. 380 381- ``ENABLE_FEAT_MOPS``: Numeric value to enable FEAT_MOPS (Standardization 382 of memory operations) when INIT_UNUSED_NS_EL2=1. 383 This feature is mandatory from v8.8 and enabling of FEAT_MOPS does not 384 require any settings from EL3 as the controls are present in EL2 registers 385 (HCRX_EL2.{MSCEn,MCE2} and SCTLR_EL2.MSCEn) and in most configurations 386 we expect EL2 to be present. But in case of INIT_UNUSED_NS_EL2=1 , 387 EL3 should configure the EL2 registers. This flag 388 can take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 389 Default value is ``0``. 390 391- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 392 if the platform wants to use this feature and MTE2 is enabled at ELX. 393 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 394 mechanism. Default value is ``0``. 395 396- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 397 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 398 permission fault for any privileged data access from EL1/EL2 to virtual 399 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 400 mandatory architectural feature and is enabled from v8.1 and upwards. This 401 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 402 mechanism. Default value is ``0``. 403 404- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 405 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 406 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 407 mechanism. Default value is ``0``. 408 409- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 410 extension. This feature is only supported in AArch64 state. This flag can 411 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 412 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 413 Armv8.5 onwards. 414 415- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 416 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 417 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 418 later CPUs. It is enabled from v8.5 and upwards and if needed can be 419 overidden from platforms explicitly. 420 421- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 422 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 423 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 424 mechanism. Default is ``0``. 425 426- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 427 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 428 available on Arm v8.6. This flag can take values 0 to 2, to align with the 429 ``ENABLE_FEAT`` mechanism. Default is ``0``. 430 431 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 432 delayed by the amount of value in ``TWED_DELAY``. 433 434- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 435 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 436 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 437 architectural feature and is enabled from v8.1 and upwards. It can take 438 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 439 Default value is ``0``. 440 441- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 442 allow access to TCR2_EL2 (extended translation control) from EL2 as 443 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 444 mandatory architectural feature and is enabled from v8.9 and upwards. This 445 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 446 mechanism. Default value is ``0``. 447 448- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 449 at EL2 and below, and context switch relevant registers. This flag 450 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 451 mechanism. Default value is ``0``. 452 453- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 454 at EL2 and below, and context switch relevant registers. This flag 455 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 456 mechanism. Default value is ``0``. 457 458- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 459 at EL2 and below, and context switch relevant registers. This flag 460 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 461 mechanism. Default value is ``0``. 462 463- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 464 at EL2 and below, and context switch relevant registers. This flag 465 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 466 mechanism. Default value is ``0``. 467 468- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 469 allow use of Guarded Control Stack from EL2 as well as adding the GCS 470 registers to the EL2 context save/restore operations. This flag can take 471 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 472 Default value is ``0``. 473 474- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE 475 (Translation Hardening Extension) at EL2 and below, setting the bit 476 SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1 477 registers and context switch them. 478 Its an optional architectural feature and is available from v8.8 and upwards. 479 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 480 mechanism. Default value is ``0``. 481 482- ``ENABLE_FEAT_SCTLR2``: Numeric value to enable support for FEAT_SCTLR2 483 (Extension to SCTLR_ELx) at EL2 and below, setting the bit 484 SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and 485 context switch them. This feature is OPTIONAL from Armv8.0 implementations 486 and mandatory in Armv8.9 implementations. 487 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 488 mechanism. Default value is ``0``. 489 490- ``ENABLE_FEAT_D128``: Numeric value to enable support for FEAT_D128 491 at EL2 and below, setting the bit SCT_EL3.D128En in EL3 to allow access to 492 128 bit version of system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, 493 TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and 494 RCWSMASK_EL1. Its an optional architectural feature and is available from 495 9.3 and upwards. 496 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 497 mechanism. Default value is ``0``. 498 499- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 500 support in GCC for TF-A. This option is currently only supported for 501 AArch64. Default is 0. 502 503- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 504 feature. MPAM is an optional Armv8.4 extension that enables various memory 505 system components and resources to define partitions; software running at 506 various ELs can assign themselves to desired partition to control their 507 performance aspects. 508 509 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 510 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 511 access their own MPAM registers without trapping into EL3. This option 512 doesn't make use of partitioning in EL3, however. Platform initialisation 513 code should configure and use partitions in EL3 as required. This option 514 defaults to ``2`` since MPAM is enabled by default for NS world only. 515 The flag is automatically disabled when the target 516 architecture is AArch32. 517 518- ``ENABLE_FEAT_LS64_ACCDATA``: Numeric value to enable access and save and 519 restore the ACCDATA_EL1 system register, at EL2 and below. This flag can 520 take the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 521 Default value is ``0``. 522 523- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 524 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 525 firmware to detect and limit high activity events to assist in SoC processor 526 power domain dynamic power budgeting and limit the triggering of whole-rail 527 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 528 529- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 530 allows platforms with cores supporting MPMM to describe them via the 531 ``HW_CONFIG`` device tree blob. Default is 0. 532 533- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 534 support within generic code in TF-A. This option is currently only supported 535 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 536 in BL32 (SP_min) for AARCH32. Default is 0. 537 538- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 539 Measurement Framework(PMF). Default is 0. 540 541- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 542 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 543 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 544 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 545 software. 546 547- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 548 instrumentation which injects timestamp collection points into TF-A to 549 allow runtime performance to be measured. Currently, only PSCI is 550 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 551 as well. Default is 0. 552 553- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 554 extensions. This is an optional architectural feature for AArch64. 555 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 556 mechanism. The default is 2 but is automatically disabled when the target 557 architecture is AArch32. 558 559- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 560 (SVE) for the Non-secure world only. SVE is an optional architectural feature 561 for AArch64. This flag can take the values 0 to 2, to align with the 562 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be used on 563 systems that have SPM_MM enabled. The default value is 2. 564 565 Note that when SVE is enabled for the Non-secure world, access 566 to SVE, SIMD and floating-point functionality from the Secure world is 567 independently controlled by build option ``ENABLE_SVE_FOR_SWD``. When enabling 568 ``CTX_INCLUDE_FPREGS`` and ``ENABLE_SVE_FOR_NS`` together, it is mandatory to 569 enable ``CTX_INCLUDE_SVE_REGS``. This is to avoid corruption of the Non-secure 570 world data in the Z-registers which are aliased by the SIMD and FP registers. 571 572- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE and FPU/SIMD functionality 573 for the Secure world. SVE is an optional architectural feature for AArch64. 574 The default is 0 and it is automatically disabled when the target architecture 575 is AArch32. 576 577 .. note:: 578 This build flag requires ``ENABLE_SVE_FOR_NS`` to be enabled. When enabling 579 ``ENABLE_SVE_FOR_SWD``, a developer must carefully consider whether 580 ``CTX_INCLUDE_SVE_REGS`` is also needed. 581 582- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 583 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 584 default value is set to "none". "strong" is the recommended stack protection 585 level if this feature is desired. "none" disables the stack protection. For 586 all values other than "none", the ``plat_get_stack_protector_canary()`` 587 platform hook needs to be implemented. The value is passed as the last 588 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 589 590- ``ENABLE_ERRATA_ALL``: This option is used only for testing purposes, Boolean 591 option to enable the workarounds for all errata that TF-A implements. Normally 592 they should be explicitly enabled depending on each platform's needs. Not 593 recommended for release builds. This option is default set to 0. 594 595- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 596 flag depends on ``DECRYPTION_SUPPORT`` build flag. 597 598- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 599 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 600 601- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 602 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 603 on ``DECRYPTION_SUPPORT`` build flag. 604 605- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 606 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 607 build flag. 608 609- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 610 deprecated platform APIs, helper functions or drivers within Trusted 611 Firmware as error. It can take the value 1 (flag the use of deprecated 612 APIs as error) or 0. The default is 0. 613 614- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 615 configure an Arm® Ethos™-N NPU. To use this service the target platform's 616 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 617 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 618 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 619 620- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 621 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 622 ``TRUSTED_BOARD_BOOT`` to be enabled. 623 624- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 625 (```ethosn.bin```). This firmware image will be included in the FIP and 626 loaded at runtime. 627 628- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 629 targeted at EL3. When set ``0`` (default), no exceptions are expected or 630 handled at EL3, and a panic will result. The exception to this rule is when 631 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 632 occuring during normal world execution, are trapped to EL3. Any exception 633 trapped during secure world execution are trapped to the SPMC. This is 634 supported only for AArch64 builds. 635 636- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 637 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 638 Default value is 40 (LOG_LEVEL_INFO). 639 640- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 641 injection from lower ELs, and this build option enables lower ELs to use 642 Error Records accessed via System Registers to inject faults. This is 643 applicable only to AArch64 builds. 644 645 This feature is intended for testing purposes only, and is advisable to keep 646 disabled for production images. 647 648- ``FIP_NAME``: This is an optional build option which specifies the FIP 649 filename for the ``fip`` target. Default is ``fip.bin``. 650 651- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 652 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 653 654- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 655 656 :: 657 658 0: Encryption is done with Secret Symmetric Key (SSK) which is common 659 for a class of devices. 660 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 661 unique per device. 662 663 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 664 665- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 666 tool to create certificates as per the Chain of Trust described in 667 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 668 include the certificates in the FIP and FWU_FIP. Default value is '0'. 669 670 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 671 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 672 the corresponding certificates, and to include those certificates in the 673 FIP and FWU_FIP. 674 675 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 676 images will not include support for Trusted Board Boot. The FIP will still 677 include the corresponding certificates. This FIP can be used to verify the 678 Chain of Trust on the host machine through other mechanisms. 679 680 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 681 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 682 will not include the corresponding certificates, causing a boot failure. 683 684- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 685 inherent support for specific EL3 type interrupts. Setting this build option 686 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 687 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 688 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 689 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 690 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 691 the Secure Payload interrupts needs to be synchronously handed over to Secure 692 EL1 for handling. The default value of this option is ``0``, which means the 693 Group 0 interrupts are assumed to be handled by Secure EL1. 694 695- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 696 Interrupts, resulting from errors in NS world, will be always trapped in 697 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 698 will be trapped in the current exception level (or in EL1 if the current 699 exception level is EL0). 700 701- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 702 software operations are required for CPUs to enter and exit coherency. 703 However, newer systems exist where CPUs' entry to and exit from coherency 704 is managed in hardware. Such systems require software to only initiate these 705 operations, and the rest is managed in hardware, minimizing active software 706 management. In such systems, this boolean option enables TF-A to carry out 707 build and run-time optimizations during boot and power management operations. 708 This option defaults to 0 and if it is enabled, then it implies 709 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 710 711 If this flag is disabled while the platform which TF-A is compiled for 712 includes cores that manage coherency in hardware, then a compilation error is 713 generated. This is based on the fact that a system cannot have, at the same 714 time, cores that manage coherency in hardware and cores that don't. In other 715 words, a platform cannot have, at the same time, cores that require 716 ``HW_ASSISTED_COHERENCY=1`` and cores that require 717 ``HW_ASSISTED_COHERENCY=0``. 718 719 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 720 translation library (xlat tables v2) must be used; version 1 of translation 721 library is not supported. 722 723- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 724 implementation defined system register accesses from lower ELs. Default 725 value is ``0``. 726 727- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 728 bottom, higher addresses at the top. This build flag can be set to '1' to 729 invert this behavior. Lower addresses will be printed at the top and higher 730 addresses at the bottom. 731 732- ``INIT_UNUSED_NS_EL2``: This build flag guards code that disables EL2 733 safely in scenario where NS-EL2 is present but unused. This flag is set to 0 734 by default. Platforms without NS-EL2 in use must enable this flag. 735 736- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 737 used for generating the PKCS keys and subsequent signing of the certificate. 738 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 739 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 740 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 741 compatibility. The default value of this flag is ``rsa`` which is the TBBR 742 compliant PKCS#1 RSA 2.1 scheme. 743 744- ``KEY_SIZE``: This build flag enables the user to select the key size for 745 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 746 depend on the chosen algorithm and the cryptographic module. 747 748 +---------------------------+------------------------------------+ 749 | KEY_ALG | Possible key sizes | 750 +===========================+====================================+ 751 | rsa | 1024 , 2048 (default), 3072, 4096 | 752 +---------------------------+------------------------------------+ 753 | ecdsa | 256 (default), 384 | 754 +---------------------------+------------------------------------+ 755 | ecdsa-brainpool-regular | 256 (default) | 756 +---------------------------+------------------------------------+ 757 | ecdsa-brainpool-twisted | 256 (default) | 758 +---------------------------+------------------------------------+ 759 760- ``HASH_ALG``: This build flag enables the user to select the secure hash 761 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 762 The default value of this flag is ``sha256``. 763 764- ``LDFLAGS``: Extra user options appended to the linkers' command line in 765 addition to the one set by the build system. 766 767- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 768 output compiled into the build. This should be one of the following: 769 770 :: 771 772 0 (LOG_LEVEL_NONE) 773 10 (LOG_LEVEL_ERROR) 774 20 (LOG_LEVEL_NOTICE) 775 30 (LOG_LEVEL_WARNING) 776 40 (LOG_LEVEL_INFO) 777 50 (LOG_LEVEL_VERBOSE) 778 779 All log output up to and including the selected log level is compiled into 780 the build. The default value is 40 in debug builds and 20 in release builds. 781 782- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 783 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 784 provide trust that the code taking the measurements and recording them has 785 not been tampered with. 786 787 This option defaults to 0. 788 789- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 790 options to the compiler. An example usage: 791 792 .. code:: make 793 794 MARCH_DIRECTIVE := -march=armv8.5-a 795 796- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 797 options to the compiler currently supporting only of the options. 798 GCC documentation: 799 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 800 801 An example usage: 802 803 .. code:: make 804 805 HARDEN_SLS := 1 806 807 This option defaults to 0. 808 809- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 810 specifies a file that contains the Non-Trusted World private key in PEM 811 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 812 will be used to save the key. 813 814- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 815 optional. It is only needed if the platform makefile specifies that it 816 is required in order to build the ``fwu_fip`` target. 817 818- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 819 contents upon world switch. It can take either 0 (don't save and restore) or 820 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 821 wants the timer registers to be saved and restored. 822 823- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 824 for the BL image. It can be either 0 (include) or 1 (remove). The default 825 value is 0. 826 827- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 828 the underlying hardware is not a full PL011 UART but a minimally compliant 829 generic UART, which is a subset of the PL011. The driver will not access 830 any register that is not part of the SBSA generic UART specification. 831 Default value is 0 (a full PL011 compliant UART is present). 832 833- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 834 must be subdirectory of any depth under ``plat/``, and must contain a 835 platform makefile named ``platform.mk``. For example, to build TF-A for the 836 Arm Juno board, select PLAT=juno. 837 838- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 839 each core as well as the global context. The data includes the memory used 840 by each world and each privileged exception level. This build option is 841 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 842 843- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 844 instead of the normal boot flow. When defined, it must specify the entry 845 point address for the preloaded BL33 image. This option is incompatible with 846 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 847 over ``PRELOADED_BL33_BASE``. 848 849- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 850 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 851 registers when the cluster goes through a power cycle. This is disabled by 852 default and platforms that require this feature have to enable them. 853 854- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 855 vector address can be programmed or is fixed on the platform. It can take 856 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 857 programmable reset address, it is expected that a CPU will start executing 858 code directly at the right address, both on a cold and warm reset. In this 859 case, there is no need to identify the entrypoint on boot and the boot path 860 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 861 does not need to be implemented in this case. 862 863- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 864 possible for the PSCI power-state parameter: original and extended State-ID 865 formats. This flag if set to 1, configures the generic PSCI layer to use the 866 extended format. The default value of this flag is 0, which means by default 867 the original power-state format is used by the PSCI implementation. This flag 868 should be specified by the platform makefile and it governs the return value 869 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 870 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 871 set to 1 as well. 872 873- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 874 OS-initiated mode. This option defaults to 0. 875 876- ``ARCH_FEATURE_AVAILABILITY``: Boolean flag to enable support for the 877 optional SMCCC_ARCH_FEATURE_AVAILABILITY call. This option implicitly 878 interacts with IMPDEF_SYSREG_TRAP and software emulation. This option 879 defaults to 0. 880 881- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 882 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 883 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 884 NOTE: This flag enables use of IESB capability to reduce entry latency into 885 EL3 even when RAS error handling is not performed on the platform. Hence this 886 flag is recommended to be turned on Armv8.2 and later CPUs. 887 888- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 889 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 890 entrypoint) or 1 (CPU reset to BL31 entrypoint). 891 The default value is 0. 892 893- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 894 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 895 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 896 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 897 898- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 899- blocks) covered by a single bit of the bitlock structure during RME GPT 900- operations. The lower the block size, the better opportunity for 901- parallelising GPT operations but at the cost of more bits being needed 902- for the bitlock structure. This numeric parameter can take the values 903- from 0 to 512 and must be a power of 2. The value of 0 is special and 904- and it chooses a single spinlock for all GPT L1 table entries. Default 905- value is 1 which corresponds to block size of 512MB per bit of bitlock 906- structure. 907 908- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 909 supported contiguous blocks in GPT Library. This parameter can take the 910 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 911 descriptors. Default value is 512. 912 913- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 914 file that contains the ROT private key in PEM format or a PKCS11 URI and 915 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 916 accepted and it will be used to save the key. 917 918- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 919 certificate generation tool to save the keys used to establish the Chain of 920 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 921 922- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 923 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 924 target. 925 926- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 927 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 928 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 929 930- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 931 optional. It is only needed if the platform makefile specifies that it 932 is required in order to build the ``fwu_fip`` target. 933 934- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 935 Delegated Exception Interface to BL31 image. This defaults to ``0``. 936 937 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 938 set to ``1``. 939 940- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 941 isolated on separate memory pages. This is a trade-off between security and 942 memory usage. See "Isolating code and read-only data on separate memory 943 pages" section in :ref:`Firmware Design`. This flag is disabled by default 944 and affects all BL images. 945 946- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 947 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 948 allocated in RAM discontiguous from the loaded firmware image. When set, the 949 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 950 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 951 sections are placed in RAM immediately following the loaded firmware image. 952 953- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 954 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 955 discontiguous from loaded firmware images. When set, the platform need to 956 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 957 flag is disabled by default and NOLOAD sections are placed in RAM immediately 958 following the loaded firmware image. 959 960- ``SEPARATE_SIMD_SECTION``: Setting this option to ``1`` allows the SIMD context 961 data structures to be put in a dedicated memory region as decided by platform 962 integrator. Default value is ``0`` which means the SIMD context is put in BSS 963 section of EL3 firmware. 964 965- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 966 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 967 UEFI+ACPI this can provide a certain amount of OS forward compatibility 968 with newer platforms that aren't ECAM compliant. 969 970- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 971 This build option is only valid if ``ARCH=aarch64``. The value should be 972 the path to the directory containing the SPD source, relative to 973 ``services/spd/``; the directory is expected to contain a makefile called 974 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 975 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 976 cannot be enabled when the ``SPM_MM`` option is enabled. 977 978- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 979 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 980 execution in BL1 just before handing over to BL31. At this point, all 981 firmware images have been loaded in memory, and the MMU and caches are 982 turned off. Refer to the "Debugging options" section for more details. 983 984- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 985 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 986 component runs at the EL3 exception level. The default value is ``0`` ( 987 disabled). This configuration supports pre-Armv8.4 platforms (aka not 988 implementing the ``FEAT_SEL2`` extension). 989 990- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 991 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 992 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 993 994- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 995 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 996 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 997 mechanism should be used. 998 999- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 1000 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1001 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 1002 extension. This is the default when enabling the SPM Dispatcher. When 1003 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 1004 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 1005 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 1006 extension). 1007 1008- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 1009 Partition Manager (SPM) implementation. The default value is ``0`` 1010 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 1011 enabled (``SPD=spmd``). 1012 1013- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 1014 description of secure partitions. The build system will parse this file and 1015 package all secure partition blobs into the FIP. This file is not 1016 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 1017 1018- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 1019 secure interrupts (caught through the FIQ line). Platforms can enable 1020 this directive if they need to handle such interruption. When enabled, 1021 the FIQ are handled in monitor mode and non secure world is not allowed 1022 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 1023 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 1024 1025- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 1026 Platforms can configure this if they need to lower the hardware 1027 limit, for example due to asymmetric configuration or limitations of 1028 software run at lower ELs. The default is the architectural maximum 1029 of 2048 which should be suitable for most configurations, the 1030 hardware will limit the effective VL to the maximum physically supported 1031 VL. 1032 1033- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 1034 Random Number Generator Interface to BL31 image. This defaults to ``0``. 1035 1036- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 1037 Boot feature. When set to '1', BL1 and BL2 images include support to load 1038 and verify the certificates and images in a FIP, and BL1 includes support 1039 for the Firmware Update. The default value is '0'. Generation and inclusion 1040 of certificates in the FIP and FWU_FIP depends upon the value of the 1041 ``GENERATE_COT`` option. 1042 1043 .. warning:: 1044 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 1045 already exist in disk, they will be overwritten without further notice. 1046 1047- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 1048 specifies a file that contains the Trusted World private key in PEM 1049 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 1050 it will be used to save the key. 1051 1052- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 1053 synchronous, (see "Initializing a BL32 Image" section in 1054 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 1055 synchronous method) or 1 (BL32 is initialized using asynchronous method). 1056 Default is 0. 1057 1058- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 1059 routing model which routes non-secure interrupts asynchronously from TSP 1060 to EL3 causing immediate preemption of TSP. The EL3 is responsible 1061 for saving and restoring the TSP context in this routing model. The 1062 default routing model (when the value is 0) is to route non-secure 1063 interrupts to TSP allowing it to save its context and hand over 1064 synchronously to EL3 via an SMC. 1065 1066 .. note:: 1067 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 1068 must also be set to ``1``. 1069 1070- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 1071 internal-trusted-storage) as SP in tb_fw_config device tree. 1072 1073- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1074 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1075 this delay. It can take values in the range (0-15). Default value is ``0`` 1076 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1077 Platforms need to explicitly update this value based on their requirements. 1078 1079- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1080 linker. When the ``LINKER`` build variable points to the armlink linker, 1081 this flag is enabled automatically. To enable support for armlink, platforms 1082 will have to provide a scatter file for the BL image. Currently, Tegra 1083 platforms use the armlink support to compile BL3-1 images. 1084 1085- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1086 memory region in the BL memory map or not (see "Use of Coherent memory in 1087 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1088 (Coherent memory region is included) or 0 (Coherent memory region is 1089 excluded). Default is 1. 1090 1091- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1092 firmware configuration framework. This will move the io_policies into a 1093 configuration device tree, instead of static structure in the code base. 1094 1095- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1096 at runtime using fconf. If this flag is enabled, COT descriptors are 1097 statically captured in tb_fw_config file in the form of device tree nodes 1098 and properties. Currently, COT descriptors used by BL2 are moved to the 1099 device tree and COT descriptors used by BL1 are retained in the code 1100 base statically. 1101 1102- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1103 runtime using firmware configuration framework. The platform specific SDEI 1104 shared and private events configuration is retrieved from device tree rather 1105 than static C structures at compile time. This is only supported if 1106 SDEI_SUPPORT build flag is enabled. 1107 1108- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1109 and Group1 secure interrupts using the firmware configuration framework. The 1110 platform specific secure interrupt property descriptor is retrieved from 1111 device tree in runtime rather than depending on static C structure at compile 1112 time. 1113 1114- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1115 This feature creates a library of functions to be placed in ROM and thus 1116 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1117 is 0. 1118 1119- ``V``: Verbose build. If assigned anything other than 0, the build commands 1120 are printed. Default is 0. 1121 1122- ``VERSION_STRING``: String used in the log output for each TF-A image. 1123 Defaults to a string formed by concatenating the version number, build type 1124 and build string. 1125 1126- ``W``: Warning level. Some compiler warning options of interest have been 1127 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1128 each level enabling more warning options. Default is 0. 1129 1130 This option is closely related to the ``E`` option, which enables 1131 ``-Werror``. 1132 1133 - ``W=0`` (default) 1134 1135 Enables a wide assortment of warnings, most notably ``-Wall`` and 1136 ``-Wextra``, as well as various bad practices and things that are likely to 1137 result in errors. Includes some compiler specific flags. No warnings are 1138 expected at this level for any build. 1139 1140 - ``W=1`` 1141 1142 Enables warnings we want the generic build to include but are too time 1143 consuming to fix at the moment. It re-enables warnings taken out for 1144 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1145 to eventually be merged into ``W=0``. Some warnings are expected on some 1146 builds, but new contributions should not introduce new ones. 1147 1148 - ``W=2`` (recommended) 1149 1150 Enables warnings we want the generic build to include but cannot be enabled 1151 due to external libraries. This level is expected to eventually be merged 1152 into ``W=0``. Lots of warnings are expected, primarily from external 1153 libraries like zlib and compiler-rt, but new controbutions should not 1154 introduce new ones. 1155 1156 - ``W=3`` 1157 1158 Enables warnings that are informative but not necessary and generally too 1159 verbose and frequently ignored. A very large number of warnings are 1160 expected. 1161 1162 The exact set of warning flags depends on the compiler and TF-A warning 1163 level, however they are all succinctly set in the top-level Makefile. Please 1164 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1165 individual flags. 1166 1167- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1168 the CPU after warm boot. This is applicable for platforms which do not 1169 require interconnect programming to enable cache coherency (eg: single 1170 cluster platforms). If this option is enabled, then warm boot path 1171 enables D-caches immediately after enabling MMU. This option defaults to 0. 1172 1173- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1174 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1175 default value of this flag is ``no``. Note this option must be enabled only 1176 for ARM architecture greater than Armv8.5-A. 1177 1178- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1179 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1180 The default value of this flag is ``0``. 1181 1182 ``AT`` speculative errata workaround disables stage1 page table walk for 1183 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1184 produces either the correct result or failure without TLB allocation. 1185 1186 This boolean option enables errata for all below CPUs. 1187 1188 +---------+--------------+-------------------------+ 1189 | Errata | CPU | Workaround Define | 1190 +=========+==============+=========================+ 1191 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1192 +---------+--------------+-------------------------+ 1193 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1194 +---------+--------------+-------------------------+ 1195 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1196 +---------+--------------+-------------------------+ 1197 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1198 +---------+--------------+-------------------------+ 1199 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1200 +---------+--------------+-------------------------+ 1201 1202 .. note:: 1203 This option is enabled by build only if platform sets any of above defines 1204 mentioned in ’Workaround Define' column in the table. 1205 If this option is enabled for the EL3 software then EL2 software also must 1206 implement this workaround due to the behaviour of the errata mentioned 1207 in new SDEN document which will get published soon. 1208 1209- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1210 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1211 This flag is disabled by default. 1212 1213- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1214 host machine where a custom installation of OpenSSL is located, which is used 1215 to build the certificate generation, firmware encryption and FIP tools. If 1216 this option is not set, the default OS installation will be used. 1217 1218- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1219 functions that wait for an arbitrary time length (udelay and mdelay). The 1220 default value is 0. 1221 1222- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1223 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1224 optional architectural feature for AArch64. This flag can take the values 1225 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1226 and it is automatically disabled when the target architecture is AArch32. 1227 1228- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1229 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1230 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1231 feature for AArch64. This flag can take the values 0 to 2, to align with the 1232 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1233 disabled when the target architecture is AArch32. 1234 1235- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1236 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1237 but unused). This feature is available if trace unit such as ETMv4.x, and 1238 ETE(extending ETM feature) is implemented. This flag can take the values 1239 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1240 1241- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1242 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1243 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1244 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1245 1246- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1247 ``plat_can_cmo`` which will return zero if cache management operations should 1248 be skipped and non-zero otherwise. By default, this option is disabled which 1249 means platform hook won't be checked and CMOs will always be performed when 1250 related functions are called. 1251 1252- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1253 firmware interface for the BL31 image. By default its disabled (``0``). 1254 1255- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1256 errata mitigation for platforms with a non-arm interconnect using the errata 1257 ABI. By default its disabled (``0``). 1258 1259- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1260 driver(s). By default it is disabled (``0``) because it constitutes an attack 1261 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1262 This option should only be enabled on a need basis if there is a use case for 1263 reading characters from the console. 1264 1265GICv3 driver options 1266-------------------- 1267 1268GICv3 driver files are included using directive: 1269 1270``include drivers/arm/gic/v3/gicv3.mk`` 1271 1272The driver can be configured with the following options set in the platform 1273makefile: 1274 1275- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1276 Enabling this option will add runtime detection support for the 1277 GIC-600, so is safe to select even for a GIC500 implementation. 1278 This option defaults to 0. 1279 1280- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1281 for GIC-600 AE. Enabling this option will introduce support to initialize 1282 the FMU. Platforms should call the init function during boot to enable the 1283 FMU and its safety mechanisms. This option defaults to 0. 1284 1285- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1286 functionality. This option defaults to 0 1287 1288- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1289 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1290 functions. This is required for FVP platform which need to simulate GIC save 1291 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1292 1293- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1294 This option defaults to 0. 1295 1296- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1297 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1298 1299Debugging options 1300----------------- 1301 1302To compile a debug version and make the build more verbose use 1303 1304.. code:: shell 1305 1306 make PLAT=<platform> DEBUG=1 V=1 all 1307 1308AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1309(for example Arm-DS) might not support this and may need an older version of 1310DWARF symbols to be emitted by GCC. This can be achieved by using the 1311``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1312the version to 4 is recommended for Arm-DS. 1313 1314When debugging logic problems it might also be useful to disable all compiler 1315optimizations by using ``-O0``. 1316 1317.. warning:: 1318 Using ``-O0`` could cause output images to be larger and base addresses 1319 might need to be recalculated (see the **Memory layout on Arm development 1320 platforms** section in the :ref:`Firmware Design`). 1321 1322Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1323``LDFLAGS``: 1324 1325.. code:: shell 1326 1327 CFLAGS='-O0 -gdwarf-2' \ 1328 make PLAT=<platform> DEBUG=1 V=1 all 1329 1330Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1331ignored as the linker is called directly. 1332 1333It is also possible to introduce an infinite loop to help in debugging the 1334post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1335``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1336section. In this case, the developer may take control of the target using a 1337debugger when indicated by the console output. When using Arm-DS, the following 1338commands can be used: 1339 1340:: 1341 1342 # Stop target execution 1343 interrupt 1344 1345 # 1346 # Prepare your debugging environment, e.g. set breakpoints 1347 # 1348 1349 # Jump over the debug loop 1350 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1351 1352 # Resume execution 1353 continue 1354 1355.. _build_options_experimental: 1356 1357Experimental build options 1358--------------------------- 1359 1360Common build options 1361~~~~~~~~~~~~~~~~~~~~ 1362 1363- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1364 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1365 set to ``1`` then measurements and additional metadata collected during the 1366 measured boot process are sent to the DICE Protection Environment for storage 1367 and processing. A certificate chain, which represents the boot state of the 1368 device, can be queried from the DPE. 1369 1370- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1371 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1372 the measurements and recording them as per `PSA DRTM specification`_. For 1373 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1374 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1375 should have mechanism to authenticate BL31. This option defaults to 0. 1376 1377- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1378 Management Extension. This flag can take the values 0 to 2, to align with 1379 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1380 1381- ``RMMD_ENABLE_EL3_TOKEN_SIGN``: Numeric value to enable support for singing 1382 realm attestation token signing requests in EL3. This flag can take the 1383 values 0 and 1. The default value is ``0``. When set to ``1``, this option 1384 enables additional RMMD SMCs to push and pop requests for signing to 1385 EL3 along with platform hooks that must be implemented to service those 1386 requests and responses. 1387 1388- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1389 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1390 registers so are enabled together. Using this option without 1391 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1392 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1393 superset of SVE. SME is an optional architectural feature for AArch64. 1394 At this time, this build option cannot be used on systems that have 1395 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1396 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1397 mechanism. Default is 0. 1398 1399- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1400 version 2 (SME2) for the non-secure world only. SME2 is an optional 1401 architectural feature for AArch64. 1402 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1403 accesses will still be trapped. This flag can take the values 0 to 2, to 1404 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1405 1406- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1407 Extension for secure world. Used along with SVE and FPU/SIMD. 1408 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1409 Default is 0. 1410 1411- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1412 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1413 for logical partitions in EL3, managed by the SPMD as defined in the 1414 FF-A v1.2 specification. This flag is disabled by default. This flag 1415 must not be used if ``SPMC_AT_EL3`` is enabled. 1416 1417- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1418 verification mechanism. This is a debug feature that compares the 1419 architectural features enabled through the feature specific build flags 1420 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1421 and reports any discrepancies. 1422 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1423 1424 It is expected that this feature is only used for flexible platforms like 1425 software emulators, or for hardware platforms at bringup time, to verify 1426 that the configured feature set matches the CPU. 1427 The ``FEATURE_DETECTION`` macro is disabled by default. 1428 1429- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1430 The platform will use PSA compliant Crypto APIs during authentication and 1431 image measurement process by enabling this option. It uses APIs defined as 1432 per the `PSA Crypto API specification`_. This feature is only supported if 1433 using MbedTLS 3.x version. It is disabled (``0``) by default. 1434 1435- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1436 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1437 This defaults to ``0``. Current implementation follows the Firmware Handoff 1438 specification v0.9. 1439 1440- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1441 interface through BL31 as a SiP SMC function. 1442 Default is disabled (0). 1443 1444- ``HOB_LIST``: Setting this to ``1`` enables support for passing boot 1445 information using HOB defined in `Platform Initialization specification`_. 1446 This defaults to ``0``. 1447 1448Firmware update options 1449~~~~~~~~~~~~~~~~~~~~~~~ 1450 1451- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1452 `PSA FW update specification`_. The default value is 0. 1453 PSA firmware update implementation has few limitations, such as: 1454 1455 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1456 be updated, then it should be done through another platform-defined 1457 mechanism. 1458 1459 - It assumes the platform's hardware supports CRC32 instructions. 1460 1461- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1462 in defining the firmware update metadata structure. This flag is by default 1463 set to '2'. 1464 1465- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1466 firmware bank. Each firmware bank must have the same number of images as per 1467 the `PSA FW update specification`_. 1468 This flag is used in defining the firmware update metadata structure. This 1469 flag is by default set to '1'. 1470 1471- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1472 metadata contains image description. The default value is 1. 1473 1474 The version 2 of the FWU metadata allows for an opaque metadata 1475 structure where a platform can choose to not include the firmware 1476 store description in the metadata structure. This option indicates 1477 if the firmware store description, which provides information on 1478 the updatable images is part of the structure. 1479 1480-------------- 1481 1482*Copyright (c) 2019-2025, Arm Limited. All rights reserved.* 1483 1484.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1485.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1486.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1487.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1488.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1489.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1490.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1491.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html 1492