1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 49 SP nodes in tb_fw_config. 50 51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 53 54- ``BL2``: This is an optional build option which specifies the path to BL2 55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 56 built. 57 58- ``BL2U``: This is an optional build option which specifies the path to 59 BL2U image. In this case, the BL2U in TF-A will not be built. 60 61- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 63 entrypoint) or 1 (CPU reset to BL2 entrypoint). 64 The default value is 0. 65 66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 68 true in a 4-world system where RESET_TO_BL2 is 0. 69 70- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 72 73- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 75 the RW sections in RAM, while leaving the RO sections in place. This option 76 enable this use-case. For now, this option is only supported 77 when RESET_TO_BL2 is set to '1'. 78 79- ``BL31``: This is an optional build option which specifies the path to 80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 81 be built. 82 83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 84 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 85 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 86 87- ``BL32``: This is an optional build option which specifies the path to 88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 89 be built. 90 91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 92 Trusted OS Extra1 image for the ``fip`` target. 93 94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 95 Trusted OS Extra2 image for the ``fip`` target. 96 97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 98 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 99 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 100 101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 102 ``fip`` target in case TF-A BL2 is used. 103 104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 105 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 106 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 107 108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 110 If enabled, it is needed to use a compiler that supports the option 111 ``-mbranch-protection``. Selects the branch protection features to use: 112- 0: Default value turns off all types of branch protection 113- 1: Enables all types of branch protection features 114- 2: Return address signing to its standard level 115- 3: Extend the signing to include leaf functions 116- 4: Turn on branch target identification mechanism 117 118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 119 and resulting PAuth/BTI features. 120 121 +-------+--------------+-------+-----+ 122 | Value | GCC option | PAuth | BTI | 123 +=======+==============+=======+=====+ 124 | 0 | none | N | N | 125 +-------+--------------+-------+-----+ 126 | 1 | standard | Y | Y | 127 +-------+--------------+-------+-----+ 128 | 2 | pac-ret | Y | N | 129 +-------+--------------+-------+-----+ 130 | 3 | pac-ret+leaf | Y | N | 131 +-------+--------------+-------+-----+ 132 | 4 | bti | N | Y | 133 +-------+--------------+-------+-----+ 134 135 This option defaults to 0. 136 Note that Pointer Authentication is enabled for Non-secure world 137 irrespective of the value of this option if the CPU supports it. 138 139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 140 compilation of each build. It must be set to a C string (including quotes 141 where applicable). Defaults to a string that contains the time and date of 142 the compilation. 143 144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 145 build to be uniquely identified. Defaults to the current git commit id. 146 147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 148 149- ``CFLAGS``: Extra user options appended on the compiler's command line in 150 addition to the options set by the build system. 151 152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 153 release several CPUs out of reset. It can take either 0 (several CPUs may be 154 brought up) or 1 (only one CPU will ever be brought up during cold reset). 155 Default is 0. If the platform always brings up a single CPU, there is no 156 need to distinguish between primary and secondary CPUs and the boot path can 157 be optimised. The ``plat_is_my_cpu_primary()`` and 158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 159 to be implemented in this case. 160 161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 162 Defaults to ``tbbr``. 163 164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 165 register state when an unexpected exception occurs during execution of 166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 167 this is only enabled for a debug build of the firmware. 168 169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 170 certificate generation tool to create new keys in case no valid keys are 171 present or specified. Allowed options are '0' or '1'. Default is '1'. 172 173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 174 the AArch32 system registers to be included when saving and restoring the 175 CPU context. The option must be set to 0 for AArch64-only platforms (that 176 is on hardware that does not implement AArch32, or at least not at EL1 and 177 higher ELs). Default value is 1. 178 179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 180 registers to be included when saving and restoring the CPU context. Default 181 is 0. 182 183- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 184 Memory System Resource Partitioning and Monitoring (MPAM) 185 registers to be included when saving and restoring the CPU context. 186 Default is '0'. 187 188- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 189 registers in cpu context. This must be enabled, if the platform wants to use 190 this feature in the Secure world and MTE is enabled at ELX. This flag can 191 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 192 Default value is 0. 193 194- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 195 registers to be saved/restored when entering/exiting an EL2 execution 196 context. This flag can take values 0 to 2, to align with the 197 ``FEATURE_DETECTION`` mechanism. Default value is 0. 198 199- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 200 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 201 to be included when saving and restoring the CPU context as part of world 202 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 203 mechanism. Default value is 0. 204 205 Note that Pointer Authentication is enabled for Non-secure world irrespective 206 of the value of this flag if the CPU supports it. 207 208- ``DEBUG``: Chooses between a debug and release build. It can take either 0 209 (release) or 1 (debug) as values. 0 is the default. 210 211- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 212 authenticated decryption algorithm to be used to decrypt firmware/s during 213 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 214 this flag is ``none`` to disable firmware decryption which is an optional 215 feature as per TBBR. 216 217- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 218 of the binary image. If set to 1, then only the ELF image is built. 219 0 is the default. 220 221- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 222 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 223 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 224 mechanism. Default is ``0``. 225 226- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 227 Board Boot authentication at runtime. This option is meant to be enabled only 228 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 229 flag has to be enabled. 0 is the default. 230 231- ``E``: Boolean option to make warnings into errors. Default is 1. 232 233 When specifying higher warnings levels (``W=1`` and higher), this option 234 defaults to 0. This is done to encourage contributors to use them, as they 235 are expected to produce warnings that would otherwise fail the build. New 236 contributions are still expected to build with ``W=0`` and ``E=1`` (the 237 default). 238 239- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 240 the normal boot flow. It must specify the entry point address of the EL3 241 payload. Please refer to the "Booting an EL3 payload" section for more 242 details. 243 244- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 245 (also known as group 1 counters). These are implementation-defined counters, 246 and as such require additional platform configuration. Default is 0. 247 248- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 249 allows platforms with auxiliary counters to describe them via the 250 ``HW_CONFIG`` device tree blob. Default is 0. 251 252- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 253 are compiled out. For debug builds, this option defaults to 1, and calls to 254 ``assert()`` are left in place. For release builds, this option defaults to 0 255 and calls to ``assert()`` function are compiled out. This option can be set 256 independently of ``DEBUG``. It can also be used to hide any auxiliary code 257 that is only required for the assertion and does not fit in the assertion 258 itself. 259 260- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 261 dumps or not. It is supported in both AArch64 and AArch32. However, in 262 AArch32 the format of the frame records are not defined in the AAPCS and they 263 are defined by the implementation. This implementation of backtrace only 264 supports the format used by GCC when T32 interworking is disabled. For this 265 reason enabling this option in AArch32 will force the compiler to only 266 generate A32 code. This option is enabled by default only in AArch64 debug 267 builds, but this behaviour can be overridden in each platform's Makefile or 268 in the build command line. 269 270- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 271 extensions. This flag can take the values 0 to 2, to align with the 272 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature 273 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 274 and this option can be used to enable this feature on those systems as well. 275 This flag can take the values 0 to 2, the default is 0. 276 277- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 278 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 279 onwards. This flag can take the values 0 to 2, to align with the 280 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 281 282- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 283 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 284 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 285 optional feature available on Arm v8.0 onwards. This flag can take values 286 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 287 Default value is ``0``. 288 289- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 290 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 291 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 292 and upwards. This flag can take the values 0 to 2, to align with the 293 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 294 295- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 296 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 297 Physical Offset register) during EL2 to EL3 context save/restore operations. 298 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 299 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 300 mechanism. Default value is ``0``. 301 302- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 303 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 304 Read Trap Register) during EL2 to EL3 context save/restore operations. 305 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 306 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 307 mechanism. Default value is ``0``. 308 309- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 310 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 311 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 312 mandatory architectural feature and is enabled from v8.7 and upwards. This 313 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 314 mechanism. Default value is ``0``. 315 316- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for 317 ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to 318 memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural 319 feature available from v8.9 and upwards. This flag can take the values 0 to 320 2, to align with the ``FEATURE_DETECTION`` mechanism. Default value is 321 ``0``. 322 323- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 324 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 325 permission fault for any privileged data access from EL1/EL2 to virtual 326 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 327 mandatory architectural feature and is enabled from v8.1 and upwards. This 328 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 329 mechanism. Default value is ``0``. 330 331- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 332 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 333 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 334 mechanism. Default value is ``0``. 335 336- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 337 extension. This feature is only supported in AArch64 state. This flag can 338 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 339 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 340 Armv8.5 onwards. 341 342- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 343 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 344 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 345 later CPUs. It is enabled from v8.5 and upwards and if needed can be 346 overidden from platforms explicitly. 347 348- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 349 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 350 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 351 mechanism. Default is ``0``. 352 353- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 354 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 355 available on Arm v8.6. This flag can take values 0 to 2, to align with the 356 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 357 358 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 359 delayed by the amount of value in ``TWED_DELAY``. 360 361- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 362 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 363 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 364 architectural feature and is enabled from v8.1 and upwards. It can take 365 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 366 Default value is ``0``. 367 368- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 369 allow access to TCR2_EL2 (extended translation control) from EL2 as 370 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 371 mandatory architectural feature and is enabled from v8.9 and upwards. This 372 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 373 mechanism. Default value is ``0``. 374 375- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 376 at EL2 and below, and context switch relevant registers. This flag 377 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 378 mechanism. Default value is ``0``. 379 380- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 381 at EL2 and below, and context switch relevant registers. This flag 382 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 383 mechanism. Default value is ``0``. 384 385- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 386 at EL2 and below, and context switch relevant registers. This flag 387 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 388 mechanism. Default value is ``0``. 389 390- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 391 at EL2 and below, and context switch relevant registers. This flag 392 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 393 mechanism. Default value is ``0``. 394 395- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 396 allow use of Guarded Control Stack from EL2 as well as adding the GCS 397 registers to the EL2 context save/restore operations. This flag can take 398 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 399 Default value is ``0``. 400 401- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 402 support in GCC for TF-A. This option is currently only supported for 403 AArch64. Default is 0. 404 405- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 406 feature. MPAM is an optional Armv8.4 extension that enables various memory 407 system components and resources to define partitions; software running at 408 various ELs can assign themselves to desired partition to control their 409 performance aspects. 410 411 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 412 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 413 access their own MPAM registers without trapping into EL3. This option 414 doesn't make use of partitioning in EL3, however. Platform initialisation 415 code should configure and use partitions in EL3 as required. This option 416 defaults to ``2`` since MPAM is enabled by default for NS world only. 417 The flag is automatically disabled when the target 418 architecture is AArch32. 419 420- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 421 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 422 firmware to detect and limit high activity events to assist in SoC processor 423 power domain dynamic power budgeting and limit the triggering of whole-rail 424 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 425 426- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 427 allows platforms with cores supporting MPMM to describe them via the 428 ``HW_CONFIG`` device tree blob. Default is 0. 429 430- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 431 support within generic code in TF-A. This option is currently only supported 432 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 433 in BL32 (SP_min) for AARCH32. Default is 0. 434 435- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 436 Measurement Framework(PMF). Default is 0. 437 438- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 439 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 440 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 441 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 442 software. 443 444- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 445 instrumentation which injects timestamp collection points into TF-A to 446 allow runtime performance to be measured. Currently, only PSCI is 447 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 448 as well. Default is 0. 449 450- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 451 extensions. This is an optional architectural feature for AArch64. 452 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 453 mechanism. The default is 2 but is automatically disabled when the target 454 architecture is AArch32. 455 456- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 457 (SVE) for the Non-secure world only. SVE is an optional architectural feature 458 for AArch64. Note that when SVE is enabled for the Non-secure world, access 459 to SIMD and floating-point functionality from the Secure world is disabled by 460 default and controlled with ENABLE_SVE_FOR_SWD. 461 This is to avoid corruption of the Non-secure world data in the Z-registers 462 which are aliased by the SIMD and FP registers. The build option is not 463 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 464 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 465 enabled. This flag can take the values 0 to 2, to align with the 466 ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be 467 used on systems that have SPM_MM enabled. The default is 1. 468 469- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 470 SVE is an optional architectural feature for AArch64. Note that this option 471 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 472 automatically disabled when the target architecture is AArch32. 473 474- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 475 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 476 default value is set to "none". "strong" is the recommended stack protection 477 level if this feature is desired. "none" disables the stack protection. For 478 all values other than "none", the ``plat_get_stack_protector_canary()`` 479 platform hook needs to be implemented. The value is passed as the last 480 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 481 482- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 483 flag depends on ``DECRYPTION_SUPPORT`` build flag. 484 485- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 486 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 487 488- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 489 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 490 on ``DECRYPTION_SUPPORT`` build flag. 491 492- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 493 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 494 build flag. 495 496- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 497 deprecated platform APIs, helper functions or drivers within Trusted 498 Firmware as error. It can take the value 1 (flag the use of deprecated 499 APIs as error) or 0. The default is 0. 500 501- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 502 configure an Arm® Ethos™-N NPU. To use this service the target platform's 503 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 504 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 505 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 506 507- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 508 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 509 ``TRUSTED_BOARD_BOOT`` to be enabled. 510 511- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 512 (```ethosn.bin```). This firmware image will be included in the FIP and 513 loaded at runtime. 514 515- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 516 targeted at EL3. When set ``0`` (default), no exceptions are expected or 517 handled at EL3, and a panic will result. The exception to this rule is when 518 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 519 occuring during normal world execution, are trapped to EL3. Any exception 520 trapped during secure world execution are trapped to the SPMC. This is 521 supported only for AArch64 builds. 522 523- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 524 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 525 Default value is 40 (LOG_LEVEL_INFO). 526 527- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 528 injection from lower ELs, and this build option enables lower ELs to use 529 Error Records accessed via System Registers to inject faults. This is 530 applicable only to AArch64 builds. 531 532 This feature is intended for testing purposes only, and is advisable to keep 533 disabled for production images. 534 535- ``FIP_NAME``: This is an optional build option which specifies the FIP 536 filename for the ``fip`` target. Default is ``fip.bin``. 537 538- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 539 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 540 541- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 542 543 :: 544 545 0: Encryption is done with Secret Symmetric Key (SSK) which is common 546 for a class of devices. 547 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 548 unique per device. 549 550 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 551 552- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 553 tool to create certificates as per the Chain of Trust described in 554 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 555 include the certificates in the FIP and FWU_FIP. Default value is '0'. 556 557 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 558 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 559 the corresponding certificates, and to include those certificates in the 560 FIP and FWU_FIP. 561 562 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 563 images will not include support for Trusted Board Boot. The FIP will still 564 include the corresponding certificates. This FIP can be used to verify the 565 Chain of Trust on the host machine through other mechanisms. 566 567 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 568 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 569 will not include the corresponding certificates, causing a boot failure. 570 571- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 572 inherent support for specific EL3 type interrupts. Setting this build option 573 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 574 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 575 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 576 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 577 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 578 the Secure Payload interrupts needs to be synchronously handed over to Secure 579 EL1 for handling. The default value of this option is ``0``, which means the 580 Group 0 interrupts are assumed to be handled by Secure EL1. 581 582- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 583 Interrupts, resulting from errors in NS world, will be always trapped in 584 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 585 will be trapped in the current exception level (or in EL1 if the current 586 exception level is EL0). 587 588- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 589 software operations are required for CPUs to enter and exit coherency. 590 However, newer systems exist where CPUs' entry to and exit from coherency 591 is managed in hardware. Such systems require software to only initiate these 592 operations, and the rest is managed in hardware, minimizing active software 593 management. In such systems, this boolean option enables TF-A to carry out 594 build and run-time optimizations during boot and power management operations. 595 This option defaults to 0 and if it is enabled, then it implies 596 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 597 598 If this flag is disabled while the platform which TF-A is compiled for 599 includes cores that manage coherency in hardware, then a compilation error is 600 generated. This is based on the fact that a system cannot have, at the same 601 time, cores that manage coherency in hardware and cores that don't. In other 602 words, a platform cannot have, at the same time, cores that require 603 ``HW_ASSISTED_COHERENCY=1`` and cores that require 604 ``HW_ASSISTED_COHERENCY=0``. 605 606 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 607 translation library (xlat tables v2) must be used; version 1 of translation 608 library is not supported. 609 610- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 611 implementation defined system register accesses from lower ELs. Default 612 value is ``0``. 613 614- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 615 bottom, higher addresses at the top. This build flag can be set to '1' to 616 invert this behavior. Lower addresses will be printed at the top and higher 617 addresses at the bottom. 618 619- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 620 used for generating the PKCS keys and subsequent signing of the certificate. 621 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 622 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 623 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 624 compatibility. The default value of this flag is ``rsa`` which is the TBBR 625 compliant PKCS#1 RSA 2.1 scheme. 626 627- ``KEY_SIZE``: This build flag enables the user to select the key size for 628 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 629 depend on the chosen algorithm and the cryptographic module. 630 631 +---------------------------+------------------------------------+ 632 | KEY_ALG | Possible key sizes | 633 +===========================+====================================+ 634 | rsa | 1024 , 2048 (default), 3072, 4096 | 635 +---------------------------+------------------------------------+ 636 | ecdsa | 256 (default), 384 | 637 +---------------------------+------------------------------------+ 638 | ecdsa-brainpool-regular | unavailable | 639 +---------------------------+------------------------------------+ 640 | ecdsa-brainpool-twisted | unavailable | 641 +---------------------------+------------------------------------+ 642 643- ``HASH_ALG``: This build flag enables the user to select the secure hash 644 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 645 The default value of this flag is ``sha256``. 646 647- ``LDFLAGS``: Extra user options appended to the linkers' command line in 648 addition to the one set by the build system. 649 650- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 651 output compiled into the build. This should be one of the following: 652 653 :: 654 655 0 (LOG_LEVEL_NONE) 656 10 (LOG_LEVEL_ERROR) 657 20 (LOG_LEVEL_NOTICE) 658 30 (LOG_LEVEL_WARNING) 659 40 (LOG_LEVEL_INFO) 660 50 (LOG_LEVEL_VERBOSE) 661 662 All log output up to and including the selected log level is compiled into 663 the build. The default value is 40 in debug builds and 20 in release builds. 664 665- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 666 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 667 provide trust that the code taking the measurements and recording them has 668 not been tampered with. 669 670 This option defaults to 0. 671 672- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 673 options to the compiler. An example usage: 674 675 .. code:: make 676 677 MARCH_DIRECTIVE := -march=armv8.5-a 678 679- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 680 options to the compiler currently supporting only of the options. 681 GCC documentation: 682 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 683 684 An example usage: 685 686 .. code:: make 687 688 HARDEN_SLS := 1 689 690 This option defaults to 0. 691 692- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 693 specifies a file that contains the Non-Trusted World private key in PEM 694 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 695 will be used to save the key. 696 697- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 698 optional. It is only needed if the platform makefile specifies that it 699 is required in order to build the ``fwu_fip`` target. 700 701- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 702 contents upon world switch. It can take either 0 (don't save and restore) or 703 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 704 wants the timer registers to be saved and restored. 705 706- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in 707 tb_fw_config device tree. This flag is defined only when 708 ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp. 709 710- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 711 for the BL image. It can be either 0 (include) or 1 (remove). The default 712 value is 0. 713 714- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 715 the underlying hardware is not a full PL011 UART but a minimally compliant 716 generic UART, which is a subset of the PL011. The driver will not access 717 any register that is not part of the SBSA generic UART specification. 718 Default value is 0 (a full PL011 compliant UART is present). 719 720- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 721 must be subdirectory of any depth under ``plat/``, and must contain a 722 platform makefile named ``platform.mk``. For example, to build TF-A for the 723 Arm Juno board, select PLAT=juno. 724 725- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 726 each core as well as the global context. The data includes the memory used 727 by each world and each privileged exception level. This build option is 728 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 729 730- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 731 instead of the normal boot flow. When defined, it must specify the entry 732 point address for the preloaded BL33 image. This option is incompatible with 733 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 734 over ``PRELOADED_BL33_BASE``. 735 736- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 737 vector address can be programmed or is fixed on the platform. It can take 738 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 739 programmable reset address, it is expected that a CPU will start executing 740 code directly at the right address, both on a cold and warm reset. In this 741 case, there is no need to identify the entrypoint on boot and the boot path 742 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 743 does not need to be implemented in this case. 744 745- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 746 possible for the PSCI power-state parameter: original and extended State-ID 747 formats. This flag if set to 1, configures the generic PSCI layer to use the 748 extended format. The default value of this flag is 0, which means by default 749 the original power-state format is used by the PSCI implementation. This flag 750 should be specified by the platform makefile and it governs the return value 751 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 752 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 753 set to 1 as well. 754 755- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 756 OS-initiated mode. This option defaults to 0. 757 758- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 759 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 760 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 761 NOTE: This flag enables use of IESB capability to reduce entry latency into 762 EL3 even when RAS error handling is not performed on the platform. Hence this 763 flag is recommended to be turned on Armv8.2 and later CPUs. 764 765- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 766 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 767 entrypoint) or 1 (CPU reset to BL31 entrypoint). 768 The default value is 0. 769 770- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 771 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 772 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 773 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 774 775- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 776 file that contains the ROT private key in PEM format or a PKCS11 URI and 777 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 778 accepted and it will be used to save the key. 779 780- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 781 certificate generation tool to save the keys used to establish the Chain of 782 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 783 784- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 785 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 786 target. 787 788- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 789 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 790 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 791 792- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 793 optional. It is only needed if the platform makefile specifies that it 794 is required in order to build the ``fwu_fip`` target. 795 796- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 797 Delegated Exception Interface to BL31 image. This defaults to ``0``. 798 799 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 800 set to ``1``. 801 802- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 803 isolated on separate memory pages. This is a trade-off between security and 804 memory usage. See "Isolating code and read-only data on separate memory 805 pages" section in :ref:`Firmware Design`. This flag is disabled by default 806 and affects all BL images. 807 808- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 809 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 810 allocated in RAM discontiguous from the loaded firmware image. When set, the 811 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 812 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 813 sections are placed in RAM immediately following the loaded firmware image. 814 815- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 816 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 817 discontiguous from loaded firmware images. When set, the platform need to 818 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 819 flag is disabled by default and NOLOAD sections are placed in RAM immediately 820 following the loaded firmware image. 821 822- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 823 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 824 UEFI+ACPI this can provide a certain amount of OS forward compatibility 825 with newer platforms that aren't ECAM compliant. 826 827- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 828 This build option is only valid if ``ARCH=aarch64``. The value should be 829 the path to the directory containing the SPD source, relative to 830 ``services/spd/``; the directory is expected to contain a makefile called 831 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 832 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 833 cannot be enabled when the ``SPM_MM`` option is enabled. 834 835- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 836 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 837 execution in BL1 just before handing over to BL31. At this point, all 838 firmware images have been loaded in memory, and the MMU and caches are 839 turned off. Refer to the "Debugging options" section for more details. 840 841- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 842 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 843 component runs at the EL3 exception level. The default value is ``0`` ( 844 disabled). This configuration supports pre-Armv8.4 platforms (aka not 845 implementing the ``FEAT_SEL2`` extension). 846 847- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 848 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 849 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 850 851- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 852 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 853 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 854 mechanism should be used. 855 856- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 857 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 858 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 859 extension. This is the default when enabling the SPM Dispatcher. When 860 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 861 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 862 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 863 extension). 864 865- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 866 Partition Manager (SPM) implementation. The default value is ``0`` 867 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 868 enabled (``SPD=spmd``). 869 870- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 871 description of secure partitions. The build system will parse this file and 872 package all secure partition blobs into the FIP. This file is not 873 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 874 875- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 876 secure interrupts (caught through the FIQ line). Platforms can enable 877 this directive if they need to handle such interruption. When enabled, 878 the FIQ are handled in monitor mode and non secure world is not allowed 879 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 880 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 881 882- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 883 Platforms can configure this if they need to lower the hardware 884 limit, for example due to asymmetric configuration or limitations of 885 software run at lower ELs. The default is the architectural maximum 886 of 2048 which should be suitable for most configurations, the 887 hardware will limit the effective VL to the maximum physically supported 888 VL. 889 890- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 891 Random Number Generator Interface to BL31 image. This defaults to ``0``. 892 893- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 894 Boot feature. When set to '1', BL1 and BL2 images include support to load 895 and verify the certificates and images in a FIP, and BL1 includes support 896 for the Firmware Update. The default value is '0'. Generation and inclusion 897 of certificates in the FIP and FWU_FIP depends upon the value of the 898 ``GENERATE_COT`` option. 899 900 .. warning:: 901 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 902 already exist in disk, they will be overwritten without further notice. 903 904- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 905 specifies a file that contains the Trusted World private key in PEM 906 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 907 it will be used to save the key. 908 909- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 910 synchronous, (see "Initializing a BL32 Image" section in 911 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 912 synchronous method) or 1 (BL32 is initialized using asynchronous method). 913 Default is 0. 914 915- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 916 routing model which routes non-secure interrupts asynchronously from TSP 917 to EL3 causing immediate preemption of TSP. The EL3 is responsible 918 for saving and restoring the TSP context in this routing model. The 919 default routing model (when the value is 0) is to route non-secure 920 interrupts to TSP allowing it to save its context and hand over 921 synchronously to EL3 via an SMC. 922 923 .. note:: 924 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 925 must also be set to ``1``. 926 927- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 928 internal-trusted-storage) as SP in tb_fw_config device tree. 929 930- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 931 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 932 this delay. It can take values in the range (0-15). Default value is ``0`` 933 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 934 Platforms need to explicitly update this value based on their requirements. 935 936- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 937 linker. When the ``LINKER`` build variable points to the armlink linker, 938 this flag is enabled automatically. To enable support for armlink, platforms 939 will have to provide a scatter file for the BL image. Currently, Tegra 940 platforms use the armlink support to compile BL3-1 images. 941 942- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 943 memory region in the BL memory map or not (see "Use of Coherent memory in 944 TF-A" section in :ref:`Firmware Design`). It can take the value 1 945 (Coherent memory region is included) or 0 (Coherent memory region is 946 excluded). Default is 1. 947 948- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 949 firmware configuration framework. This will move the io_policies into a 950 configuration device tree, instead of static structure in the code base. 951 952- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 953 at runtime using fconf. If this flag is enabled, COT descriptors are 954 statically captured in tb_fw_config file in the form of device tree nodes 955 and properties. Currently, COT descriptors used by BL2 are moved to the 956 device tree and COT descriptors used by BL1 are retained in the code 957 base statically. 958 959- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 960 runtime using firmware configuration framework. The platform specific SDEI 961 shared and private events configuration is retrieved from device tree rather 962 than static C structures at compile time. This is only supported if 963 SDEI_SUPPORT build flag is enabled. 964 965- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 966 and Group1 secure interrupts using the firmware configuration framework. The 967 platform specific secure interrupt property descriptor is retrieved from 968 device tree in runtime rather than depending on static C structure at compile 969 time. 970 971- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 972 This feature creates a library of functions to be placed in ROM and thus 973 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 974 is 0. 975 976- ``V``: Verbose build. If assigned anything other than 0, the build commands 977 are printed. Default is 0. 978 979- ``VERSION_STRING``: String used in the log output for each TF-A image. 980 Defaults to a string formed by concatenating the version number, build type 981 and build string. 982 983- ``W``: Warning level. Some compiler warning options of interest have been 984 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 985 each level enabling more warning options. Default is 0. 986 987 This option is closely related to the ``E`` option, which enables 988 ``-Werror``. 989 990 - ``W=0`` (default) 991 992 Enables a wide assortment of warnings, most notably ``-Wall`` and 993 ``-Wextra``, as well as various bad practices and things that are likely to 994 result in errors. Includes some compiler specific flags. No warnings are 995 expected at this level for any build. 996 997 - ``W=1`` 998 999 Enables warnings we want the generic build to include but are too time 1000 consuming to fix at the moment. It re-enables warnings taken out for 1001 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1002 to eventually be merged into ``W=0``. Some warnings are expected on some 1003 builds, but new contributions should not introduce new ones. 1004 1005 - ``W=2`` (recommended) 1006 1007 Enables warnings we want the generic build to include but cannot be enabled 1008 due to external libraries. This level is expected to eventually be merged 1009 into ``W=0``. Lots of warnings are expected, primarily from external 1010 libraries like zlib and compiler-rt, but new controbutions should not 1011 introduce new ones. 1012 1013 - ``W=3`` 1014 1015 Enables warnings that are informative but not necessary and generally too 1016 verbose and frequently ignored. A very large number of warnings are 1017 expected. 1018 1019 The exact set of warning flags depends on the compiler and TF-A warning 1020 level, however they are all succinctly set in the top-level Makefile. Please 1021 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1022 individual flags. 1023 1024- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1025 the CPU after warm boot. This is applicable for platforms which do not 1026 require interconnect programming to enable cache coherency (eg: single 1027 cluster platforms). If this option is enabled, then warm boot path 1028 enables D-caches immediately after enabling MMU. This option defaults to 0. 1029 1030- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1031 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1032 default value of this flag is ``no``. Note this option must be enabled only 1033 for ARM architecture greater than Armv8.5-A. 1034 1035- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1036 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1037 The default value of this flag is ``0``. 1038 1039 ``AT`` speculative errata workaround disables stage1 page table walk for 1040 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1041 produces either the correct result or failure without TLB allocation. 1042 1043 This boolean option enables errata for all below CPUs. 1044 1045 +---------+--------------+-------------------------+ 1046 | Errata | CPU | Workaround Define | 1047 +=========+==============+=========================+ 1048 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1049 +---------+--------------+-------------------------+ 1050 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1051 +---------+--------------+-------------------------+ 1052 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1053 +---------+--------------+-------------------------+ 1054 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1055 +---------+--------------+-------------------------+ 1056 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1057 +---------+--------------+-------------------------+ 1058 1059 .. note:: 1060 This option is enabled by build only if platform sets any of above defines 1061 mentioned in ’Workaround Define' column in the table. 1062 If this option is enabled for the EL3 software then EL2 software also must 1063 implement this workaround due to the behaviour of the errata mentioned 1064 in new SDEN document which will get published soon. 1065 1066- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1067 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1068 This flag is disabled by default. 1069 1070- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1071 host machine where a custom installation of OpenSSL is located, which is used 1072 to build the certificate generation, firmware encryption and FIP tools. If 1073 this option is not set, the default OS installation will be used. 1074 1075- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1076 functions that wait for an arbitrary time length (udelay and mdelay). The 1077 default value is 0. 1078 1079- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1080 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1081 optional architectural feature for AArch64. This flag can take the values 1082 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1083 and it is automatically disabled when the target architecture is AArch32. 1084 1085- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1086 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1087 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1088 feature for AArch64. This flag can take the values 0 to 2, to align with the 1089 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1090 disabled when the target architecture is AArch32. 1091 1092- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1093 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1094 but unused). This feature is available if trace unit such as ETMv4.x, and 1095 ETE(extending ETM feature) is implemented. This flag can take the values 1096 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0. 1097 1098- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1099 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1100 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1101 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1102 1103- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1104 ``plat_can_cmo`` which will return zero if cache management operations should 1105 be skipped and non-zero otherwise. By default, this option is disabled which 1106 means platform hook won't be checked and CMOs will always be performed when 1107 related functions are called. 1108 1109- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1110 firmware interface for the BL31 image. By default its disabled (``0``). 1111 1112- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1113 errata mitigation for platforms with a non-arm interconnect using the errata 1114 ABI. By default its disabled (``0``). 1115 1116- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1117 driver(s). By default it is disabled (``0``) because it constitutes an attack 1118 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1119 This option should only be enabled on a need basis if there is a use case for 1120 reading characters from the console. 1121 1122GICv3 driver options 1123-------------------- 1124 1125GICv3 driver files are included using directive: 1126 1127``include drivers/arm/gic/v3/gicv3.mk`` 1128 1129The driver can be configured with the following options set in the platform 1130makefile: 1131 1132- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1133 Enabling this option will add runtime detection support for the 1134 GIC-600, so is safe to select even for a GIC500 implementation. 1135 This option defaults to 0. 1136 1137- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1138 for GIC-600 AE. Enabling this option will introduce support to initialize 1139 the FMU. Platforms should call the init function during boot to enable the 1140 FMU and its safety mechanisms. This option defaults to 0. 1141 1142- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1143 functionality. This option defaults to 0 1144 1145- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1146 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1147 functions. This is required for FVP platform which need to simulate GIC save 1148 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1149 1150- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1151 This option defaults to 0. 1152 1153- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1154 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1155 1156Debugging options 1157----------------- 1158 1159To compile a debug version and make the build more verbose use 1160 1161.. code:: shell 1162 1163 make PLAT=<platform> DEBUG=1 V=1 all 1164 1165AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1166(for example Arm-DS) might not support this and may need an older version of 1167DWARF symbols to be emitted by GCC. This can be achieved by using the 1168``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1169the version to 4 is recommended for Arm-DS. 1170 1171When debugging logic problems it might also be useful to disable all compiler 1172optimizations by using ``-O0``. 1173 1174.. warning:: 1175 Using ``-O0`` could cause output images to be larger and base addresses 1176 might need to be recalculated (see the **Memory layout on Arm development 1177 platforms** section in the :ref:`Firmware Design`). 1178 1179Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1180``LDFLAGS``: 1181 1182.. code:: shell 1183 1184 CFLAGS='-O0 -gdwarf-2' \ 1185 make PLAT=<platform> DEBUG=1 V=1 all 1186 1187Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1188ignored as the linker is called directly. 1189 1190It is also possible to introduce an infinite loop to help in debugging the 1191post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1192``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1193section. In this case, the developer may take control of the target using a 1194debugger when indicated by the console output. When using Arm-DS, the following 1195commands can be used: 1196 1197:: 1198 1199 # Stop target execution 1200 interrupt 1201 1202 # 1203 # Prepare your debugging environment, e.g. set breakpoints 1204 # 1205 1206 # Jump over the debug loop 1207 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1208 1209 # Resume execution 1210 continue 1211 1212.. _build_options_experimental: 1213 1214Experimental build options 1215--------------------------- 1216 1217Common build options 1218~~~~~~~~~~~~~~~~~~~~ 1219 1220- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1221 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1222 the measurements and recording them as per `PSA DRTM specification`_. For 1223 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1224 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1225 should have mechanism to authenticate BL31. This option defaults to 0. 1226 1227- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1228 Management Extension. This flag can take the values 0 to 2, to align with 1229 the ``FEATURE_DETECTION`` mechanism. Default value is 0. 1230 1231- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1232 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1233 registers so are enabled together. Using this option without 1234 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1235 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1236 superset of SVE. SME is an optional architectural feature for AArch64. 1237 At this time, this build option cannot be used on systems that have 1238 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1239 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 1240 mechanism. Default is 0. 1241 1242- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1243 version 2 (SME2) for the non-secure world only. SME2 is an optional 1244 architectural feature for AArch64. 1245 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1246 accesses will still be trapped. This flag can take the values 0 to 2, to 1247 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 1248 1249- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1250 Extension for secure world. Used along with SVE and FPU/SIMD. 1251 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1252 Default is 0. 1253 1254- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1255 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1256 for logical partitions in EL3, managed by the SPMD as defined in the 1257 FF-A v1.2 specification. This flag is disabled by default. This flag 1258 must not be used if ``SPMC_AT_EL3`` is enabled. 1259 1260- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1261 detection mechanism. It detects whether the Architectural features enabled 1262 through feature specific build flags are supported by the PE or not by 1263 validating them either at boot phase or at runtime based on the value 1264 possessed by the feature flag (0 to 2) and report error messages at an early 1265 stage. This flag will also enable errata ordering checking for ``DEBUG`` 1266 builds. 1267 1268 This prevents and benefits us from EL3 runtime exceptions during context save 1269 and restore routines guarded by these build flags. Henceforth validating them 1270 before their usage provides more control on the actions taken under them. 1271 1272 The mechanism permits the build flags to take values 0, 1 or 2 and 1273 evaluates them accordingly. 1274 1275 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 1276 1277 :: 1278 1279 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 1280 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 1281 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 1282 1283 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 1284 0, feature is disabled statically during compilation. If it is defined as 1, 1285 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 1286 implemented by the PE, a hard panic is generated. Finally, if the flag is set 1287 to 2, feature is validated at runtime. 1288 1289 Note that the entire implementation is divided into two phases, wherein as 1290 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 1291 supported and is planned to be handled explicilty in phase-2 implementation. 1292 1293 ``FEATURE_DETECTION`` macro is disabled by default. Platforms can explicitly 1294 make use of this by mechanism, by enabling it to validate whether they have 1295 set their build flags properly at an early phase. 1296 1297- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1298 The platform will use PSA compliant Crypto APIs during authentication and 1299 image measurement process by enabling this option. It uses APIs defined as 1300 per the `PSA Crypto API specification`_. This feature is only supported if 1301 using MbedTLS 3.x version. It is disabled (``0``) by default. 1302 1303- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1304 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1305 This defaults to ``0``. Current implementation follows the Firmware Handoff 1306 specification v0.9. 1307 1308- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1309 interface through BL31 as a SiP SMC function. 1310 Default is disabled (0). 1311 1312Firmware update options 1313~~~~~~~~~~~~~~~~~~~~~~~ 1314 1315- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1316 `PSA FW update specification`_. The default value is 0. 1317 PSA firmware update implementation has few limitations, such as: 1318 1319 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1320 be updated, then it should be done through another platform-defined 1321 mechanism. 1322 1323 - It assumes the platform's hardware supports CRC32 instructions. 1324 1325- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1326 in defining the firmware update metadata structure. This flag is by default 1327 set to '2'. 1328 1329- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1330 firmware bank. Each firmware bank must have the same number of images as per 1331 the `PSA FW update specification`_. 1332 This flag is used in defining the firmware update metadata structure. This 1333 flag is by default set to '1'. 1334 1335-------------- 1336 1337*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 1338 1339.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1340.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1341.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1342.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1343.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1344.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1345.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1346