1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 49 SP nodes in tb_fw_config. 50 51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 53 54- ``BL2``: This is an optional build option which specifies the path to BL2 55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 56 built. 57 58- ``BL2U``: This is an optional build option which specifies the path to 59 BL2U image. In this case, the BL2U in TF-A will not be built. 60 61- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 63 entrypoint) or 1 (CPU reset to BL2 entrypoint). 64 The default value is 0. 65 66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 68 true in a 4-world system where RESET_TO_BL2 is 0. 69 70- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 72 73- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 75 the RW sections in RAM, while leaving the RO sections in place. This option 76 enable this use-case. For now, this option is only supported 77 when RESET_TO_BL2 is set to '1'. 78 79- ``BL31``: This is an optional build option which specifies the path to 80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 81 be built. 82 83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 84 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 85 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 86 87- ``BL32``: This is an optional build option which specifies the path to 88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 89 be built. 90 91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 92 Trusted OS Extra1 image for the ``fip`` target. 93 94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 95 Trusted OS Extra2 image for the ``fip`` target. 96 97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 98 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 99 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 100 101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 102 ``fip`` target in case TF-A BL2 is used. 103 104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 105 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 106 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 107 108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 110 If enabled, it is needed to use a compiler that supports the option 111 ``-mbranch-protection``. Selects the branch protection features to use: 112- 0: Default value turns off all types of branch protection 113- 1: Enables all types of branch protection features 114- 2: Return address signing to its standard level 115- 3: Extend the signing to include leaf functions 116- 4: Turn on branch target identification mechanism 117 118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 119 and resulting PAuth/BTI features. 120 121 +-------+--------------+-------+-----+ 122 | Value | GCC option | PAuth | BTI | 123 +=======+==============+=======+=====+ 124 | 0 | none | N | N | 125 +-------+--------------+-------+-----+ 126 | 1 | standard | Y | Y | 127 +-------+--------------+-------+-----+ 128 | 2 | pac-ret | Y | N | 129 +-------+--------------+-------+-----+ 130 | 3 | pac-ret+leaf | Y | N | 131 +-------+--------------+-------+-----+ 132 | 4 | bti | N | Y | 133 +-------+--------------+-------+-----+ 134 135 This option defaults to 0. 136 Note that Pointer Authentication is enabled for Non-secure world 137 irrespective of the value of this option if the CPU supports it. 138 139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 140 compilation of each build. It must be set to a C string (including quotes 141 where applicable). Defaults to a string that contains the time and date of 142 the compilation. 143 144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 145 build to be uniquely identified. Defaults to the current git commit id. 146 147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 148 149- ``CFLAGS``: Extra user options appended on the compiler's command line in 150 addition to the options set by the build system. 151 152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 153 release several CPUs out of reset. It can take either 0 (several CPUs may be 154 brought up) or 1 (only one CPU will ever be brought up during cold reset). 155 Default is 0. If the platform always brings up a single CPU, there is no 156 need to distinguish between primary and secondary CPUs and the boot path can 157 be optimised. The ``plat_is_my_cpu_primary()`` and 158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 159 to be implemented in this case. 160 161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 162 Defaults to ``tbbr``. 163 164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 165 register state when an unexpected exception occurs during execution of 166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 167 this is only enabled for a debug build of the firmware. 168 169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 170 certificate generation tool to create new keys in case no valid keys are 171 present or specified. Allowed options are '0' or '1'. Default is '1'. 172 173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 174 the AArch32 system registers to be included when saving and restoring the 175 CPU context. The option must be set to 0 for AArch64-only platforms (that 176 is on hardware that does not implement AArch32, or at least not at EL1 and 177 higher ELs). Default value is 1. 178 179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 180 registers to be included when saving and restoring the CPU context. Default 181 is 0. 182 183- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 184 registers in cpu context. This must be enabled, if the platform wants to use 185 this feature in the Secure world and MTE is enabled at ELX. This flag can 186 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 187 Default value is 0. 188 189- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 190 registers to be saved/restored when entering/exiting an EL2 execution 191 context. This flag can take values 0 to 2, to align with the 192 ``FEATURE_DETECTION`` mechanism. Default value is 0. 193 194- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 195 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 196 to be included when saving and restoring the CPU context as part of world 197 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 198 mechanism. Default value is 0. 199 200 Note that Pointer Authentication is enabled for Non-secure world irrespective 201 of the value of this flag if the CPU supports it. 202 203- ``DEBUG``: Chooses between a debug and release build. It can take either 0 204 (release) or 1 (debug) as values. 0 is the default. 205 206- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 207 authenticated decryption algorithm to be used to decrypt firmware/s during 208 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 209 this flag is ``none`` to disable firmware decryption which is an optional 210 feature as per TBBR. 211 212- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 213 of the binary image. If set to 1, then only the ELF image is built. 214 0 is the default. 215 216- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 217 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 218 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 219 mechanism. Default is ``0``. 220 221- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 222 Board Boot authentication at runtime. This option is meant to be enabled only 223 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 224 flag has to be enabled. 0 is the default. 225 226- ``E``: Boolean option to make warnings into errors. Default is 1. 227 228 When specifying higher warnings levels (``W=1`` and higher), this option 229 defaults to 0. This is done to encourage contributors to use them, as they 230 are expected to produce warnings that would otherwise fail the build. New 231 contributions are still expected to build with ``W=0`` and ``E=1`` (the 232 default). 233 234- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 235 the normal boot flow. It must specify the entry point address of the EL3 236 payload. Please refer to the "Booting an EL3 payload" section for more 237 details. 238 239- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 240 (also known as group 1 counters). These are implementation-defined counters, 241 and as such require additional platform configuration. Default is 0. 242 243- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 244 allows platforms with auxiliary counters to describe them via the 245 ``HW_CONFIG`` device tree blob. Default is 0. 246 247- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 248 are compiled out. For debug builds, this option defaults to 1, and calls to 249 ``assert()`` are left in place. For release builds, this option defaults to 0 250 and calls to ``assert()`` function are compiled out. This option can be set 251 independently of ``DEBUG``. It can also be used to hide any auxiliary code 252 that is only required for the assertion and does not fit in the assertion 253 itself. 254 255- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 256 dumps or not. It is supported in both AArch64 and AArch32. However, in 257 AArch32 the format of the frame records are not defined in the AAPCS and they 258 are defined by the implementation. This implementation of backtrace only 259 supports the format used by GCC when T32 interworking is disabled. For this 260 reason enabling this option in AArch32 will force the compiler to only 261 generate A32 code. This option is enabled by default only in AArch64 debug 262 builds, but this behaviour can be overridden in each platform's Makefile or 263 in the build command line. 264 265- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 266 extensions. This flag can take the values 0 to 2, to align with the 267 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature 268 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 269 and this option can be used to enable this feature on those systems as well. 270 This flag can take the values 0 to 2, the default is 0. 271 272- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 273 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 274 onwards. This flag can take the values 0 to 2, to align with the 275 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 276 277- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 278 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 279 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 280 optional feature available on Arm v8.0 onwards. This flag can take values 281 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 282 Default value is ``0``. 283 284- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 285 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 286 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 287 and upwards. This flag can take the values 0 to 2, to align with the 288 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 289 290- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 291 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 292 Physical Offset register) during EL2 to EL3 context save/restore operations. 293 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 294 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 295 mechanism. Default value is ``0``. 296 297- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 298 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 299 Read Trap Register) during EL2 to EL3 context save/restore operations. 300 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 301 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 302 mechanism. Default value is ``0``. 303 304- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 305 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 306 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 307 mandatory architectural feature and is enabled from v8.7 and upwards. This 308 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 309 mechanism. Default value is ``0``. 310 311- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for 312 ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to 313 memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural 314 feature available from v8.9 and upwards. This flag can take the values 0 to 315 2, to align with the ``FEATURE_DETECTION`` mechanism. Default value is 316 ``0``. 317 318- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 319 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 320 permission fault for any privileged data access from EL1/EL2 to virtual 321 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 322 mandatory architectural feature and is enabled from v8.1 and upwards. This 323 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 324 mechanism. Default value is ``0``. 325 326- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 327 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 328 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 329 mechanism. Default value is ``0``. 330 331- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 332 extension. This feature is only supported in AArch64 state. This flag can 333 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 334 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 335 Armv8.5 onwards. 336 337- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 338 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 339 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 340 later CPUs. It is enabled from v8.5 and upwards and if needed can be 341 overidden from platforms explicitly. 342 343- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 344 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 345 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 346 mechanism. Default is ``0``. 347 348- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 349 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 350 available on Arm v8.6. This flag can take values 0 to 2, to align with the 351 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 352 353 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 354 delayed by the amount of value in ``TWED_DELAY``. 355 356- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 357 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 358 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 359 architectural feature and is enabled from v8.1 and upwards. It can take 360 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 361 Default value is ``0``. 362 363- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 364 allow access to TCR2_EL2 (extended translation control) from EL2 as 365 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 366 mandatory architectural feature and is enabled from v8.9 and upwards. This 367 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 368 mechanism. Default value is ``0``. 369 370- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 371 at EL2 and below, and context switch relevant registers. This flag 372 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 373 mechanism. Default value is ``0``. 374 375- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 376 at EL2 and below, and context switch relevant registers. This flag 377 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 378 mechanism. Default value is ``0``. 379 380- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 381 at EL2 and below, and context switch relevant registers. This flag 382 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 383 mechanism. Default value is ``0``. 384 385- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 386 at EL2 and below, and context switch relevant registers. This flag 387 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 388 mechanism. Default value is ``0``. 389 390- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 391 allow use of Guarded Control Stack from EL2 as well as adding the GCS 392 registers to the EL2 context save/restore operations. This flag can take 393 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 394 Default value is ``0``. 395 396- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 397 support in GCC for TF-A. This option is currently only supported for 398 AArch64. Default is 0. 399 400- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 401 feature. MPAM is an optional Armv8.4 extension that enables various memory 402 system components and resources to define partitions; software running at 403 various ELs can assign themselves to desired partition to control their 404 performance aspects. 405 406 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 407 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 408 access their own MPAM registers without trapping into EL3. This option 409 doesn't make use of partitioning in EL3, however. Platform initialisation 410 code should configure and use partitions in EL3 as required. This option 411 defaults to ``2`` since MPAM is enabled by default for NS world only. 412 The flag is automatically disabled when the target 413 architecture is AArch32. 414 415- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 416 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 417 firmware to detect and limit high activity events to assist in SoC processor 418 power domain dynamic power budgeting and limit the triggering of whole-rail 419 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 420 421- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 422 allows platforms with cores supporting MPMM to describe them via the 423 ``HW_CONFIG`` device tree blob. Default is 0. 424 425- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 426 support within generic code in TF-A. This option is currently only supported 427 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 428 in BL32 (SP_min) for AARCH32. Default is 0. 429 430- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 431 Measurement Framework(PMF). Default is 0. 432 433- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 434 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 435 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 436 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 437 software. 438 439- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 440 Management Extension. This flag can take the values 0 to 2, to align with 441 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently 442 an experimental feature. 443 444- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 445 instrumentation which injects timestamp collection points into TF-A to 446 allow runtime performance to be measured. Currently, only PSCI is 447 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 448 as well. Default is 0. 449 450- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 451 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 452 registers so are enabled together. Using this option without 453 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 454 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 455 superset of SVE. SME is an optional architectural feature for AArch64 456 and TF-A support is experimental. At this time, this build option cannot be 457 used on systems that have SPD=spmd/SPM_MM and atempting to build with this 458 option will fail. This flag can take the values 0 to 2, to align with the 459 ``FEATURE_DETECTION`` mechanism. Default is 0. 460 461- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 462 version 2 (SME2) for the non-secure world only. SME2 is an optional 463 architectural feature for AArch64 and TF-A support is experimental. 464 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 465 accesses will still be trapped. This flag can take the values 0 to 2, to 466 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 467 468- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 469 Extension for secure world. Used along with SVE and FPU/SIMD. 470 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 471 This is experimental. Default is 0. 472 473- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 474 extensions. This is an optional architectural feature for AArch64. 475 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 476 mechanism. The default is 2 but is automatically disabled when the target 477 architecture is AArch32. 478 479- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 480 (SVE) for the Non-secure world only. SVE is an optional architectural feature 481 for AArch64. Note that when SVE is enabled for the Non-secure world, access 482 to SIMD and floating-point functionality from the Secure world is disabled by 483 default and controlled with ENABLE_SVE_FOR_SWD. 484 This is to avoid corruption of the Non-secure world data in the Z-registers 485 which are aliased by the SIMD and FP registers. The build option is not 486 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 487 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 488 enabled. This flag can take the values 0 to 2, to align with the 489 ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be 490 used on systems that have SPM_MM enabled. The default is 1. 491 492- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 493 SVE is an optional architectural feature for AArch64. Note that this option 494 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 495 automatically disabled when the target architecture is AArch32. 496 497- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 498 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 499 default value is set to "none". "strong" is the recommended stack protection 500 level if this feature is desired. "none" disables the stack protection. For 501 all values other than "none", the ``plat_get_stack_protector_canary()`` 502 platform hook needs to be implemented. The value is passed as the last 503 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 504 505- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 506 flag depends on ``DECRYPTION_SUPPORT`` build flag. 507 508- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 509 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 510 511- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 512 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 513 on ``DECRYPTION_SUPPORT`` build flag. 514 515- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 516 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 517 build flag. 518 519- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 520 deprecated platform APIs, helper functions or drivers within Trusted 521 Firmware as error. It can take the value 1 (flag the use of deprecated 522 APIs as error) or 0. The default is 0. 523 524- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 525 configure an Arm® Ethos™-N NPU. To use this service the target platform's 526 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 527 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 528 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 529 530- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 531 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 532 ``TRUSTED_BOARD_BOOT`` to be enabled. 533 534- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 535 (```ethosn.bin```). This firmware image will be included in the FIP and 536 loaded at runtime. 537 538- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 539 targeted at EL3. When set ``0`` (default), no exceptions are expected or 540 handled at EL3, and a panic will result. The exception to this rule is when 541 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 542 occuring during normal world execution, are trapped to EL3. Any exception 543 trapped during secure world execution are trapped to the SPMC. This is 544 supported only for AArch64 builds. 545 546- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 547 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 548 Default value is 40 (LOG_LEVEL_INFO). 549 550- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 551 injection from lower ELs, and this build option enables lower ELs to use 552 Error Records accessed via System Registers to inject faults. This is 553 applicable only to AArch64 builds. 554 555 This feature is intended for testing purposes only, and is advisable to keep 556 disabled for production images. 557 558- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 559 detection mechanism. It detects whether the Architectural features enabled 560 through feature specific build flags are supported by the PE or not by 561 validating them either at boot phase or at runtime based on the value 562 possessed by the feature flag (0 to 2) and report error messages at an early 563 stage. This flag will also enable errata ordering checking for ``DEBUG`` 564 builds. 565 566 This prevents and benefits us from EL3 runtime exceptions during context save 567 and restore routines guarded by these build flags. Henceforth validating them 568 before their usage provides more control on the actions taken under them. 569 570 The mechanism permits the build flags to take values 0, 1 or 2 and 571 evaluates them accordingly. 572 573 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 574 575 :: 576 577 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 578 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 579 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 580 581 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 582 0, feature is disabled statically during compilation. If it is defined as 1, 583 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 584 implemented by the PE, a hard panic is generated. Finally, if the flag is set 585 to 2, feature is validated at runtime. 586 587 Note that the entire implementation is divided into two phases, wherein as 588 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 589 supported and is planned to be handled explicilty in phase-2 implementation. 590 591 FEATURE_DETECTION macro is disabled by default, and is currently an 592 experimental procedure. Platforms can explicitly make use of this by 593 mechanism, by enabling it to validate whether they have set their build flags 594 properly at an early phase. 595 596- ``FIP_NAME``: This is an optional build option which specifies the FIP 597 filename for the ``fip`` target. Default is ``fip.bin``. 598 599- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 600 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 601 602- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 603 604 :: 605 606 0: Encryption is done with Secret Symmetric Key (SSK) which is common 607 for a class of devices. 608 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 609 unique per device. 610 611 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 612 613- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 614 tool to create certificates as per the Chain of Trust described in 615 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 616 include the certificates in the FIP and FWU_FIP. Default value is '0'. 617 618 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 619 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 620 the corresponding certificates, and to include those certificates in the 621 FIP and FWU_FIP. 622 623 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 624 images will not include support for Trusted Board Boot. The FIP will still 625 include the corresponding certificates. This FIP can be used to verify the 626 Chain of Trust on the host machine through other mechanisms. 627 628 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 629 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 630 will not include the corresponding certificates, causing a boot failure. 631 632- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 633 inherent support for specific EL3 type interrupts. Setting this build option 634 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 635 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 636 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 637 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 638 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 639 the Secure Payload interrupts needs to be synchronously handed over to Secure 640 EL1 for handling. The default value of this option is ``0``, which means the 641 Group 0 interrupts are assumed to be handled by Secure EL1. 642 643- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 644 Interrupts, resulting from errors in NS world, will be always trapped in 645 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 646 will be trapped in the current exception level (or in EL1 if the current 647 exception level is EL0). 648 649- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 650 software operations are required for CPUs to enter and exit coherency. 651 However, newer systems exist where CPUs' entry to and exit from coherency 652 is managed in hardware. Such systems require software to only initiate these 653 operations, and the rest is managed in hardware, minimizing active software 654 management. In such systems, this boolean option enables TF-A to carry out 655 build and run-time optimizations during boot and power management operations. 656 This option defaults to 0 and if it is enabled, then it implies 657 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 658 659 If this flag is disabled while the platform which TF-A is compiled for 660 includes cores that manage coherency in hardware, then a compilation error is 661 generated. This is based on the fact that a system cannot have, at the same 662 time, cores that manage coherency in hardware and cores that don't. In other 663 words, a platform cannot have, at the same time, cores that require 664 ``HW_ASSISTED_COHERENCY=1`` and cores that require 665 ``HW_ASSISTED_COHERENCY=0``. 666 667 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 668 translation library (xlat tables v2) must be used; version 1 of translation 669 library is not supported. 670 671- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 672 implementation defined system register accesses from lower ELs. Default 673 value is ``0``. 674 675- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 676 bottom, higher addresses at the top. This build flag can be set to '1' to 677 invert this behavior. Lower addresses will be printed at the top and higher 678 addresses at the bottom. 679 680- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 681 used for generating the PKCS keys and subsequent signing of the certificate. 682 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 683 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 684 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 685 compatibility. The default value of this flag is ``rsa`` which is the TBBR 686 compliant PKCS#1 RSA 2.1 scheme. 687 688- ``KEY_SIZE``: This build flag enables the user to select the key size for 689 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 690 depend on the chosen algorithm and the cryptographic module. 691 692 +---------------------------+------------------------------------+ 693 | KEY_ALG | Possible key sizes | 694 +===========================+====================================+ 695 | rsa | 1024 , 2048 (default), 3072, 4096* | 696 +---------------------------+------------------------------------+ 697 | ecdsa | 256 (default), 384 | 698 +---------------------------+------------------------------------+ 699 | ecdsa-brainpool-regular | unavailable | 700 +---------------------------+------------------------------------+ 701 | ecdsa-brainpool-twisted | unavailable | 702 +---------------------------+------------------------------------+ 703 704 705 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 706 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 707 708- ``HASH_ALG``: This build flag enables the user to select the secure hash 709 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 710 The default value of this flag is ``sha256``. 711 712- ``LDFLAGS``: Extra user options appended to the linkers' command line in 713 addition to the one set by the build system. 714 715- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 716 output compiled into the build. This should be one of the following: 717 718 :: 719 720 0 (LOG_LEVEL_NONE) 721 10 (LOG_LEVEL_ERROR) 722 20 (LOG_LEVEL_NOTICE) 723 30 (LOG_LEVEL_WARNING) 724 40 (LOG_LEVEL_INFO) 725 50 (LOG_LEVEL_VERBOSE) 726 727 All log output up to and including the selected log level is compiled into 728 the build. The default value is 40 in debug builds and 20 in release builds. 729 730- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 731 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 732 provide trust that the code taking the measurements and recording them has 733 not been tampered with. 734 735 This option defaults to 0. 736 737- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 738 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 739 the measurements and recording them as per `PSA DRTM specification`_. For 740 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 741 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 742 should have mechanism to authenticate BL31. This is an experimental feature. 743 744 This option defaults to 0. 745 746- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 747 options to the compiler. An example usage: 748 749 .. code:: make 750 751 MARCH_DIRECTIVE := -march=armv8.5-a 752 753- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 754 specifies a file that contains the Non-Trusted World private key in PEM 755 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 756 will be used to save the key. 757 758- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 759 optional. It is only needed if the platform makefile specifies that it 760 is required in order to build the ``fwu_fip`` target. 761 762- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 763 contents upon world switch. It can take either 0 (don't save and restore) or 764 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 765 wants the timer registers to be saved and restored. 766 767- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in 768 tb_fw_config device tree. This flag is defined only when 769 ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp. 770 771- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 772 for the BL image. It can be either 0 (include) or 1 (remove). The default 773 value is 0. 774 775- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 776 the underlying hardware is not a full PL011 UART but a minimally compliant 777 generic UART, which is a subset of the PL011. The driver will not access 778 any register that is not part of the SBSA generic UART specification. 779 Default value is 0 (a full PL011 compliant UART is present). 780 781- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 782 must be subdirectory of any depth under ``plat/``, and must contain a 783 platform makefile named ``platform.mk``. For example, to build TF-A for the 784 Arm Juno board, select PLAT=juno. 785 786- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 787 instead of the normal boot flow. When defined, it must specify the entry 788 point address for the preloaded BL33 image. This option is incompatible with 789 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 790 over ``PRELOADED_BL33_BASE``. 791 792- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 793 vector address can be programmed or is fixed on the platform. It can take 794 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 795 programmable reset address, it is expected that a CPU will start executing 796 code directly at the right address, both on a cold and warm reset. In this 797 case, there is no need to identify the entrypoint on boot and the boot path 798 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 799 does not need to be implemented in this case. 800 801- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 802 possible for the PSCI power-state parameter: original and extended State-ID 803 formats. This flag if set to 1, configures the generic PSCI layer to use the 804 extended format. The default value of this flag is 0, which means by default 805 the original power-state format is used by the PSCI implementation. This flag 806 should be specified by the platform makefile and it governs the return value 807 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 808 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 809 set to 1 as well. 810 811- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 812 OS-initiated mode. This option defaults to 0. 813 814- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features 815 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 816 or later CPUs. This flag can take the values 0 to 2, to align with the 817 ``FEATURE_DETECTION`` mechanism. 818 819- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors 820 originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``, 821 ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``. 822 823- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 824 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 825 entrypoint) or 1 (CPU reset to BL31 entrypoint). 826 The default value is 0. 827 828- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 829 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 830 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 831 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 832 833- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 834 file that contains the ROT private key in PEM format or a PKCS11 URI and 835 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 836 accepted and it will be used to save the key. 837 838- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 839 certificate generation tool to save the keys used to establish the Chain of 840 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 841 842- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 843 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 844 target. 845 846- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 847 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 848 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 849 850- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 851 optional. It is only needed if the platform makefile specifies that it 852 is required in order to build the ``fwu_fip`` target. 853 854- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 855 Delegated Exception Interface to BL31 image. This defaults to ``0``. 856 857 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 858 set to ``1``. 859 860- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 861 isolated on separate memory pages. This is a trade-off between security and 862 memory usage. See "Isolating code and read-only data on separate memory 863 pages" section in :ref:`Firmware Design`. This flag is disabled by default 864 and affects all BL images. 865 866- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 867 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 868 allocated in RAM discontiguous from the loaded firmware image. When set, the 869 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 870 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 871 sections are placed in RAM immediately following the loaded firmware image. 872 873- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 874 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 875 discontiguous from loaded firmware images. When set, the platform need to 876 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 877 flag is disabled by default and NOLOAD sections are placed in RAM immediately 878 following the loaded firmware image. 879 880- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 881 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 882 UEFI+ACPI this can provide a certain amount of OS forward compatibility 883 with newer platforms that aren't ECAM compliant. 884 885- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 886 This build option is only valid if ``ARCH=aarch64``. The value should be 887 the path to the directory containing the SPD source, relative to 888 ``services/spd/``; the directory is expected to contain a makefile called 889 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 890 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 891 cannot be enabled when the ``SPM_MM`` option is enabled. 892 893- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 894 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 895 execution in BL1 just before handing over to BL31. At this point, all 896 firmware images have been loaded in memory, and the MMU and caches are 897 turned off. Refer to the "Debugging options" section for more details. 898 899- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 900 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 901 component runs at the EL3 exception level. The default value is ``0`` ( 902 disabled). This configuration supports pre-Armv8.4 platforms (aka not 903 implementing the ``FEAT_SEL2`` extension). This is an experimental feature. 904 905- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 906 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 907 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 908 909- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 910 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 911 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 912 mechanism should be used. 913 914- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 915 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 916 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 917 extension. This is the default when enabling the SPM Dispatcher. When 918 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 919 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 920 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 921 extension). 922 923- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 924 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 925 for logical partitions in EL3, managed by the SPMD as defined in the FF-A 926 1.2 specification. This flag is disabled by default. This flag must not be 927 used if ``SPMC_AT_EL3`` is enabled. This is an experimental feature. 928 929- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 930 Partition Manager (SPM) implementation. The default value is ``0`` 931 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 932 enabled (``SPD=spmd``). 933 934- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 935 description of secure partitions. The build system will parse this file and 936 package all secure partition blobs into the FIP. This file is not 937 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 938 939- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 940 secure interrupts (caught through the FIQ line). Platforms can enable 941 this directive if they need to handle such interruption. When enabled, 942 the FIQ are handled in monitor mode and non secure world is not allowed 943 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 944 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 945 946- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 947 Platforms can configure this if they need to lower the hardware 948 limit, for example due to asymmetric configuration or limitations of 949 software run at lower ELs. The default is the architectural maximum 950 of 2048 which should be suitable for most configurations, the 951 hardware will limit the effective VL to the maximum physically supported 952 VL. 953 954- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 955 Handoff using Transfer List defined in `Firmware Handoff specification`_. 956 This defaults to ``0``. Please note that this is an experimental feature 957 based on Firmware Handoff specification v0.9. 958 959- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 960 Random Number Generator Interface to BL31 image. This defaults to ``0``. 961 962- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 963 Boot feature. When set to '1', BL1 and BL2 images include support to load 964 and verify the certificates and images in a FIP, and BL1 includes support 965 for the Firmware Update. The default value is '0'. Generation and inclusion 966 of certificates in the FIP and FWU_FIP depends upon the value of the 967 ``GENERATE_COT`` option. 968 969 .. warning:: 970 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 971 already exist in disk, they will be overwritten without further notice. 972 973- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 974 specifies a file that contains the Trusted World private key in PEM 975 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 976 it will be used to save the key. 977 978- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 979 synchronous, (see "Initializing a BL32 Image" section in 980 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 981 synchronous method) or 1 (BL32 is initialized using asynchronous method). 982 Default is 0. 983 984- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 985 routing model which routes non-secure interrupts asynchronously from TSP 986 to EL3 causing immediate preemption of TSP. The EL3 is responsible 987 for saving and restoring the TSP context in this routing model. The 988 default routing model (when the value is 0) is to route non-secure 989 interrupts to TSP allowing it to save its context and hand over 990 synchronously to EL3 via an SMC. 991 992 .. note:: 993 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 994 must also be set to ``1``. 995 996- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 997 internal-trusted-storage) as SP in tb_fw_config device tree. 998 999- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1000 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1001 this delay. It can take values in the range (0-15). Default value is ``0`` 1002 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1003 Platforms need to explicitly update this value based on their requirements. 1004 1005- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1006 linker. When the ``LINKER`` build variable points to the armlink linker, 1007 this flag is enabled automatically. To enable support for armlink, platforms 1008 will have to provide a scatter file for the BL image. Currently, Tegra 1009 platforms use the armlink support to compile BL3-1 images. 1010 1011- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1012 memory region in the BL memory map or not (see "Use of Coherent memory in 1013 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1014 (Coherent memory region is included) or 0 (Coherent memory region is 1015 excluded). Default is 1. 1016 1017- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 1018 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 1019 Default is 0. 1020 1021- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1022 firmware configuration framework. This will move the io_policies into a 1023 configuration device tree, instead of static structure in the code base. 1024 1025- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1026 at runtime using fconf. If this flag is enabled, COT descriptors are 1027 statically captured in tb_fw_config file in the form of device tree nodes 1028 and properties. Currently, COT descriptors used by BL2 are moved to the 1029 device tree and COT descriptors used by BL1 are retained in the code 1030 base statically. 1031 1032- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1033 runtime using firmware configuration framework. The platform specific SDEI 1034 shared and private events configuration is retrieved from device tree rather 1035 than static C structures at compile time. This is only supported if 1036 SDEI_SUPPORT build flag is enabled. 1037 1038- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1039 and Group1 secure interrupts using the firmware configuration framework. The 1040 platform specific secure interrupt property descriptor is retrieved from 1041 device tree in runtime rather than depending on static C structure at compile 1042 time. 1043 1044- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1045 This feature creates a library of functions to be placed in ROM and thus 1046 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1047 is 0. 1048 1049- ``V``: Verbose build. If assigned anything other than 0, the build commands 1050 are printed. Default is 0. 1051 1052- ``VERSION_STRING``: String used in the log output for each TF-A image. 1053 Defaults to a string formed by concatenating the version number, build type 1054 and build string. 1055 1056- ``W``: Warning level. Some compiler warning options of interest have been 1057 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1058 each level enabling more warning options. Default is 0. 1059 1060 This option is closely related to the ``E`` option, which enables 1061 ``-Werror``. 1062 1063 - ``W=0`` (default) 1064 1065 Enables a wide assortment of warnings, most notably ``-Wall`` and 1066 ``-Wextra``, as well as various bad practices and things that are likely to 1067 result in errors. Includes some compiler specific flags. No warnings are 1068 expected at this level for any build. 1069 1070 - ``W=1`` 1071 1072 Enables warnings we want the generic build to include but are too time 1073 consuming to fix at the moment. It re-enables warnings taken out for 1074 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1075 to eventually be merged into ``W=0``. Some warnings are expected on some 1076 builds, but new contributions should not introduce new ones. 1077 1078 - ``W=2`` (recommended) 1079 1080 Enables warnings we want the generic build to include but cannot be enabled 1081 due to external libraries. This level is expected to eventually be merged 1082 into ``W=0``. Lots of warnings are expected, primarily from external 1083 libraries like zlib and compiler-rt, but new controbutions should not 1084 introduce new ones. 1085 1086 - ``W=3`` 1087 1088 Enables warnings that are informative but not necessary and generally too 1089 verbose and frequently ignored. A very large number of warnings are 1090 expected. 1091 1092 The exact set of warning flags depends on the compiler and TF-A warning 1093 level, however they are all succinctly set in the top-level Makefile. Please 1094 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1095 individual flags. 1096 1097- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1098 the CPU after warm boot. This is applicable for platforms which do not 1099 require interconnect programming to enable cache coherency (eg: single 1100 cluster platforms). If this option is enabled, then warm boot path 1101 enables D-caches immediately after enabling MMU. This option defaults to 0. 1102 1103- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1104 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1105 default value of this flag is ``no``. Note this option must be enabled only 1106 for ARM architecture greater than Armv8.5-A. 1107 1108- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1109 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1110 The default value of this flag is ``0``. 1111 1112 ``AT`` speculative errata workaround disables stage1 page table walk for 1113 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1114 produces either the correct result or failure without TLB allocation. 1115 1116 This boolean option enables errata for all below CPUs. 1117 1118 +---------+--------------+-------------------------+ 1119 | Errata | CPU | Workaround Define | 1120 +=========+==============+=========================+ 1121 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1122 +---------+--------------+-------------------------+ 1123 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1124 +---------+--------------+-------------------------+ 1125 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1126 +---------+--------------+-------------------------+ 1127 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1128 +---------+--------------+-------------------------+ 1129 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1130 +---------+--------------+-------------------------+ 1131 1132 .. note:: 1133 This option is enabled by build only if platform sets any of above defines 1134 mentioned in ’Workaround Define' column in the table. 1135 If this option is enabled for the EL3 software then EL2 software also must 1136 implement this workaround due to the behaviour of the errata mentioned 1137 in new SDEN document which will get published soon. 1138 1139- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1140 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1141 This flag is disabled by default. 1142 1143- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1144 host machine where a custom installation of OpenSSL is located, which is used 1145 to build the certificate generation, firmware encryption and FIP tools. If 1146 this option is not set, the default OS installation will be used. 1147 1148- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1149 functions that wait for an arbitrary time length (udelay and mdelay). The 1150 default value is 0. 1151 1152- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1153 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1154 optional architectural feature for AArch64. This flag can take the values 1155 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1156 and it is automatically disabled when the target architecture is AArch32. 1157 1158- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1159 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1160 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1161 feature for AArch64. This flag can take the values 0 to 2, to align with the 1162 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1163 disabled when the target architecture is AArch32. 1164 1165- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1166 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1167 but unused). This feature is available if trace unit such as ETMv4.x, and 1168 ETE(extending ETM feature) is implemented. This flag can take the values 1169 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0. 1170 1171- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1172 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1173 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1174 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1175 1176- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA 1177 APIs on platforms that doesn't support RSS (providing Arm CCA HES 1178 functionalities). When enabled (``1``), a mocked version of the APIs are used. 1179 The default value is 0. 1180 1181- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1182 ``plat_can_cmo`` which will return zero if cache management operations should 1183 be skipped and non-zero otherwise. By default, this option is disabled which 1184 means platform hook won't be checked and CMOs will always be performed when 1185 related functions are called. 1186 1187- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1188 firmware interface for the BL31 image. By default its disabled (``0``). 1189 1190- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1191 errata mitigation for platforms with a non-arm interconnect using the errata 1192 ABI. By default its disabled (``0``). 1193 1194- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1195 The platform will use PSA compliant Crypto APIs during authentication and 1196 image measurement process by enabling this option. It uses APIs defined as 1197 per the `PSA Crypto API specification`_. This feature is only supported if 1198 using MbedTLS 3.x version. By default it is disabled (``0``). 1199 1200- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1201 driver(s). By default it is disabled (``0``) because it constitutes an attack 1202 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1203 This option should only be enabled on a need basis if there is a use case for 1204 reading characters from the console. 1205 1206GICv3 driver options 1207-------------------- 1208 1209GICv3 driver files are included using directive: 1210 1211``include drivers/arm/gic/v3/gicv3.mk`` 1212 1213The driver can be configured with the following options set in the platform 1214makefile: 1215 1216- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1217 Enabling this option will add runtime detection support for the 1218 GIC-600, so is safe to select even for a GIC500 implementation. 1219 This option defaults to 0. 1220 1221- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1222 for GIC-600 AE. Enabling this option will introduce support to initialize 1223 the FMU. Platforms should call the init function during boot to enable the 1224 FMU and its safety mechanisms. This option defaults to 0. 1225 1226- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1227 functionality. This option defaults to 0 1228 1229- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1230 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1231 functions. This is required for FVP platform which need to simulate GIC save 1232 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1233 1234- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1235 This option defaults to 0. 1236 1237- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1238 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1239 1240Debugging options 1241----------------- 1242 1243To compile a debug version and make the build more verbose use 1244 1245.. code:: shell 1246 1247 make PLAT=<platform> DEBUG=1 V=1 all 1248 1249AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1250(for example Arm-DS) might not support this and may need an older version of 1251DWARF symbols to be emitted by GCC. This can be achieved by using the 1252``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1253the version to 4 is recommended for Arm-DS. 1254 1255When debugging logic problems it might also be useful to disable all compiler 1256optimizations by using ``-O0``. 1257 1258.. warning:: 1259 Using ``-O0`` could cause output images to be larger and base addresses 1260 might need to be recalculated (see the **Memory layout on Arm development 1261 platforms** section in the :ref:`Firmware Design`). 1262 1263Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1264``LDFLAGS``: 1265 1266.. code:: shell 1267 1268 CFLAGS='-O0 -gdwarf-2' \ 1269 make PLAT=<platform> DEBUG=1 V=1 all 1270 1271Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1272ignored as the linker is called directly. 1273 1274It is also possible to introduce an infinite loop to help in debugging the 1275post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1276``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1277section. In this case, the developer may take control of the target using a 1278debugger when indicated by the console output. When using Arm-DS, the following 1279commands can be used: 1280 1281:: 1282 1283 # Stop target execution 1284 interrupt 1285 1286 # 1287 # Prepare your debugging environment, e.g. set breakpoints 1288 # 1289 1290 # Jump over the debug loop 1291 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1292 1293 # Resume execution 1294 continue 1295 1296Firmware update options 1297----------------------- 1298 1299- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1300 in defining the firmware update metadata structure. This flag is by default 1301 set to '2'. 1302 1303- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1304 firmware bank. Each firmware bank must have the same number of images as per 1305 the `PSA FW update specification`_. 1306 This flag is used in defining the firmware update metadata structure. This 1307 flag is by default set to '1'. 1308 1309- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1310 `PSA FW update specification`_. The default value is 0, and this is an 1311 experimental feature. 1312 PSA firmware update implementation has some limitations, such as BL2 is 1313 not part of the protocol-updatable images, if BL2 needs to be updated, then 1314 it should be done through another platform-defined mechanism, and it assumes 1315 that the platform's hardware supports CRC32 instructions. 1316 1317-------------- 1318 1319*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 1320 1321.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1322.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1323.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1324.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1325.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1326.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1327.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1328