1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 49 SP nodes in tb_fw_config. 50 51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 53 54- ``BL2``: This is an optional build option which specifies the path to BL2 55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 56 built. 57 58- ``BL2U``: This is an optional build option which specifies the path to 59 BL2U image. In this case, the BL2U in TF-A will not be built. 60 61- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 63 entrypoint) or 1 (CPU reset to BL2 entrypoint). 64 The default value is 0. 65 66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 68 true in a 4-world system where RESET_TO_BL2 is 0. 69 70- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 72 73- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 75 the RW sections in RAM, while leaving the RO sections in place. This option 76 enable this use-case. For now, this option is only supported 77 when RESET_TO_BL2 is set to '1'. 78 79- ``BL31``: This is an optional build option which specifies the path to 80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 81 be built. 82 83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 84 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 85 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 86 87- ``BL32``: This is an optional build option which specifies the path to 88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 89 be built. 90 91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 92 Trusted OS Extra1 image for the ``fip`` target. 93 94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 95 Trusted OS Extra2 image for the ``fip`` target. 96 97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 98 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 99 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 100 101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 102 ``fip`` target in case TF-A BL2 is used. 103 104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 105 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 106 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 107 108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 110 If enabled, it is needed to use a compiler that supports the option 111 ``-mbranch-protection``. Selects the branch protection features to use: 112- 0: Default value turns off all types of branch protection 113- 1: Enables all types of branch protection features 114- 2: Return address signing to its standard level 115- 3: Extend the signing to include leaf functions 116- 4: Turn on branch target identification mechanism 117 118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 119 and resulting PAuth/BTI features. 120 121 +-------+--------------+-------+-----+ 122 | Value | GCC option | PAuth | BTI | 123 +=======+==============+=======+=====+ 124 | 0 | none | N | N | 125 +-------+--------------+-------+-----+ 126 | 1 | standard | Y | Y | 127 +-------+--------------+-------+-----+ 128 | 2 | pac-ret | Y | N | 129 +-------+--------------+-------+-----+ 130 | 3 | pac-ret+leaf | Y | N | 131 +-------+--------------+-------+-----+ 132 | 4 | bti | N | Y | 133 +-------+--------------+-------+-----+ 134 135 This option defaults to 0. 136 Note that Pointer Authentication is enabled for Non-secure world 137 irrespective of the value of this option if the CPU supports it. 138 139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 140 compilation of each build. It must be set to a C string (including quotes 141 where applicable). Defaults to a string that contains the time and date of 142 the compilation. 143 144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 145 build to be uniquely identified. Defaults to the current git commit id. 146 147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 148 149- ``CFLAGS``: Extra user options appended on the compiler's command line in 150 addition to the options set by the build system. 151 152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 153 release several CPUs out of reset. It can take either 0 (several CPUs may be 154 brought up) or 1 (only one CPU will ever be brought up during cold reset). 155 Default is 0. If the platform always brings up a single CPU, there is no 156 need to distinguish between primary and secondary CPUs and the boot path can 157 be optimised. The ``plat_is_my_cpu_primary()`` and 158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 159 to be implemented in this case. 160 161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 162 Defaults to ``tbbr``. 163 164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 165 register state when an unexpected exception occurs during execution of 166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 167 this is only enabled for a debug build of the firmware. 168 169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 170 certificate generation tool to create new keys in case no valid keys are 171 present or specified. Allowed options are '0' or '1'. Default is '1'. 172 173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 174 the AArch32 system registers to be included when saving and restoring the 175 CPU context. The option must be set to 0 for AArch64-only platforms (that 176 is on hardware that does not implement AArch32, or at least not at EL1 and 177 higher ELs). Default value is 1. 178 179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 180 registers to be included when saving and restoring the CPU context. Default 181 is 0. 182 183- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 184 Memory System Resource Partitioning and Monitoring (MPAM) 185 registers to be included when saving and restoring the CPU context. 186 Default is '0'. 187 188- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 189 registers to be saved/restored when entering/exiting an EL2 execution 190 context. This flag can take values 0 to 2, to align with the 191 ``FEATURE_DETECTION`` mechanism. Default value is 0. 192 193- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 194 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 195 to be included when saving and restoring the CPU context as part of world 196 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 197 mechanism. Default value is 0. 198 199 Note that Pointer Authentication is enabled for Non-secure world irrespective 200 of the value of this flag if the CPU supports it. 201 202- ``DEBUG``: Chooses between a debug and release build. It can take either 0 203 (release) or 1 (debug) as values. 0 is the default. 204 205- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 206 authenticated decryption algorithm to be used to decrypt firmware/s during 207 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 208 this flag is ``none`` to disable firmware decryption which is an optional 209 feature as per TBBR. 210 211- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 212 of the binary image. If set to 1, then only the ELF image is built. 213 0 is the default. 214 215- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 216 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 217 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 218 mechanism. Default is ``0``. 219 220- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 221 Board Boot authentication at runtime. This option is meant to be enabled only 222 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 223 flag has to be enabled. 0 is the default. 224 225- ``E``: Boolean option to make warnings into errors. Default is 1. 226 227 When specifying higher warnings levels (``W=1`` and higher), this option 228 defaults to 0. This is done to encourage contributors to use them, as they 229 are expected to produce warnings that would otherwise fail the build. New 230 contributions are still expected to build with ``W=0`` and ``E=1`` (the 231 default). 232 233- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 234 the normal boot flow. It must specify the entry point address of the EL3 235 payload. Please refer to the "Booting an EL3 payload" section for more 236 details. 237 238- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 239 (also known as group 1 counters). These are implementation-defined counters, 240 and as such require additional platform configuration. Default is 0. 241 242- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 243 allows platforms with auxiliary counters to describe them via the 244 ``HW_CONFIG`` device tree blob. Default is 0. 245 246- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 247 are compiled out. For debug builds, this option defaults to 1, and calls to 248 ``assert()`` are left in place. For release builds, this option defaults to 0 249 and calls to ``assert()`` function are compiled out. This option can be set 250 independently of ``DEBUG``. It can also be used to hide any auxiliary code 251 that is only required for the assertion and does not fit in the assertion 252 itself. 253 254- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 255 dumps or not. It is supported in both AArch64 and AArch32. However, in 256 AArch32 the format of the frame records are not defined in the AAPCS and they 257 are defined by the implementation. This implementation of backtrace only 258 supports the format used by GCC when T32 interworking is disabled. For this 259 reason enabling this option in AArch32 will force the compiler to only 260 generate A32 code. This option is enabled by default only in AArch64 debug 261 builds, but this behaviour can be overridden in each platform's Makefile or 262 in the build command line. 263 264- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 265 extensions. This flag can take the values 0 to 2, to align with the 266 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature 267 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 268 and this option can be used to enable this feature on those systems as well. 269 This flag can take the values 0 to 2, the default is 0. 270 271- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 272 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 273 onwards. This flag can take the values 0 to 2, to align with the 274 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 275 276- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 277 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 278 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 279 optional feature available on Arm v8.0 onwards. This flag can take values 280 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 281 Default value is ``0``. 282 283- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 284 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 285 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 286 and upwards. This flag can take the values 0 to 2, to align with the 287 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 288 289- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 290 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 291 Physical Offset register) during EL2 to EL3 context save/restore operations. 292 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 293 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 294 mechanism. Default value is ``0``. 295 296- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 297 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 298 Read Trap Register) during EL2 to EL3 context save/restore operations. 299 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 300 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 301 mechanism. Default value is ``0``. 302 303- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 304 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 305 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 306 mandatory architectural feature and is enabled from v8.7 and upwards. This 307 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 308 mechanism. Default value is ``0``. 309 310- ``ENABLE_FEAT_MTE``: Numeric value to enable Memory Tagging Extension 311 if the platform wants to use this feature in the Secure world and MTE is 312 enabled at ELX. This flag can take values 0 to 2, to align with the 313 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 314 315- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for 316 ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to 317 memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural 318 feature available from v8.9 and upwards. This flag can take the values 0 to 319 2, to align with the ``FEATURE_DETECTION`` mechanism. Default value is 320 ``0``. 321 322- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 323 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 324 permission fault for any privileged data access from EL1/EL2 to virtual 325 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 326 mandatory architectural feature and is enabled from v8.1 and upwards. This 327 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 328 mechanism. Default value is ``0``. 329 330- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 331 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 332 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 333 mechanism. Default value is ``0``. 334 335- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 336 extension. This feature is only supported in AArch64 state. This flag can 337 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 338 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 339 Armv8.5 onwards. 340 341- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 342 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 343 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 344 later CPUs. It is enabled from v8.5 and upwards and if needed can be 345 overidden from platforms explicitly. 346 347- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 348 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 349 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 350 mechanism. Default is ``0``. 351 352- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 353 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 354 available on Arm v8.6. This flag can take values 0 to 2, to align with the 355 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 356 357 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 358 delayed by the amount of value in ``TWED_DELAY``. 359 360- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 361 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 362 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 363 architectural feature and is enabled from v8.1 and upwards. It can take 364 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 365 Default value is ``0``. 366 367- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 368 allow access to TCR2_EL2 (extended translation control) from EL2 as 369 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 370 mandatory architectural feature and is enabled from v8.9 and upwards. This 371 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 372 mechanism. Default value is ``0``. 373 374- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 375 at EL2 and below, and context switch relevant registers. This flag 376 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 377 mechanism. Default value is ``0``. 378 379- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 380 at EL2 and below, and context switch relevant registers. This flag 381 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 382 mechanism. Default value is ``0``. 383 384- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 385 at EL2 and below, and context switch relevant registers. This flag 386 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 387 mechanism. Default value is ``0``. 388 389- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 390 at EL2 and below, and context switch relevant registers. This flag 391 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 392 mechanism. Default value is ``0``. 393 394- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 395 allow use of Guarded Control Stack from EL2 as well as adding the GCS 396 registers to the EL2 context save/restore operations. This flag can take 397 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 398 Default value is ``0``. 399 400- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 401 support in GCC for TF-A. This option is currently only supported for 402 AArch64. Default is 0. 403 404- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 405 feature. MPAM is an optional Armv8.4 extension that enables various memory 406 system components and resources to define partitions; software running at 407 various ELs can assign themselves to desired partition to control their 408 performance aspects. 409 410 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 411 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 412 access their own MPAM registers without trapping into EL3. This option 413 doesn't make use of partitioning in EL3, however. Platform initialisation 414 code should configure and use partitions in EL3 as required. This option 415 defaults to ``2`` since MPAM is enabled by default for NS world only. 416 The flag is automatically disabled when the target 417 architecture is AArch32. 418 419- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 420 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 421 firmware to detect and limit high activity events to assist in SoC processor 422 power domain dynamic power budgeting and limit the triggering of whole-rail 423 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 424 425- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 426 allows platforms with cores supporting MPMM to describe them via the 427 ``HW_CONFIG`` device tree blob. Default is 0. 428 429- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 430 support within generic code in TF-A. This option is currently only supported 431 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 432 in BL32 (SP_min) for AARCH32. Default is 0. 433 434- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 435 Measurement Framework(PMF). Default is 0. 436 437- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 438 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 439 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 440 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 441 software. 442 443- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 444 instrumentation which injects timestamp collection points into TF-A to 445 allow runtime performance to be measured. Currently, only PSCI is 446 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 447 as well. Default is 0. 448 449- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 450 extensions. This is an optional architectural feature for AArch64. 451 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 452 mechanism. The default is 2 but is automatically disabled when the target 453 architecture is AArch32. 454 455- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 456 (SVE) for the Non-secure world only. SVE is an optional architectural feature 457 for AArch64. Note that when SVE is enabled for the Non-secure world, access 458 to SIMD and floating-point functionality from the Secure world is disabled by 459 default and controlled with ENABLE_SVE_FOR_SWD. 460 This is to avoid corruption of the Non-secure world data in the Z-registers 461 which are aliased by the SIMD and FP registers. The build option is not 462 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 463 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 464 enabled. This flag can take the values 0 to 2, to align with the 465 ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be 466 used on systems that have SPM_MM enabled. The default is 1. 467 468- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 469 SVE is an optional architectural feature for AArch64. Note that this option 470 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 471 automatically disabled when the target architecture is AArch32. 472 473- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 474 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 475 default value is set to "none". "strong" is the recommended stack protection 476 level if this feature is desired. "none" disables the stack protection. For 477 all values other than "none", the ``plat_get_stack_protector_canary()`` 478 platform hook needs to be implemented. The value is passed as the last 479 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 480 481- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 482 flag depends on ``DECRYPTION_SUPPORT`` build flag. 483 484- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 485 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 486 487- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 488 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 489 on ``DECRYPTION_SUPPORT`` build flag. 490 491- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 492 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 493 build flag. 494 495- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 496 deprecated platform APIs, helper functions or drivers within Trusted 497 Firmware as error. It can take the value 1 (flag the use of deprecated 498 APIs as error) or 0. The default is 0. 499 500- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 501 configure an Arm® Ethos™-N NPU. To use this service the target platform's 502 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 503 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 504 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 505 506- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 507 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 508 ``TRUSTED_BOARD_BOOT`` to be enabled. 509 510- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 511 (```ethosn.bin```). This firmware image will be included in the FIP and 512 loaded at runtime. 513 514- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 515 targeted at EL3. When set ``0`` (default), no exceptions are expected or 516 handled at EL3, and a panic will result. The exception to this rule is when 517 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 518 occuring during normal world execution, are trapped to EL3. Any exception 519 trapped during secure world execution are trapped to the SPMC. This is 520 supported only for AArch64 builds. 521 522- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 523 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 524 Default value is 40 (LOG_LEVEL_INFO). 525 526- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 527 injection from lower ELs, and this build option enables lower ELs to use 528 Error Records accessed via System Registers to inject faults. This is 529 applicable only to AArch64 builds. 530 531 This feature is intended for testing purposes only, and is advisable to keep 532 disabled for production images. 533 534- ``FIP_NAME``: This is an optional build option which specifies the FIP 535 filename for the ``fip`` target. Default is ``fip.bin``. 536 537- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 538 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 539 540- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 541 542 :: 543 544 0: Encryption is done with Secret Symmetric Key (SSK) which is common 545 for a class of devices. 546 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 547 unique per device. 548 549 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 550 551- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 552 tool to create certificates as per the Chain of Trust described in 553 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 554 include the certificates in the FIP and FWU_FIP. Default value is '0'. 555 556 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 557 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 558 the corresponding certificates, and to include those certificates in the 559 FIP and FWU_FIP. 560 561 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 562 images will not include support for Trusted Board Boot. The FIP will still 563 include the corresponding certificates. This FIP can be used to verify the 564 Chain of Trust on the host machine through other mechanisms. 565 566 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 567 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 568 will not include the corresponding certificates, causing a boot failure. 569 570- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 571 inherent support for specific EL3 type interrupts. Setting this build option 572 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 573 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 574 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 575 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 576 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 577 the Secure Payload interrupts needs to be synchronously handed over to Secure 578 EL1 for handling. The default value of this option is ``0``, which means the 579 Group 0 interrupts are assumed to be handled by Secure EL1. 580 581- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 582 Interrupts, resulting from errors in NS world, will be always trapped in 583 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 584 will be trapped in the current exception level (or in EL1 if the current 585 exception level is EL0). 586 587- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 588 software operations are required for CPUs to enter and exit coherency. 589 However, newer systems exist where CPUs' entry to and exit from coherency 590 is managed in hardware. Such systems require software to only initiate these 591 operations, and the rest is managed in hardware, minimizing active software 592 management. In such systems, this boolean option enables TF-A to carry out 593 build and run-time optimizations during boot and power management operations. 594 This option defaults to 0 and if it is enabled, then it implies 595 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 596 597 If this flag is disabled while the platform which TF-A is compiled for 598 includes cores that manage coherency in hardware, then a compilation error is 599 generated. This is based on the fact that a system cannot have, at the same 600 time, cores that manage coherency in hardware and cores that don't. In other 601 words, a platform cannot have, at the same time, cores that require 602 ``HW_ASSISTED_COHERENCY=1`` and cores that require 603 ``HW_ASSISTED_COHERENCY=0``. 604 605 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 606 translation library (xlat tables v2) must be used; version 1 of translation 607 library is not supported. 608 609- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 610 implementation defined system register accesses from lower ELs. Default 611 value is ``0``. 612 613- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 614 bottom, higher addresses at the top. This build flag can be set to '1' to 615 invert this behavior. Lower addresses will be printed at the top and higher 616 addresses at the bottom. 617 618- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 619 used for generating the PKCS keys and subsequent signing of the certificate. 620 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 621 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 622 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 623 compatibility. The default value of this flag is ``rsa`` which is the TBBR 624 compliant PKCS#1 RSA 2.1 scheme. 625 626- ``KEY_SIZE``: This build flag enables the user to select the key size for 627 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 628 depend on the chosen algorithm and the cryptographic module. 629 630 +---------------------------+------------------------------------+ 631 | KEY_ALG | Possible key sizes | 632 +===========================+====================================+ 633 | rsa | 1024 , 2048 (default), 3072, 4096 | 634 +---------------------------+------------------------------------+ 635 | ecdsa | 256 (default), 384 | 636 +---------------------------+------------------------------------+ 637 | ecdsa-brainpool-regular | unavailable | 638 +---------------------------+------------------------------------+ 639 | ecdsa-brainpool-twisted | unavailable | 640 +---------------------------+------------------------------------+ 641 642- ``HASH_ALG``: This build flag enables the user to select the secure hash 643 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 644 The default value of this flag is ``sha256``. 645 646- ``LDFLAGS``: Extra user options appended to the linkers' command line in 647 addition to the one set by the build system. 648 649- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 650 output compiled into the build. This should be one of the following: 651 652 :: 653 654 0 (LOG_LEVEL_NONE) 655 10 (LOG_LEVEL_ERROR) 656 20 (LOG_LEVEL_NOTICE) 657 30 (LOG_LEVEL_WARNING) 658 40 (LOG_LEVEL_INFO) 659 50 (LOG_LEVEL_VERBOSE) 660 661 All log output up to and including the selected log level is compiled into 662 the build. The default value is 40 in debug builds and 20 in release builds. 663 664- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 665 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 666 provide trust that the code taking the measurements and recording them has 667 not been tampered with. 668 669 This option defaults to 0. 670 671- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 672 options to the compiler. An example usage: 673 674 .. code:: make 675 676 MARCH_DIRECTIVE := -march=armv8.5-a 677 678- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 679 options to the compiler currently supporting only of the options. 680 GCC documentation: 681 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 682 683 An example usage: 684 685 .. code:: make 686 687 HARDEN_SLS := 1 688 689 This option defaults to 0. 690 691- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 692 specifies a file that contains the Non-Trusted World private key in PEM 693 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 694 will be used to save the key. 695 696- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 697 optional. It is only needed if the platform makefile specifies that it 698 is required in order to build the ``fwu_fip`` target. 699 700- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 701 contents upon world switch. It can take either 0 (don't save and restore) or 702 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 703 wants the timer registers to be saved and restored. 704 705- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in 706 tb_fw_config device tree. This flag is defined only when 707 ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp. 708 709- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 710 for the BL image. It can be either 0 (include) or 1 (remove). The default 711 value is 0. 712 713- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 714 the underlying hardware is not a full PL011 UART but a minimally compliant 715 generic UART, which is a subset of the PL011. The driver will not access 716 any register that is not part of the SBSA generic UART specification. 717 Default value is 0 (a full PL011 compliant UART is present). 718 719- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 720 must be subdirectory of any depth under ``plat/``, and must contain a 721 platform makefile named ``platform.mk``. For example, to build TF-A for the 722 Arm Juno board, select PLAT=juno. 723 724- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 725 each core as well as the global context. The data includes the memory used 726 by each world and each privileged exception level. This build option is 727 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 728 729- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 730 instead of the normal boot flow. When defined, it must specify the entry 731 point address for the preloaded BL33 image. This option is incompatible with 732 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 733 over ``PRELOADED_BL33_BASE``. 734 735- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 736 vector address can be programmed or is fixed on the platform. It can take 737 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 738 programmable reset address, it is expected that a CPU will start executing 739 code directly at the right address, both on a cold and warm reset. In this 740 case, there is no need to identify the entrypoint on boot and the boot path 741 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 742 does not need to be implemented in this case. 743 744- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 745 possible for the PSCI power-state parameter: original and extended State-ID 746 formats. This flag if set to 1, configures the generic PSCI layer to use the 747 extended format. The default value of this flag is 0, which means by default 748 the original power-state format is used by the PSCI implementation. This flag 749 should be specified by the platform makefile and it governs the return value 750 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 751 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 752 set to 1 as well. 753 754- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 755 OS-initiated mode. This option defaults to 0. 756 757- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 758 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 759 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 760 NOTE: This flag enables use of IESB capability to reduce entry latency into 761 EL3 even when RAS error handling is not performed on the platform. Hence this 762 flag is recommended to be turned on Armv8.2 and later CPUs. 763 764- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 765 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 766 entrypoint) or 1 (CPU reset to BL31 entrypoint). 767 The default value is 0. 768 769- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 770 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 771 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 772 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 773 774- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 775 file that contains the ROT private key in PEM format or a PKCS11 URI and 776 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 777 accepted and it will be used to save the key. 778 779- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 780 certificate generation tool to save the keys used to establish the Chain of 781 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 782 783- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 784 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 785 target. 786 787- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 788 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 789 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 790 791- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 792 optional. It is only needed if the platform makefile specifies that it 793 is required in order to build the ``fwu_fip`` target. 794 795- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 796 Delegated Exception Interface to BL31 image. This defaults to ``0``. 797 798 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 799 set to ``1``. 800 801- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 802 isolated on separate memory pages. This is a trade-off between security and 803 memory usage. See "Isolating code and read-only data on separate memory 804 pages" section in :ref:`Firmware Design`. This flag is disabled by default 805 and affects all BL images. 806 807- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 808 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 809 allocated in RAM discontiguous from the loaded firmware image. When set, the 810 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 811 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 812 sections are placed in RAM immediately following the loaded firmware image. 813 814- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 815 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 816 discontiguous from loaded firmware images. When set, the platform need to 817 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 818 flag is disabled by default and NOLOAD sections are placed in RAM immediately 819 following the loaded firmware image. 820 821- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 822 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 823 UEFI+ACPI this can provide a certain amount of OS forward compatibility 824 with newer platforms that aren't ECAM compliant. 825 826- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 827 This build option is only valid if ``ARCH=aarch64``. The value should be 828 the path to the directory containing the SPD source, relative to 829 ``services/spd/``; the directory is expected to contain a makefile called 830 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 831 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 832 cannot be enabled when the ``SPM_MM`` option is enabled. 833 834- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 835 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 836 execution in BL1 just before handing over to BL31. At this point, all 837 firmware images have been loaded in memory, and the MMU and caches are 838 turned off. Refer to the "Debugging options" section for more details. 839 840- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 841 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 842 component runs at the EL3 exception level. The default value is ``0`` ( 843 disabled). This configuration supports pre-Armv8.4 platforms (aka not 844 implementing the ``FEAT_SEL2`` extension). 845 846- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 847 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 848 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 849 850- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 851 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 852 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 853 mechanism should be used. 854 855- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 856 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 857 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 858 extension. This is the default when enabling the SPM Dispatcher. When 859 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 860 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 861 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 862 extension). 863 864- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 865 Partition Manager (SPM) implementation. The default value is ``0`` 866 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 867 enabled (``SPD=spmd``). 868 869- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 870 description of secure partitions. The build system will parse this file and 871 package all secure partition blobs into the FIP. This file is not 872 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 873 874- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 875 secure interrupts (caught through the FIQ line). Platforms can enable 876 this directive if they need to handle such interruption. When enabled, 877 the FIQ are handled in monitor mode and non secure world is not allowed 878 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 879 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 880 881- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 882 Platforms can configure this if they need to lower the hardware 883 limit, for example due to asymmetric configuration or limitations of 884 software run at lower ELs. The default is the architectural maximum 885 of 2048 which should be suitable for most configurations, the 886 hardware will limit the effective VL to the maximum physically supported 887 VL. 888 889- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 890 Random Number Generator Interface to BL31 image. This defaults to ``0``. 891 892- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 893 Boot feature. When set to '1', BL1 and BL2 images include support to load 894 and verify the certificates and images in a FIP, and BL1 includes support 895 for the Firmware Update. The default value is '0'. Generation and inclusion 896 of certificates in the FIP and FWU_FIP depends upon the value of the 897 ``GENERATE_COT`` option. 898 899 .. warning:: 900 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 901 already exist in disk, they will be overwritten without further notice. 902 903- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 904 specifies a file that contains the Trusted World private key in PEM 905 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 906 it will be used to save the key. 907 908- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 909 synchronous, (see "Initializing a BL32 Image" section in 910 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 911 synchronous method) or 1 (BL32 is initialized using asynchronous method). 912 Default is 0. 913 914- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 915 routing model which routes non-secure interrupts asynchronously from TSP 916 to EL3 causing immediate preemption of TSP. The EL3 is responsible 917 for saving and restoring the TSP context in this routing model. The 918 default routing model (when the value is 0) is to route non-secure 919 interrupts to TSP allowing it to save its context and hand over 920 synchronously to EL3 via an SMC. 921 922 .. note:: 923 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 924 must also be set to ``1``. 925 926- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 927 internal-trusted-storage) as SP in tb_fw_config device tree. 928 929- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 930 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 931 this delay. It can take values in the range (0-15). Default value is ``0`` 932 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 933 Platforms need to explicitly update this value based on their requirements. 934 935- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 936 linker. When the ``LINKER`` build variable points to the armlink linker, 937 this flag is enabled automatically. To enable support for armlink, platforms 938 will have to provide a scatter file for the BL image. Currently, Tegra 939 platforms use the armlink support to compile BL3-1 images. 940 941- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 942 memory region in the BL memory map or not (see "Use of Coherent memory in 943 TF-A" section in :ref:`Firmware Design`). It can take the value 1 944 (Coherent memory region is included) or 0 (Coherent memory region is 945 excluded). Default is 1. 946 947- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 948 firmware configuration framework. This will move the io_policies into a 949 configuration device tree, instead of static structure in the code base. 950 951- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 952 at runtime using fconf. If this flag is enabled, COT descriptors are 953 statically captured in tb_fw_config file in the form of device tree nodes 954 and properties. Currently, COT descriptors used by BL2 are moved to the 955 device tree and COT descriptors used by BL1 are retained in the code 956 base statically. 957 958- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 959 runtime using firmware configuration framework. The platform specific SDEI 960 shared and private events configuration is retrieved from device tree rather 961 than static C structures at compile time. This is only supported if 962 SDEI_SUPPORT build flag is enabled. 963 964- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 965 and Group1 secure interrupts using the firmware configuration framework. The 966 platform specific secure interrupt property descriptor is retrieved from 967 device tree in runtime rather than depending on static C structure at compile 968 time. 969 970- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 971 This feature creates a library of functions to be placed in ROM and thus 972 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 973 is 0. 974 975- ``V``: Verbose build. If assigned anything other than 0, the build commands 976 are printed. Default is 0. 977 978- ``VERSION_STRING``: String used in the log output for each TF-A image. 979 Defaults to a string formed by concatenating the version number, build type 980 and build string. 981 982- ``W``: Warning level. Some compiler warning options of interest have been 983 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 984 each level enabling more warning options. Default is 0. 985 986 This option is closely related to the ``E`` option, which enables 987 ``-Werror``. 988 989 - ``W=0`` (default) 990 991 Enables a wide assortment of warnings, most notably ``-Wall`` and 992 ``-Wextra``, as well as various bad practices and things that are likely to 993 result in errors. Includes some compiler specific flags. No warnings are 994 expected at this level for any build. 995 996 - ``W=1`` 997 998 Enables warnings we want the generic build to include but are too time 999 consuming to fix at the moment. It re-enables warnings taken out for 1000 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1001 to eventually be merged into ``W=0``. Some warnings are expected on some 1002 builds, but new contributions should not introduce new ones. 1003 1004 - ``W=2`` (recommended) 1005 1006 Enables warnings we want the generic build to include but cannot be enabled 1007 due to external libraries. This level is expected to eventually be merged 1008 into ``W=0``. Lots of warnings are expected, primarily from external 1009 libraries like zlib and compiler-rt, but new controbutions should not 1010 introduce new ones. 1011 1012 - ``W=3`` 1013 1014 Enables warnings that are informative but not necessary and generally too 1015 verbose and frequently ignored. A very large number of warnings are 1016 expected. 1017 1018 The exact set of warning flags depends on the compiler and TF-A warning 1019 level, however they are all succinctly set in the top-level Makefile. Please 1020 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1021 individual flags. 1022 1023- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1024 the CPU after warm boot. This is applicable for platforms which do not 1025 require interconnect programming to enable cache coherency (eg: single 1026 cluster platforms). If this option is enabled, then warm boot path 1027 enables D-caches immediately after enabling MMU. This option defaults to 0. 1028 1029- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1030 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1031 default value of this flag is ``no``. Note this option must be enabled only 1032 for ARM architecture greater than Armv8.5-A. 1033 1034- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1035 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1036 The default value of this flag is ``0``. 1037 1038 ``AT`` speculative errata workaround disables stage1 page table walk for 1039 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1040 produces either the correct result or failure without TLB allocation. 1041 1042 This boolean option enables errata for all below CPUs. 1043 1044 +---------+--------------+-------------------------+ 1045 | Errata | CPU | Workaround Define | 1046 +=========+==============+=========================+ 1047 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1048 +---------+--------------+-------------------------+ 1049 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1050 +---------+--------------+-------------------------+ 1051 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1052 +---------+--------------+-------------------------+ 1053 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1054 +---------+--------------+-------------------------+ 1055 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1056 +---------+--------------+-------------------------+ 1057 1058 .. note:: 1059 This option is enabled by build only if platform sets any of above defines 1060 mentioned in ’Workaround Define' column in the table. 1061 If this option is enabled for the EL3 software then EL2 software also must 1062 implement this workaround due to the behaviour of the errata mentioned 1063 in new SDEN document which will get published soon. 1064 1065- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1066 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1067 This flag is disabled by default. 1068 1069- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1070 host machine where a custom installation of OpenSSL is located, which is used 1071 to build the certificate generation, firmware encryption and FIP tools. If 1072 this option is not set, the default OS installation will be used. 1073 1074- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1075 functions that wait for an arbitrary time length (udelay and mdelay). The 1076 default value is 0. 1077 1078- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1079 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1080 optional architectural feature for AArch64. This flag can take the values 1081 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1082 and it is automatically disabled when the target architecture is AArch32. 1083 1084- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1085 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1086 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1087 feature for AArch64. This flag can take the values 0 to 2, to align with the 1088 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1089 disabled when the target architecture is AArch32. 1090 1091- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1092 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1093 but unused). This feature is available if trace unit such as ETMv4.x, and 1094 ETE(extending ETM feature) is implemented. This flag can take the values 1095 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0. 1096 1097- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1098 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1099 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1100 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1101 1102- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1103 ``plat_can_cmo`` which will return zero if cache management operations should 1104 be skipped and non-zero otherwise. By default, this option is disabled which 1105 means platform hook won't be checked and CMOs will always be performed when 1106 related functions are called. 1107 1108- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1109 firmware interface for the BL31 image. By default its disabled (``0``). 1110 1111- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1112 errata mitigation for platforms with a non-arm interconnect using the errata 1113 ABI. By default its disabled (``0``). 1114 1115- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1116 driver(s). By default it is disabled (``0``) because it constitutes an attack 1117 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1118 This option should only be enabled on a need basis if there is a use case for 1119 reading characters from the console. 1120 1121GICv3 driver options 1122-------------------- 1123 1124GICv3 driver files are included using directive: 1125 1126``include drivers/arm/gic/v3/gicv3.mk`` 1127 1128The driver can be configured with the following options set in the platform 1129makefile: 1130 1131- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1132 Enabling this option will add runtime detection support for the 1133 GIC-600, so is safe to select even for a GIC500 implementation. 1134 This option defaults to 0. 1135 1136- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1137 for GIC-600 AE. Enabling this option will introduce support to initialize 1138 the FMU. Platforms should call the init function during boot to enable the 1139 FMU and its safety mechanisms. This option defaults to 0. 1140 1141- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1142 functionality. This option defaults to 0 1143 1144- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1145 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1146 functions. This is required for FVP platform which need to simulate GIC save 1147 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1148 1149- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1150 This option defaults to 0. 1151 1152- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1153 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1154 1155Debugging options 1156----------------- 1157 1158To compile a debug version and make the build more verbose use 1159 1160.. code:: shell 1161 1162 make PLAT=<platform> DEBUG=1 V=1 all 1163 1164AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1165(for example Arm-DS) might not support this and may need an older version of 1166DWARF symbols to be emitted by GCC. This can be achieved by using the 1167``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1168the version to 4 is recommended for Arm-DS. 1169 1170When debugging logic problems it might also be useful to disable all compiler 1171optimizations by using ``-O0``. 1172 1173.. warning:: 1174 Using ``-O0`` could cause output images to be larger and base addresses 1175 might need to be recalculated (see the **Memory layout on Arm development 1176 platforms** section in the :ref:`Firmware Design`). 1177 1178Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1179``LDFLAGS``: 1180 1181.. code:: shell 1182 1183 CFLAGS='-O0 -gdwarf-2' \ 1184 make PLAT=<platform> DEBUG=1 V=1 all 1185 1186Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1187ignored as the linker is called directly. 1188 1189It is also possible to introduce an infinite loop to help in debugging the 1190post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1191``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1192section. In this case, the developer may take control of the target using a 1193debugger when indicated by the console output. When using Arm-DS, the following 1194commands can be used: 1195 1196:: 1197 1198 # Stop target execution 1199 interrupt 1200 1201 # 1202 # Prepare your debugging environment, e.g. set breakpoints 1203 # 1204 1205 # Jump over the debug loop 1206 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1207 1208 # Resume execution 1209 continue 1210 1211.. _build_options_experimental: 1212 1213Experimental build options 1214--------------------------- 1215 1216Common build options 1217~~~~~~~~~~~~~~~~~~~~ 1218 1219- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1220 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1221 the measurements and recording them as per `PSA DRTM specification`_. For 1222 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1223 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1224 should have mechanism to authenticate BL31. This option defaults to 0. 1225 1226- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1227 Management Extension. This flag can take the values 0 to 2, to align with 1228 the ``FEATURE_DETECTION`` mechanism. Default value is 0. 1229 1230- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1231 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1232 registers so are enabled together. Using this option without 1233 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1234 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1235 superset of SVE. SME is an optional architectural feature for AArch64. 1236 At this time, this build option cannot be used on systems that have 1237 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1238 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 1239 mechanism. Default is 0. 1240 1241- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1242 version 2 (SME2) for the non-secure world only. SME2 is an optional 1243 architectural feature for AArch64. 1244 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1245 accesses will still be trapped. This flag can take the values 0 to 2, to 1246 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 1247 1248- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1249 Extension for secure world. Used along with SVE and FPU/SIMD. 1250 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1251 Default is 0. 1252 1253- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1254 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1255 for logical partitions in EL3, managed by the SPMD as defined in the 1256 FF-A v1.2 specification. This flag is disabled by default. This flag 1257 must not be used if ``SPMC_AT_EL3`` is enabled. 1258 1259- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1260 detection mechanism. It detects whether the Architectural features enabled 1261 through feature specific build flags are supported by the PE or not by 1262 validating them either at boot phase or at runtime based on the value 1263 possessed by the feature flag (0 to 2) and report error messages at an early 1264 stage. This flag will also enable errata ordering checking for ``DEBUG`` 1265 builds. 1266 1267 This prevents and benefits us from EL3 runtime exceptions during context save 1268 and restore routines guarded by these build flags. Henceforth validating them 1269 before their usage provides more control on the actions taken under them. 1270 1271 The mechanism permits the build flags to take values 0, 1 or 2 and 1272 evaluates them accordingly. 1273 1274 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 1275 1276 :: 1277 1278 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 1279 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 1280 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 1281 1282 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 1283 0, feature is disabled statically during compilation. If it is defined as 1, 1284 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 1285 implemented by the PE, a hard panic is generated. Finally, if the flag is set 1286 to 2, feature is validated at runtime. 1287 1288 Note that the entire implementation is divided into two phases, wherein as 1289 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 1290 supported and is planned to be handled explicilty in phase-2 implementation. 1291 1292 ``FEATURE_DETECTION`` macro is disabled by default. Platforms can explicitly 1293 make use of this by mechanism, by enabling it to validate whether they have 1294 set their build flags properly at an early phase. 1295 1296- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1297 The platform will use PSA compliant Crypto APIs during authentication and 1298 image measurement process by enabling this option. It uses APIs defined as 1299 per the `PSA Crypto API specification`_. This feature is only supported if 1300 using MbedTLS 3.x version. It is disabled (``0``) by default. 1301 1302- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1303 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1304 This defaults to ``0``. Current implementation follows the Firmware Handoff 1305 specification v0.9. 1306 1307- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1308 interface through BL31 as a SiP SMC function. 1309 Default is disabled (0). 1310 1311Firmware update options 1312~~~~~~~~~~~~~~~~~~~~~~~ 1313 1314- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1315 `PSA FW update specification`_. The default value is 0. 1316 PSA firmware update implementation has few limitations, such as: 1317 1318 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1319 be updated, then it should be done through another platform-defined 1320 mechanism. 1321 1322 - It assumes the platform's hardware supports CRC32 instructions. 1323 1324- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1325 in defining the firmware update metadata structure. This flag is by default 1326 set to '2'. 1327 1328- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1329 firmware bank. Each firmware bank must have the same number of images as per 1330 the `PSA FW update specification`_. 1331 This flag is used in defining the firmware update metadata structure. This 1332 flag is by default set to '1'. 1333 1334-------------- 1335 1336*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 1337 1338.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1339.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1340.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1341.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1342.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1343.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1344.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1345